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In electronic-warfare (EW) receiver applications, real-time measurement of the radar signals' carrier frequencies is mandatory and considered to be one of the most important radar parameters. Accurate frequency detection can be used to sort and deinterleave signals in a dense signal environment where multiple signals arrive simultaneously presenting severe problems unless they can be differentiated appropriately. Researchers and engineers are actively looking for new algorithms for high resolution wideband receivers with easier implementation. This paper presents an adaptive gain control and dynamic thresholding wideband digital receiver to accurately detect two simultaneous high dynamic range signals, even when their signal frequencies are very close. The proposed fast Fourier transform (FFT) based receiver examines incoming signal characteristics and provides real-time accomplishment of these tasks, by way of using an adaptive gain-control amplifier, a squarer, two analog-to-digital converters, and two FFT's. The wideband receiver offers high probability of intercept over wide instantaneous RF bandwidths, high dynamic ranges and sensitivity. Two simultaneous signal accommodations and their characteristics are provided to demonstrate the improvements over presently used receivers in this field.

Multi-region multi-sector energy-economic models are often used to analyze long-term scenarios of energy development, however, these models usually rely on a simplified representation of technological details in power generation. To strengthen this representation, we develop a method for modeling the economic competition between different advanced technologies in multi-region multi-sector dynamic energy-economic models based on a markup approach, which represents the measure of the cost of a technology relative to the price received for electricity generation. The markup includes capital costs, fixed and variable operating and maintenance (O&M) costs, fuel costs, and transmission and distribution (T&D) costs. For intermittent technologies, it also includes a backup requirement to make these technologies effectively dispatchable. For carbon capture and storage (CCS) technologies, it also includes the costs of CO2 capture, transportation and storage. We provide a standardized markup calculation for generation technologies for different regions of the world, including USA, China, India, EU, Japan and others. Then we analyze the sensitivity of the calculation to critical inputs, including capital costs, fuel costs, carbon prices and capacity factors. We provide a detailed calculation of the relative costs of the following technologies: new pulverized coal, new pulverized coal with CCS, natural gas combined cycle, natural gas with CCS, biomass-fueled plant, biomass with CCS, advanced nuclear, wind (for small and medium penetration levels), solar, wind with backup (for large penetration levels), co-firing of coal and biomass combined with CCS, and advanced CCS on natural gas. For illustration, we incorporate the markups into the MIT Economic Projection and Policy Analysis (EPPA) model, a global multi-sector multi-sector dynamic energy-economic model with a detailed representation of power generation technologies, and run several scenarios. Our analysis and results provide insight on the deployment of different low-carbon power generation technologies depending on assumptions about carbon policy stringency.

Single crystals of mercurous halide were grown by physical vapor transport method (PVT). The orientation and the crystalline quality of the grown crystals were determined using high resolution x-ray diffraction (HRXRD) technique. The full width at half maximum (FWHM) of the grown mercurous bromide crystals was measured to be 0.13 degrees for (004) reflection, which is the best that has been achieved so far for PVT grown mercurous halide single crystals. The extended defects of the crystals were also analyzed using high resolution x-ray diffraction topography. Preliminary studies were carried out to evaluate the performance of the crystals on acousto-optic modulator (AOM) and gamma-ray detector applications. The results indicate the grown mercurous halide crystals are excellent materials for acousto-optic modulator device fabrication. The diffraction efficiencies of the fabricated AOM device with 1152 and 1523 nm wavelength lasers polarizing parallel to the acoustic wave were found to be 35% and 28%, respectively. The results also indicate the grown crystals are a promising material for gamma-ray detector application with a very high energy resolution of 1.86% FWHM.

The use of chirp signals in modern radar and ranging systems have numerous benefits. They are extensively used to improve signal-to-noise ratio and range resolution. The performance capabilities of these signals are directly related to their time-bandwidth product, i.e., the duration and bandwidth of the pulse. Ultra-wideband chirp signals are further desirable because they span a large bandwidth, making them resistant to narrowband environmental interference. The accurate detection and measurement of high chirp signals is difficult due to the necessity of a high-sampling analog-digital converter, a target measurement platform with high computational power, and a time-of-arrival (TOA) estimator with high temporal resolution. The difficulty of the problem is further compounded with the requirement that no a priori knowledge of the signal, noise, or operating environment is known. This paper presents a practical approach and implementation of a high linear chirp rate receiver and TOA estimator pair capable of detecting and measuring stationary radio frequency pulses as well as linear chirp rates up to 1.18 GHz in 400 ns. The high-resolution TOA algorithm and linear chirp receiver have been prototyped, synthesized, and placed and routed for a Virtex 6 SX475 FPGA.

The fact that Sn-Cu reaction rate is much faster than Sn-Ni reaction and releasing much more gibbs free energy causing Sn prefers to have reaction with Cu instead of Ni. Moreover, at the temperature below 170°C, Sn side-wall reaction rate is larger than IMC formation rate at the temperature below 200 °C because the long distance Sn side-wall migration is faster than Cu traveling through to center Sn. This makes Sn in the micro-bump favors to flow to the Cu side-wall to have side-wall reaction during the high temperature (maximum 170 °C) storage process (HTS). This will result in large voids formed at the center of the micro-bump after HTS, causing malfunction of the product. Therefore, detail DOEs needs to be done to evaluate the reaction rate mentioned above in order to design a highly reliable microbump that can last over 3000 hours under HTS test.

A classic second-order coupled-capacitor Chebyshev bandpass filter using resonator of tunable active capacitor and inductor is presented. The low cost and small size of CMOS active components make the bandpass filter (BPF) attractive in fully integrated CMOS applications. The tunable active capacitor is designed to compensate active inductor’s resistance for resistive match in the resonator. In many design cases, more than 95% resistive loss is cancelled. Meanwhile, adjusting design parameter of the active component provides BPF tunability in center frequency, pass band, and pass band gain. Designed in 1.8 V 180 nanometer CMOS process, the BPF has a tuning frequency range of 758–864 MHz, a controllable pass band of 7.1–65.9 MHz, a quality factor Q of 12–107, a pass band gain of 6.5–18.1 dB, and a stopband rejection of 38–50 dB.

This paper investigates a wireless-powered cooperative network (WPCN) consisting of one source-destination pair and multiple decode-and-forward (DF) relays. We consider that the DF relays are wireless-powered such that they rely only on the harvested energy from the source to perform information forwarding. Furthermore, these relays are equipped with separate energy and information receivers as well as energy storage to accumulate the harvested energy. In this paper, we develop an energy threshold based multi-relay selection (ETMRS) scheme for the considered WPCN, in which each relay determines to switch between energy harvesting and information forwarding modes in a fully distributed manner. By modeling the charging/discharging of the discrete-level battery at each relay as a finite state Markov Chain (MC), we derive a closed-form expression for the system outage probability of the proposed ETMRS scheme over independent but not necessarily identical Rayleigh fading channels. Numerical results validate our theoretical analysis and show that the proposed ETMRS scheme can outperform the existing single-relay selection scheme, especially when the source's transmission rate is relatively high.

Dynamic CMOS circuits are significantly used in high-performance very large-scale integrated (VLSI) systems. However, they suffer from limitations such as noise tolerance, charge leakage, and power consumption. With the escalating impact of process variations on design performance, aggressive technology scaling, noise in dynamic CMOS circuit has become an imperative design challenge. The design performance of dynamic circuits has to be first improved for reliable operation of VLSI systems. Alongside, this impact of process variation is worse in circuits with multiple timing paths such as those used in microprocessors. In this paper, these problems of process variations, timing, noise tolerance, and power are investigated together for performance optimization. We propose a process variation-aware load-balance of multiple paths transistor sizing algorithm to: 1) improve worst-case delay, delay uncertainty, and sensitivity due to process variations in dynamic CMOS circuits, and 2) optimize dynamic CMOS circuits with MOSFET-based keepers to improve the noise tolerance. Implemented using 90-nm CMOS process, the proposed algorithm has demonstrated an average improvement in worst-case delay by 34%, delay uncertainty by 40.3%, delay sensitivity by 25.1%, and noise margins by 19.4% when compared to their initial performances.

A 2.56-gigasample-per-second (GSPS) fixed-point fixed-precision dynamic kernel function fast Fourier transform (FFT) with a variable truncation scheme (VTS) is designed for real-time wideband signal detection. Using an Atmel 10-bit analog-to-digital converter (ADC), the two-tone real-time signal detection is verified for a bandwidth of 1.14 GHz with 20-MHz channelization and output throughput rates of 50 ns. The proposed design has an averaged single-signal spurious-free dynamic range (SFDR) of 27.7 dB and the ability to detect a weak input signal at -45 dBm. The overall dynamic range (DR) of the system is 40.6 dB. This is possible for a fixed-precision FFT design due to the embedded VTS to extend the total DR while preserving the instantaneous DR (IDR) relationship. In addition, with an ideal 8-bit ADC, the averaged single-signal SFDR of 32.60 dB and the two-tone signal IDR of 22 dB are achieved. The overall DR is 48.3 dB. The dynamic kernel FFT uses about 57% of the slices available on a Xilinx XC4VSX55 Virtex 4 field-programmable gate array (FPGA). In comparison with alternative implementations based on Xilinx LogicCORE 256-point IP FFT for 8-bit data, the processing time and the overall DR are considerably superior. Additional case studies that applying the windowing function and the Taylor-series-based square root approximation show favorable results utilizing the VTS for real-time data acquisition and signal-enhancement algorithms for computing high-bit-width data while minimizing the hardware.

High densities of impurities and defects lead to severe charge-carrier trapping that can be major issues in assuring the high performance of CZT detectors. For some medical-imaging applications, the typical X-ray flux can be very high. Under such high irradiation conditions, the trapped charge builds up inside the detector affecting its stability. This phenomenon generally is termed the polarization effect. We conducted detailed studies on polarization in CZT crystals employing a highly collimated synchrotron X-ray radiation source available at Brookhaven's National Synchrotron Light Source (NSLS). We were able to induce polarization effects by irradiating specific areas within the detector. These measurements allowed us to make, for the first time, a quantitative comparison between areas where polarization is induced, and the electron- and hole-collection X-ray maps obtained at low flux, where no polarization is induced. We discuss the results of these polarization studies.

This paper presents a 4-b low-power, low-voltage flash analog-to-digital converter (ADC). The proposed ADC is pipelined and mainly consists of three stages: 1) track-and-hold (T/H); 2)differential comparator; and 3) differential cascode voltage switch with pass gates (DCVSPG) encoder. The T/H uses a current-mode dual-array structure to reduce the aperture jitter for high-input signal frequency. The differential comparator eliminates the use of the resistor ladder circuit by generating the reference voltages internally. The DCVSPG encoder has a full output signal swing and compact logic design style of pass gate circuits, which makes it suitable for high sampling frequency. The DCVSPG encoder reduces the power consumption by a factor of 88% as compared with the conventional ROM encoder. The ADC is designed in 130-nm CMOS technology. Fast Fourier transform tests prove proper operation of the ADC sampled at 2.5 GHz for the input signal frequency up to 1 GHz

As a modern radar receiver must rapidly search a large frequency range with maximum sensitivity, capabilities such as high instantaneous dynamic range (IDR), good multiple-signal-detection capability, wider bandwidth (BW), and high-frequency resolution are indispensable. Many techniques proposed to improve digital wideband receiver performance are computationally intensive and limit their real-time performance due to hardware constraint. In this paper, an innovative three gigasample-per-second hybrid computing platform digital wideband receiver system is presented, which employs two Nvidia Tesla C2050 graphics processor units and a Xilinx Virtex-5 field-programmable gate array for hardware acceleration to drastically improve receiver performance over its predecessor designs. The receiver detects five simultaneous signals in 1.25-GHz BW (125-1375 MHz) with a maximum IDR of 42.5 dB and a frequency resolution of 0.5 MHz. The proposed receiver architecture achieves high-resolution spectral estimation and employs a hardware mechanism for multiple-signal detection before the next set of data arrives for processing.

A data path consists of memory elements (i.e., registers), data operators (i.e. ALUs) and interconnection units (i.e. buses) to control the data transfers in the digital system. Many approaches to hardware allocation for data path synthesis have been proposed in the literature; however, only single-port memory is considered for register allocation and no efficient synthesis approach for multiport memory synthesis. A novel design methodology for data path synthesis using multiport memories is proposed which can be applied to hardware allocation algorithms or to already synthesized data path as a postprocessor to achieve a better design. Illustrations of applying this method to different synthesis examples are presented. Results and improvements over previous techniques are demonstrated. Experiments on benchmarks show very promising results.

This paper describes the design and intricacies of a wideband digital chirp receiver utilizing a one-bit ADC (Analog to Digital Converter) to measure the carrier frequency and chirp rate of unknown received signals which have very high chip rates. The core of the chirp receiver is composed of monobit IFM receivers which are low cost and very accurate.

Design and implementation of a modern radar receiver that is capable of rapidly searching a large frequency range with maximum sensitivity in real time presents a challenge. Such a receiver not only has stringent operational requirements like high instantaneous dynamic range (IDR), multiple signal detection capability, wider bandwidth and also high frequency resolution. Currently, operating speeds of digital processors are not on par with state-of-the-art ADCs. To overcome this impediment, researchers are exploring methods of offloading the computational intensive tasks to specialized hardware accelerators. A 3 giga-sample-per-second (GSPS) wideband digital receiver system implemented on a unique hybrid computing platform, which is composed of two Tesla C2050 GPUs and a Xilinx Virtex-5 FPGA, is presented. Drastically improving its performance over its predecessors, the proposed receiver system detects five simultaneous signals in 1.25 GHz bandwidth (125–1375 MHz) with a maximum IDR of 42.5 dB and a frequency resolution of 0.5 MHz. The proposed receiver architecture performs a high-resolution spectral estimation and employs a hardware efficient platform for detecting multiple signals before the next set of buffered data arrives for processing.

Performance variation is one of the primary concerns in nanoscale CMOS circuits. This performance variation is worse in circuits with multiple timing paths such as those used in microprocessors. In this paper, a Process Variation-aware, Transistor (PVT) sizing algorithm is proposed, which is capable of reducing worst-case delay, delay uncertainty, and delay sensitivity to process variations in nanoscale CMOS circuits. The proposed algorithm is based on identifying the significance of timing paths in a design, and performing respective optimization for optimal design performance. Additional advantages in this algorithm include its simplicity, accuracy, independent of the transistor order, and initial sizing factors. Using 90 nm CMOS process, the proposed algorithm has demonstrated an average improvement in worst-case delay by 36.9%, delay uncertainty by 44.1%, delay sensitivity by 19.8%, and power-delay-product by 35.3% when compared to their initial performances.

Performance variation is one of the primary concerns in nanometer-scale dynamic CMOS circuits. This performance variation is worse in circuits with multiple timing paths such as those used in microprocessors. In this paper, a Process Variation-aware Transistor (PVT) sizing algorithm is proposed, which is capable of significantly reducing worst-case delay, delay uncertainty, and delay sensitivity to process variations in dynamic CMOS circuits. The proposed algorithm is based on identifying the significance of all timing paths in the design, increasing the sizes of transistors that appear in most number of paths to reduce delays of most paths. In parallel, it minimizes the channel load by reducing the size of transistors in the interacting paths, which will lead to a power saving. Additional advantages in this algorithm include its simplicity, accuracy, independent of the transistor order, and initial sizing factors. Using 90 nm CMOS process, the proposed algorithm has demonstrated an average improvement in worst-case delay by 36.9%, delay uncertainty by 44.1%, delay sensitivity by 19.8%, and power-delay-product by 35.3% when compared to their initial performances.

A 2.048 GSPS fixed-point fixed-precision dynamic kernel function FFT processor with variable truncation scheme (VTS) is proposed and implemented for real-time wideband signal detection. Using Xilinx System Generator, single-signal detection is demonstrated for a bandwidth of 912 MHz with 16 MHz channelization and output throughput rates of 62.5 ns. The proposed design has an averaged single-signal spurious-free dynamic range (SFDR) of 26 dB and the ability to detect a weak input signal utilizing only the often truncated least significant bits of the analog-to-digital converter. This is possible for a fixed-precision FFT design due to the embedded variable truncation scheme to extend the total dynamic range (DR) while preserving the SFDR relationship. Additional case studies utilizing different dynamic kernel function and inter-stage precision shows important area and performance trade-offs when utilized in a high-speed wideband FFT processor without the use of decimators.

A pulsed laser method is used to map the charge collection amplitude and electron mobility-lifetime product (μ e τ e ) in Cd 1−x Zn x Te (x = 0.1) pieces especially selected to include regions with crystallographic defects. Additionally, ultrasound imaging is used in conjunction with X-ray diffraction in order to localize and analyze the defects. The defect regions studied include twins, misoriented secondary grains, and Te inclusions. Specific defect types were observed to degrade the local charge collection efficiency with a characteristic magnitude and spatial distribution. Coherent grain boundaries associated with the twin were less affecting than high angle, incoherent boundary associated with second grains. We consider the feasibility of in-line inspection at an early stage of device manufacture by 2D mapping of electron transport properties over large CZT wafer sizes.

A novel thresholding technique is presented for digital channelized receiver to minimize second signal false alarm. The additional constraint placed for signal detection improves the false alarm rate with minimal hardware increase due to the simplicity of the proposed algorithm. Preliminary dual-tone signal analysis with instantaneous dynamic range (IDR) from −12 to −20 dB shows favorable second signal detection rates with no false alarms reported based on 53760 samples per test. The implemented digital receiver samples at 2.048 GHz on Xilinx Virtex 4 field programmable gate array (FPGA) with output throughput rate of 62.5 ns. Exhaustive evaluation of fifty-eight 16 MHz channels includes signals not centered on the frequency bin, which also shows favorable detection results.

Cadmium zinc telluride (CZT) surface protection through chemical encapsulation is critical for making reliable pixellated radiation detectors. Epoxy based photoimageable solder mask has been found to be an effective coating material for protecting bare CZT surfaces. Solder mask coating has a couple of functions depending on surface areas coated, and on detector manufacturing and application processes. Firstly, solder mask applied on the pixellated anode surface with opening patterns on electrode pads could provide packaging guidance when conductive epoxy or solder ball is used for CZT substrate — printed circuit board (PCB) attachment. Secondly, solder mask provides excellent protection to CZT bare surfaces from mechanical scratching, moisture penetration, and chemical attack. In addition, solder mask provides excellent electrical isolation between interpixel gaps, anode to cathode edges, and between shielding cathode and semiconductor substrate. In this paper, gamma ray spectral responses and leakage current — voltage characteristics of CZT pixellated detectors encapsulated with solder mask were extensively studied. Solder mask coatings were applied on detectors with various shapes, sizes, and pixel patterns. Encapsulated detector showed stable and reliable performances. It was concluded that epoxy based solder mask was an excellent encapsulating material for CZT radiation detectors.

CdZnTe (or CZT) crystals can be used in a variety of detector-type applications. This large band gap material shows great promise for use as a gamma radiation spectrometer. Historically, the performance of CZT has typically been adversely affected by point defects, structural and compositional heterogeneities within the crystals, such as twinning, pipes, grain boundaries (polycrystallinity) and secondary phases (SP). The synthesis of CZT material has improved greatly with the primary performance limitation being attributed to mainly SP. In this presentation, we describe the extensive characterization of detector grade material that has been treated with post growth annealing to remove the SPs. Some of the analytical methods used in this study included polarized, cross polarized and transmission IR imaging, I-V curves measurements, synchrotron X-ray topography and electron microscopy.

The complexity of timing optimization has been increasing rapidly in proportion to the shrinking CMOS device size, due to the increased number of channel-connected transistors in a path, and the rising magnitude of process variations. These significant challenges can be addressed through the implementation of designs with an optimal balance between static and dynamic circuits. This paper presents a process variation-aware path oriented in time (POINT) optimization flow for mixed-static-dynamic CMOS logic designs, where a design is partitioned into static and dynamic circuits based on timing critical paths. Implemented on a 64-b adder and ISCAS benchmark circuits, the POINT optimization flow demonstrated an average improvement in delay by 44% and average improvement in delay uncertainty from process variations by 37% in comparison with a state-of-the-art commercial optimization tool.

A 2.56 giga sample per second (GSPS) fixed-point fixed-precision dynamic kernel function fast Fourier transform (FFT) with variable truncation scheme is designed for real-time wideband signal detection. This design is verified for two-tone signal detection in a bandwidth of 1.14 GHz at 20 MHz intervals with output throughput rates of 50 ns. The dynamic kernel FFT uses about 32 % of the slices available on the Xilinx Virtex 4 FPGA model XC4VSX55 onboard the Delphi ADC3255 with an Atmel 10-bit analog to digital converter (ADC). The proposed design has an averaged single signal spurious-free dynamic range (SFDR) of 40.6 dB and the ability to detect a weak input signal at -45 dBm. This is possible for a fixed-precision FFT design due to the embedded variable truncation scheme. In addition, with an ideal 8-bit ADC, averaged single signal SFDR performance of 47.60 dB and two-tone signal instantaneous dynamic range (IDR) of 32.60 dB are achieved. The two-tone signal IDR is the ratio between the strong and weak signal inputs in the time domain. The high throughput rates and single signal SFDR have performed better than Xilinx LogicCOREtrade 256-point IP FFT's throughput rate of 4.827 to 5.119 mus and single-tone SFDR of 25- 30 dB for an 8-bit input.

A real-time architecture to the Hilbert transform is presented for an implemented digital instantaneous frequency measurement (IFM) receiver to avoid the suspension of data acquisition during signal processing due to input buffer constraints. The ability to continuously process incoming signals allows constant monitoring of the spectrum under interest, which is critical for radar signal tracking. Architectural improvements yield a 99.5% reduction in the amount of hardware used for storage and processing for the Hilbert transform component alone. Data throughput rate of the Hilbert transform increased by a factor of eighty from a single bitstream at 32 mega bits per second (Mbps) to eight bitstreams at 320 Mbps each. The maximum combined throughput rate possible of all eight channels after place and route is estimated at 4264 Mbps and verified for 3200 Mbps. Prior to the modifications, the digital IFM is capable of classifying continuous or short pulse wave signal of 1.2 GHz bandwidth with a major frequency detection error within 2 MHz for every 100 nsec 95.92% of the time.

A major challenge in the design of microprocessor circuits is transistor sizing in dynamic CMOS logic due to increased number of channel-connected transistors on various paths of the design, and increased magnitude of process variations in the nanometer process. This paper proposes a process variation aware transistor sizing algorithm for dynamic CMOS logic. The efficiency of this algorithm is illustrated first by a 2-b weighted binary-to-thermometric converter, of which the critical path delay was optimized from 355 to 157 ps which accounts for a 55.77% delay improvement, and the delay uncertainty due to process variation was optimized by 60.75%. A 4-b unity weight binary-to-thermometric converter was also optimized, of which the critical path delay was reduced from 152 to 103 ps which accounts for a 32.23% delay improvement, and delay uncertainty was optimized by 63.6%. Applying the proposed timing optimization algorithm to a mixed-dynamic-static CMOS 64-bit adder, the critical path delay and the power-delay-product were optimized to 632 ps and 84.17 pJ, respectively.

The complexity in timing optimization of high performance microprocessors has been increasing with the number of channel-connected transistors in various paths of dynamic CMOS circuits and the rising magnitude of process variations in nanometer CMOS process. In this paper, a process variation aware transistor sizing algorithm for dynamic CMOS circuits while considering the Load Balance of Multiple Paths (LBMP) is proposed. The proposed iterative optimization algorithm is a deterministic approach and is illustrated first by a 2-b weighted binary-to-thermometric converter (WBTC) and of which the critical path was optimized from an initial delay of 355 ps to an optimal delay of 157 ps, which accounts for a 55.77% delay improvement. A 4-b unity weight binary-to-thermometric converter (UWBTC) was also designed and of which the critical path was optimized from an initial delay of 152 ps to an optimal delay of 103 ps, which accounts for a 32.23% delay improvement. Finally, a 64-b parallel binary adder was partitioned to a mixed dynamic-static CMOS style and the critical path and the power delay product were optimized to 632 ps and 84.17 pJ respectively.

The focus of this paper is to evaluate thick, 20 X 20 X 10 and 10 X 10 X 10 mm(3), cadmium zinc telluride (CZT), Cd0.9Zn0.1Te, crystals grown using the traveling heater method (THIM). The phenomenal spectral performance and small size and low concentration of Te inclusions/precipitates of these crystals indicate that the THM is suitable for the mass production of CZT radiation detectors that can be used in a variety of applications. Our result also proves that with careful material selection using IR and high-quality fabrication processes, the theoretical energy resolution limit can be achieved.

Due to the increased importance of speed on microprocessor circuits, the complexity in transistor sizing for timing optimization increases due to channel-connected transistors on various paths of the design. In this paper, an efficient approach to transistor sizing of dynamic CMOS circuits for timing optimization while considering the load balance of multiple paths, named LBMP, is proposed. The iterative optimization algorithm is a deterministic approach and illustrated first by a 2-b weighted binary-to-thermometric converter (BTC), of which the critical path is optimized from an initial delay of 287.57 ps to an optimal delay of 161.37 ps which accounts for a 43.9% delay improvement. Then by a 64-b adder partitioned to a mixed dynamic-static style, the critical path is optimized to 686.11 ps and the power delay product is optimized to 91.6ps

A low-power 1.25-GHz signal bandwidth 4-bit ADC designed in a standard 130 nanometer digital CMOS process for high spurious-free dynamic range (SFDR) wideband communications is presented. The ADC uses new clocked digital comparators designed by a dynamic offset suppression technique. The SFDR and ENOB of this 4-bit ADC achieve 31.44 dB and 3.75 bits at input signal of 39 MHz. Near Nyquist frequency input signals, the SFDR and ENOB maintains above 22.79 dB and 2.37 bits at input signal of 1.23 GHz. This ADC has a latency of two and half clock cycles, a low input capacitance of 300 fF, and a low power consumption of 7.9 mW at a 2.5 GHz conversion rate operating down to 120 mV. The ADC has a figure-of-merit (FoM) of 0.611 pJ per conversion step.

This paper presents a low-cost low-power self-test design and verification of on-chip analog-to-digital converter (ADC) for System-on-a-Chip (SoC) applications. A methodology for performing mixed-mode built-in self-test (BIST) simulation was performed along with the BIST architecture. The architecture presented allows for generation of analog test signals of frequency up to 600 MHz, using a 4-b 2.5 Gsamples/s current steering digital-to-analog converter (DAC). Both integral nonlinearity (INL) and differential nonlinearity (DNL ) errors of test signals were obtained about 0.5 LSB by the sine wave histogram testing. The measured power dissipation for generated test signals of 600 MHz at the power supply of 1.2 V is about 5.32 mW. The current steering DAC achieves 22.3 dB of spur free dynamic range (SFDR) for 600 MHz signals.

In this paper, we investigate the possible methods of generating circles and arcs on an active matrix liquid crystal display (AMLCD) within a custom graphics engine called enhanced system integrated graphic hardware topography II (ENSIGHT II). Research is done to choose the best possible method of generating complete circles and arcs. An algorithm utilizing Bresenham's circle algorithm with thirteen different clipping modes is developed, implemented and placed accordingly inside of ENSIGHT II. To prove the algorithm is working as described, simulation is performed and then demonstrated with an Altera XA10 FPGA Development Board and a Toshiba 6.3" AMLCD

This paper presents a design synthesis and performance measurement of a 4-bit pipelined flash analog-to-digital converter (ADC). The preliminary results show the ADC in 130 nanometer CMOS. CMOS technology has superior performance of sampling rate of 2.5 GHz for input signal bandwidth of 1 GHz. For the purpose of design reuse, a general architecture and synthesis flow of the ADC is proposed. One of such work is about solution of a long-standing open problem on the design synthesis of high-performance ADC

This paper presents a 4-bit high-speed, low-power, pipelined flash analog-to-digital converter (ADC). The proposed ADC is pipelined and mainly consists of three stages: 1) track-and-hold (T/H), 2) differential comparator, and 3) differential cascode voltage switch with pass gates (DCVSPG) encoder. The T/H uses a current mode, dual-array structure to reduce the aperture jitter for high input frequency. The differential comparator eliminates the use of a resistor ladder circuit by generating the reference voltages internally. The DCVSPG encoder has a full output signal swing and compact logic design style of pass gate circuits which makes it suitable for high sampling frequency. The DCVSPG encoder reduces the power consumption by a factor of 88% as compared to the conventional ROM encoder. The ADC is designed in 130 nm CMOS technology. FFT tests prove proper operation of the ADC sampled at 2.5 GHz for an input signal frequency up to 1 GHz.

Due to the increasing level of integration achieved by Very Large Scale Integrated (VLSI) technology, traditional gate-level fault simulation becomes more complex, difficult, and costly. Behavioral fault simulation at top functional level, described in a hardware description language, offers very attractive alternatives to these problems. This paper presents a new way to simulate the behavioral fault models for the Very high speed integrated circuits Hardware Description Language (VHDL). The performance analysis shows that relatively small number of test patterns generated by the behavioral fault simulation and Automatic Test Pattern Generation (ATPG) system detects around 98 percent of all testable gate-level faults. >

An ASIC for a wide band (1 GHz) digital monobit receiver designed for processing two simultaneous signals will be described. The receiver consists of three major elements: (1) a nonlinear radio frequency (RF) front-end, (2) a signal sampler and formatting system (analog-to-digital converter (ADC) and demultiplexers), and (3) a monobit algorithm implemented as an ASIC for signal detection and frequency measurement. The receiver uses a two-bit ADC operating at 2.5 GHz whose outputs are collected and formatted by demultiplexers for presentation to the ASIC. The ASIC has two basic functions: (1) perform a fast Fourier transform (FFT) and (2) determine the number of signals and report their frequencies.

Undoped CdSe single crystals were investigated by current- voltage measurement and low temperature photoluminescence. Crystal quality and surface morphology were also studied by optical microscopy and scanning electron microscopy. Together with gamma spectroscopy, the results show that the CdSe crystals have high resistivities in the 1010 (Omega) (DOT)cm range. This indicates their usefulness for room temperature nuclear radiation detection. Small active volume CdSe detector were fabricated and their performance is presented. A comparison of fundamental material properties between CdSe and CdZnTe detectors is also given.© (1998) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Pd/SiC has been used as a high temperature hydrocarbon and hydrogen gas sensor in environmental and aeronautical applications. In this work, the relationships between diffusion, reaction, and interfacial chemical composition with electrical properties for Pd ultra-thin films on 6H-SiC (∼< 30Å) are studied at different annealing temperatures.Ultra-thin film Pd on 6H-SiC has been prepared by the RF sputtering method. The Schottky barrier heights are measured by XPS for an unannealed sample and samples annealed from 100°C to 400°C for 30 minutes, respectively. No significant change in the Schottky barrier height of the Pd/SiC contact was found in the temperature range. The morphology from UHV-STM and AFM show that the unannealed Pd thin film had good uniformity across the SiC substrate, and the Pd has dispersed, and then partially aggregated into rounded shaped precipitates with increasing annealing temperatures. At 400°C, all Pd metal has reacted and formed to silicides. From XPS, Pd2Si was found on the surface after annealing, and almost all Pd has reacted to become Pd2Si after annealing at 400°C. No other silicide was found. The intensity of Pd on XPS decreases enormously at 400°C. This is explained if Pd has diffused into SiC. The Pd diffusion and the formation of Pd silicides do not significantly affect the Schottky barrier height. The SiO2 was found at the top of surface after annealing, and increased in amount with increasing annealing temperature. The SiO2 formation was accelerated by the presence of Pd. Pd may play a role in absorbing oxygen, and activating Si from SiC to form SiO2.Key Words: Pd thin film, SiC, X-ray photoelectron spectroscopy, scanning tunneling microscopy, and atomic force microscopy.

The optical, electrical and surface properties of mercuric iodide platelets grown from solution in a HgI2-HI-H2O system were investigated by comparing them with Physical Vapor Transport (PVT) grown crystals. The absence of bulk imperfections and the uniformity of the as-grown surfaces and the KI solution etched surfaces were confirmed by optical microscopy. The as-grown surface uniformity is higher for solution grown crystals than that of PVT crystals, since the platelets do not have to be cleaved or polished. AFM studies show that the roughness for the cleaved, aged and etched surfaces were 0.06 nm, 0.48 nm and 0.3 nm respectively. Low temperature photoluminescence properties were measured for the two kind of crystals and will be discussed. However, I-V curves give higher current density and lower apparent resistivity values for the solution grown than for PVT grown crystals. Correlations between optical and surface quality as well as the electrical properties of the crystals grown from both solution and PVT methods are also discussed.

A bilateral supplementary comparison of resistance, APMP.EM-S6, was conducted between the National Institute of Metrology Thailand (NIMT) and the CSIRO National Measurement Laboratory of Australia (NML). The comparison covered seven values of resistance, 0.1 Ω, 1 Ω, 100 Ω, 10 kΩ, 100 kΩ, 1 MΩ and 100 MΩ. The 0.1 Ω resistor was a YEW type 2792, the 100 MΩ resistor was an IET type SRC and the other five resistors were Fluke type 742A. The resistors were supplied by NIMT, and NML was the pilot laboratory for the comparison. The measurements for the comparison were made between December 2003 and April 2004. The resistors were measured on three separate occasions by NIMT and between each of these occasions the resistors were sent to NML for measurement. The resistors of nominal values 0.1 Ω, 1 Ω, 100 Ω and 10 kΩ were measured as four-terminal resistors while the 100 kΩ, 1 MΩ and 100 MΩ resistors were measured as two-terminal resistors. The quantity En (the absolute value of the difference between the values obtained at the two laboratories divided by the root sum square of the expanded uncertainties of the two values) was calculated for each resistance value used in the comparison. In all cases En was less than 0.5. Main text. To reach the main text of this paper, click on Final Report. Note that this text is that which appears in Appendix B of the BIPM key comparison database kcdb.bipm.org/. The final report has been peer-reviewed and approved for publication by the APMP, according to the provisions of the Mutual Recognition Arrangement (MRA).