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As the safety-critical applications (e.g. automotive and medical electronics) emerge, various techniques of radiation hardening by design (RHBD) are proposed to deal with soft errors. Among all RHBD techniques, Built-In Soft-Error Resilience (BISER) is the first one to apply the delayed latching to separate input signals on all flip-flops for error detection. However, the delay values induced by BISER extend the setup time of all flip-flops, and may fail to meet the timing specification of the design. For minimizing such delay impact on the setup time of each flip-flop, we propose the Automated Latching-Delay Assignment (ALDA) to transfer partial values to the CK-Q delay. Later, Time-Borrowable D-Flip-Flop (TBD-FF) as well as a modified design flow is also proposed to realize the delay assignment by ALDA and to complete the design hardening. Experiments show that ALDA together with TBD-FF effectively protects four benchmark circuits against soft errors, and optimally avoids the timing violations caused by the prior delayed-latching solutions.

In advanced technology nodes, SRAM cells, used in the aerospace industry, have become highly susceptible to soft-error. In this brief, a Soft-Error-Aware Read-Decoupled 14T (SAR14T) SRAM cell is proposed for aerospace applications. To assess the performance of the proposed cell, it is compared with other soft-error-aware SRAM cells, like WE-QUATRO, QUCCE12T, RHD12T, RSP14T and RHBD14T. Simulation results show that all the sensitive nodes of SAR14T can reattain their initial states after being impacted by soft-error. Furthermore, the cell is capable of recovering from multi-node upset induced at its internal node-pair. Due to the employment of the read-decoupling technique, SAR14T shows the highest read stability compared to its peers. The proposed cell also proves to be the superior SRAM in terms of write ability and write delay. All these improvements are accomplished at the expense of a slightly longer read delay.

Conventional flip‐flops are more vulnerable to particle strikes in a radiation environment. To overcome this disadvantage, in the literature, many radiation‐hardened flip‐flops (FFs) based on techniques like triple modular redundancy, dual interlocked cell, Quatro and guard‐gated Quatro cell, and so on, are discussed. The flip‐flop realized using radiation hardened by design Quatro cell is named as the improved version of Quatro flip‐flop (IVQFF). Single event upset (SEU) at inverter stages of master/slave and at output are the two drawbacks of IVQFF. This study proposes a guard‐gated Quatro FF (GQFF) using guard‐gated Quatro cell and Muller C‐element. To overcome the SEU at inverter stages of IVQFF, in GQFF, the inverter stages are realized in a parallel fashion. A dual‐input Muller C‐element is connected to the GQFF output stage to mask the SEU and thus maintain the correct output. The proposed GQFF tolerates both single node upset (SNU) and double node upset (DNU). It also achieves low power. To prove the efficacy, GQFF and the existing FFs are implemented in 45 nm Complementary Metal Oxide Semiconductor (CMOS) technology. From the simulation results, it may be noted that the GQFF is 100% immune to SNUs and 50% immune to DNUs.

CMOS circuits based on scaled transistors are typically more susceptible to soft errors caused by energetic particles in the radiation environment than circuits employing their large-area counterparts. In this paper, a soft error tolerant latch built on a Schmitt trigger, which is entirely realized with NMOS transistors with an additional voltage booster, which we refer to as NST-VB, is proposed. To evaluate the circuits’ radiation resilience, we identify the most sensitive nodes by analyzing the critical charges at the various latches’ internal sensitive nodes. We also examine the linear energy transfer (LET) of the essential latches and observe that the NST-VB latch has an improved LET of $$0.386~\mathrm {MeV~cm^2/mg}$$ as compared to $$0.231~\mathrm {MeV~cm^2/mg}$$ and $$0.365~\mathrm {MeV~cm^2/mg}$$ for unhardened latch and ST latch, respectively. For the process variation analysis, we further examined 5k Monte Carlo simulations to analyze the impact of device variability on our design and observe that the proposed NST-VB latch has $$1.96\times $$ less variability critical voltage concerning the ST latch. Further, the logic flipping probability for NST-VB latch is 48.32% compared to 53.04% for ST latch. Also, the critical charge to power delay area product ratio (QPAR) is calculated and evaluated for the proposed latch’s effectiveness compared to other considered latches.

International audience; To meet the requirements of both costeffectiveness and high reliability for low-orbit aerospace applications, this paper first presents a radiation hardened latch design, namely HLCRT. The latch mainly consists of a single-node-upset self-recoverable cell, a 3input C-element, and an inverter. If any two inputs of the C-element suffer from a double-node-upset (DNU), or if one node inside the cell together with another node outside the cell suffer from a DNU, the latch still has a correct value on its output node, i.e., the latch is effectively DNU hardened. Based on the latch, this paper also presents a flip-flop, namely HLCRT-FF that can tolerate SNUs and DNUs. Simulation results demonstrate the SNU/DNU tolerance capability of the proposed HLCRT latch and HLCRT-FF. Moreover, due to the use of a few transistors, clock gating technologies, and high-speed paths, the proposed HLCRT latch and HLCRT-FF approximately save 61% and 92% of delay, 45% and 55% of power, 28% and 28% of area, and 84% and 97% of delay-power-area product on average, compared to state-of-the-art DNU hardened latch/flip-flop designs, respectively.

This article provides a review of semiconductor based ionising radiation sensors to measure accumulated dose and detect individual strikes of ionising particles. The measurement of ionising radiation (γ-ray, X-ray, high energy UV-ray and heavy ions, etc.) is essential in several critical reliability applications such as medical, aviation, space missions and high energy physics experiments considering safety and quality assurance. In the last few decades, numerous techniques based on semiconductor devices such as diodes, metal-oxide-semiconductor field-effect transistors (MOSFETs) and solid-state photomultipliers (SSPMs), etc., have been reported to estimate the absorbed dose of radiation with sensitivity varying by several orders of magnitude from μGy to MGy. In addition, the mitigation of soft errors in integrated circuits essentially requires detection of charged particle induced transients and digital bit-flips in storage elements. Depending on the particle energies, flux and the application requirements, several sensing solutions such as diodes, static random access memory (SRAM) and NAND flash, etc., are reported in the literature. This article goes through the evolution of radiation dosimeters and particle detectors implemented using semiconductor technologies and summarises the features with emphasis on their underlying principles and applications. In addition, this article performs a comparison of the different methodologies while mentioning their advantages and limitations.

With aggressive scaling of transistor size and supply voltage, the critical charge of the sensitive nodes is reducing rapidly. As a result, when these deep submicron devices are used in memory cells in the space environment, single-event upsets (SEUs), also known as soft-errors, pose a great threat to the reliability of the cells. To mitigate the effects of SEUs, we propose a soft-error-immune read-stability-improved (SIRI) SRAM cell. To assess the performance of the proposed cell, it is compared with other soft-error-immune SRAM cells, namely, QUCCE12T, WE-QUATRO, RHPD12T, RHBD14T and RSP14T. Simulation results confirm that the detrimental effects of SEUs do not alter the state of SIRI as all the sensitive nodes can reattain their initial states after being impacted by an SEU. The cell can also recover from single-event multi-node upsets (SEMNUs) that occur at its storage node-pair. Moreover, the storage nodes of the proposed cell are isolated from the bitlines during read operation. Hence, it exhibits the highest read stability. The write ability and write delay of SIRI are also superior to those of the majority of the comparison cells, and it consumes much lower hold power than many of the conventional SRAM cells. All these improvements are brought about only at the expense of a slightly longer read delay.

As the demand of safety-critical applications (e.g., automobile electronics) increases, various radiation-hardened flip-flops are proposed for enhancing design reliability. Among all flip-flops, Delay-Adjustable D-Flip-Flop (DAD-FF) is specialized in arbitrarily adjusting delay in the design to tolerate soft errors induced by different energy levels. However, due to a lack of testability on DAD-FF, its soft-error tolerability is not yet verified, leading to uncertain design reliability. Therefore, this work proposes Delay-Adjustable, Self-Testable Flip-Flop (DAST-FF), built on top of DAD-FF with two extra MUXs (one for scan test and the other for latching-delay verification) to achieve both soft-error tolerability and testability. Meanwhile, a built-in self-test method is also developed on DAST-FFs to verify the cumulative latching delay before operation. The experimental result shows that for a design with 8,802 DAST-FFs, the built-in self-test method only takes 946 ns to ensure the soft-error tolerability. As to the testability, the enhanced scan capability can be enabled by inserting one extra transmission gate into DAST-FF with only 4.5 area overhead.

To achieve improved speed of operation, a higher integration density and lower power dissipation, transistors are being scaled aggressively. This trend has reduced the critical charge of sensitive nodes. As a result, SRAM cells used in the high radiation environment of aerospace have become highly vulnerable to soft errors. In this paper, we propose a soft-error-aware 14T (SEA14T) SRAM cell for aerospace applications. The performance of the proposed cell is assessed by comparing it with other radiation-hardened SRAM cells like QUCCE12T, WE-QUATRO, RHM12T, RHD12T, RSP14T and RHBD14T. The proposed cell can fully recover from a single-event upset, of any strength and polarity, induced at all the sensitive nodes. Simulation results also show that SEA14T can fully recover from a multi-node upset induced at the internal node-pair. The proposed cell exhibits $1.06\times / 1.08\times / 1.36\times $ shorter read delay than QUCCE12T/ WE-QUATRO/ RHBD14T and $1.03\times / 1.09\times / 1.12\times / 1.15\times / 1.17\times $ shorter write delay than RHM12T/ WE-QUATRO/ QUCCE12T/ RSP14T/ RHD12T. It also shows $1.33\times / 1.6\times / 2.4\times $ higher read stability than QUCCE12T/ WE-QUATRO/ RHBD14T and $1.13\times / 1.32\times / 1.37\times / 1.42\times / 1.5\times $ higher write ability than RHM12T/ WE-QUATRO/ QUCCE12T/ RSP14T/ RHD12T. Furthermore, the proposed cell consumes $2.31\times / 2.42\times / 2.55\times / 3.04\times $ lower hold power than RHD12T/ RSP14T/ WE-QUATRO/ QUCCE12T @ ${V} _{\text {DD}}$ = 1 V. All these improvements are achieved at the cost of a slightly larger area overhead.

Radiation vulnerability and high power density are critical challenges in modern CMOS processors. Spin-based devices like magnetic tunnel junction (MTJ) are among the promising alternatives for addressing these challenges thanks to their fascinating properties such as radiation immunity, non-volatility, high endurance, and compatibility with the CMOS fabrication process. Utilizing the fascinating non-volatile property of the MTJ device, a high-performance, and energy-efficient soft error immune retention latch, and a high-reliable non-volatile flip-flop (FF) are proposed in this paper. Thanks to the single event upset (SEU) immunity, the proposed circuits are applicable in designing highly reliable processors, especially in applications like aerospace systems, where immunity to radiation induced soft errors is very critical. Because of the innovative design of the proposed approach, the MTJ switching delay does not affect the performance of the proposed latch. The simulation results indicate that the proposed latch offers lower delay, power consumption, and power delay product (PDP) than the state-of-the-art designs. The results of the comprehensive Monte-Carlo simulations also demonstrate that the proposed approach is more robust to process, voltage, and temperature variations as compared to their previous counterparts. This is because our designs do not use a pre-charge sense amplifier (PCSA) to read the data stored in the MTJs, and hence, the proposed designs have lower error rates. Furthermore, the transient impact of the particle strikes on the internal nodes is not transferred to the output node of the proposed circuits. The proposed design also has a significantly shorter output recovery time compared to its state-of-the-art counterparts.

Recent advances in CMOS scaling have made circuits more and more sensitive to errors and dysfunction caused by ionizing radiation, even at ground level, requiring accurate modeling of such effects. Besides generation, transport, and collection of radiation-induced excess carriers, another phenomenon, called funneling, has to be modeled for an accurate prediction of soft errors. The funneling effect occurs when the radiation track crosses a space charge region and generates excess carriers with a density higher than the doping close to it. These carriers distort the electric field of the space charge region, deeply changing the transport mechanism, from diffusion in a field-free semiconductor to drift. The objective of this work is to include funneling as part of the generalized lumped devices model in order to obtain a complete tool for SPICE-compatible simulations of single-event effects (SEEs). The latter approach has been recently proposed to simulate radiation-induced charges in the silicon substrate and is based on the so-called generalized lumped devices that simulate charge generation, propagation, and collection using standard circuit simulators. The generalized devices are here extended to include funneling and used to simulate an alpha particle impinging on the bulk of nMOS and pMOS transistors. The results obtained are validated with TCAD numerical simulations. Finally, an static random-access memory (SRAM) struck by an alpha particle is analyzed. The model predicts that the occurrence of a soft error, i.e., flipping of memory state, may depend on whether or not there is funneling. This justifies the need for accurate modeling of funneling phenomena to predict SEEs in ICs.

Space consists of high-energy particles and high-temperature fluctuations, which causes single event upsets (SEUs). Conventional 6T static random access memory (SRAM) is unable to tolerate this harsh environment in space. Therefore, it is necessary to design an SRAM, which can withstand this harsh environment. In order to mitigate SEUs, a radiation-hardened SRAM cell, named soft-error resilient read decoupled 12T (SRRD12T), is presented in this article. To estimate the relative performance of the proposed cell, it is compared with other contemporary designs, such as RHMN12T, RHMP12T, RHD12T, QUCCE12T, and QUATRO12T, over various important design metrics. SRRD12T can not only recover from SEU induced at any of its sensitive nodes but also from single event multi-node upsets (SEMNUs) induced at its storage node pair. Furthermore, due to the read decoupled design of SRRD12T, it exhibits the highest read stability. In addition to these, SRRD12T shows $1.14\times /1.17\times $ shorter write delay than RHD12T/RHMP12T. Moreover, SRRD12T consumes lower hold power and exhibits higher write ability than most of the comparison cells. However, these advantages are obtained by exhibiting a slightly longer read delay.

A new dynamic random access memory (DRAM) memory cell transistor is fabricated, and its soft-error immunity and rowhammer tolerance are studied. The vertical channel is formed by selective epitaxial growth of silicon pillar, and the surround gate forms a fully depleted (FD) channel, which can suppress floating-body effects, such as hysteresis. A TCAD simulation study compares this device and conventional bulk saddle FinFET in terms of soft error immunity and rowhammer tolerance. The confined channel limits soft error because of its thin channel volume for charge generation due to alpha and neutron particles. The surround gate device is inherently free from rowhammer attack as each silicon body of any memory cell transistor is fully isolated from neighboring word lines.

This paper presents two novel low cost, double-and-triple-node-upset tolerant latch designs. First, a novel low cost and double-node-upset (DNU) completely tolerant (LCDNUT) latch design is proposed. The latch mainly comprises a storage module (SM) feeding back to a 3-input C-element. The SM mainly consists of eight input-split inverters. Since the inputs of the C-element cannot be simultaneously flipped, the latch tolerates any DNU in the SM. When a single node in the SM and the output node are affected, the latch can self-recover from the DNU. Second, to completely tolerate any triple-node-upset (TNU), by replacing the C-element in the LCDNUT latch with a two-level error-interceptive module constructed from triple C-elements, a novel low cost and TNU completely tolerant (LCTNUT) latch design is proposed. Simulation results demonstrate the robustness of the proposed latches. Furthermore, due to the use of a high-speed transmission path, the clock-gating technology and fewer transistors, the proposed LCTNUT latch reduces the delay-power-area product by approximately 99.39 percent and has a low sensitivity to the process-voltage-and-temperature variation effects, compared with currently the only TNU completely tolerant latch design.

Soft error resilience is an increasingly important requirement of integrated circuits realized in CMOS nanometer technologies. Among the several approaches, Bulk Built-in Current Sensors (BBICS) offer a promising solution as they are able to detect particle strikes immediately after its occurrence. Based on this idea we demonstrate a novel modular BBICS (mBBICS) that tackles the main problems of these integrated sensors – area, leakage, and robustness. Simulations based on a predictive nanometer technology indicate competitive response times for high performance applications at the cost of 25 % area overhead and very low power penalty. Thereby, all simulated particle strikes that lead to transient faults could be detected. Additionally, reliability analysis proved the robustness of the proposed mBBICS against wide variations of temperature and process parameters.

Negative bias temperature instability (NBTI) is the major reliability issue which affects many parameters such as threshold voltage, mobility, and leakage current. The threshold voltage of the PMOS transistor increases due to NBTI with stress time, which degrades the circuit performance. In this article, we have proposed a novel reliable data-dependent low power 10T SRAM cell, which is highly stable and free from half select issues. We investigated all the circuit simulations using 65nm CMOS technology. The proposed 10T cell has a higher critical charge and lower soft error rate (SER) as compared to other SRAM cells. To better assess, we introduced a bit read failure (BRF) at read operation and observed that the BRF of the proposed 10T cell is significantly reduced as compared to the other considered SRAM cells at 0.15V supply. The leakage power, write power-delay-product, and read power-delay-product of the proposed 10T cell is $0.1\times $ , $0.21\times $ , and $3.13\times $ , respectively as compared to the conventional 6T cell at 0.4V supply. The proposed cell offers $4\times $ , $1.15\times $ and $1.66\times $ higher read, hold and write margin, respectively, as compared to 6T cell at 0.4V supply voltage. The simulation result shows that the HSNM, WSNM, and RSNM are decreased by 0.31%, 0.13%, and 0.08%, respectively, with the proposed 10T cell while 6T cell reduces 3.21%, 0.43%, and 8.62%, respectively, after 10 years of stress time. We have also introduced an on-chip adaptive VDD scaled reconfigurable architecture compared to the conventional array architecture design to reduce 97.04% and 92.17% hold power of unselected cells during read and write operation of the selected cell, respectively for the proposed 10T cell.

At the Korea Multi-purpose Accelerator Complex (KOMAC), a 100-MeV high-power proton linac has been used for proton-beam irradiation services for various applications and research programs, including material science, bio-medical science, semiconductor applications, as well as nuclear physics and basic science, since commissioning of the machine in 2013. Recently, demands for fast neutrons from users in the semiconductor industries are increasing to test the semiconductor device SER (soft error rate) or SEE (single event effect). At present, we provide pilot services to users with pulsed white-spectrum neutrons (max. neutron energy ∼100 MeV) generated at the beam dump, which is made of copper. However, the neutron energy should be increased at least to 200 MeV to meet international standards such as ISO26262 or JEDEC89A. For the upgrade of the linac energy to 200 MeV, we conducted a preliminary design study, including superconducting radio-frequency (SRF) based linac structure, a neutron generation target and a neutron utilization facility. The upgrade plan for the KOMAC linac, along with the preliminary results of the design study on the superconducting linac and neutron generation facility, will be given in this paper.

We evaluated soft-error tolerance by neutrons and heavy ions on four types of flip flops (FFs) called D-type flip flop (DFF), guard-gate FF (GGFF), feedback recovery FF (FRFF), and dual FRFF (DFRFF) in a 65-nm thin buried oxide (BOX) fully depleted silicon on insulator (FDSOI). FRFF has a guard-gate structure only in the master latch. GGFF and DFRFF have the guard-gate structure in both master and slave latches. The guard-gate structure resolves a single-event transient (SET) pulse by delaying it through the guard gate. FRFF and DFRFF have smaller area and shorter delay overheads than GGFF. We revealed that the guard-gate structure has high soft-error tolerance by low-linear energy transfer (LET) heavy ions, but the larger-LET ions over 40 MeV-cm2/mg cause upset even in the guard-gate structures. We revealed that longer delay in the guard-gate can resolve these issues by circuit simulations.

This brief presents an output transition detector-based radiation-hardened latch (TDRHL) for reliability improvement. With an error recovery assistant logic and an in-situ transition detector, for any radiation induced single- and double-node upsets, the proposed TDRHL can 1) provide full self-recovery capability and 2) generate a warning signal for architecture-level recovery when soft errors cause the latch output flipped. The evaluation results show that TDRHL outperforms state-of-the-art double-node upset tolerant designs with addition error detection capability, and up to 5.0X power-delay-product improvement can be achieved.

In Space applications, the scaling of transistors has made integrated circuits (ICs) more susceptible to soft errors, caused by radiation strikes. When a soft error causes a bit flip in a memory device, this event is referred to as a Single Event Upset (SEU). Since SEU errors degrade system performance and eventually lead to system failure, the design of radiation-resilient memory is substantial. This paper presents a radiation resilient SRAM with a self-refresh scheme for lowering the number of errors in each row below a threshold number. The proposed self-refresh operation reads out the stored data and performs single error correction using a simple algorithm during its hold/idle mode. A 4KB SRAM test chip in 65nm CMOS technology demonstrates a significant reduction in errors with the self-refresh operation. When the SRAM test chip was exposed to accelerated proton radiation with an energy level of 39.38 MeV, the self-refresh scheme reduces the number of uncorrectable errors by $25\times $ and $8\times $ lesser for the fluence of $9.82\times 10^{11}$ particles/cm2 and $49.1\times 10^{11}$ particles/cm2, respectively.

Purpose The purpose of this paper is to design novel hardened flip-flop using carbon nanotube field effect transistors (CNTFETs). Design/methodology/approach To design the proposed flip-flop, the Schmitt trigger-based soft error masking and unhardened latches have been used. In the proposed design, the novel mechanism, i.e. hysteresis property is used to enhance the hardness of the single event upset. Findings To obtain the simulation results, all the proposed circuits are extensively simulated in Hewlett simulation program with integrated circuit emphasis software. Moreover, the results of the proposed latches are compared to the conventional latches to show performance improvements. It is noted that the proposed latch shows the performance improvements up to 25.8%, 51.2% and 17.8%, respectively, in terms of power consumption, area and power delay product compared to the conventional latches. Additionally, it is observed that the simulation result of the proposed flip-flop confirmed the correctness with its respective functions. Originality/value The novel hardened flip-flop utilizing ST based SEM latch is presented. This flip-flop is significantly improves the performance and reliability compared to the existing flip-flops.

We present the experimental results on the impact of transistor width modulation and power supply voltage variation on the $\alpha $ -soft error rate (SER) in a 65-nm CMOS 6T static random access memory (SRAM) obtained from an accelerated test experiment using an Am- $241~\alpha $ -source. Five 6T cells with various combinations of transistor widths were tested and the results show that nMOS and pMOS widths play a different role on SER. We also found that the transistor width modulation effectiveness is highly dependent on the power supply voltage. In particular, the results show that at around nominal voltages, widening all pMOS while keeping all nMOS minimum sized, is the best way to improve SER. However, at lower voltages the results become completely different, and the best option for an overall SER improvement is to keep all transistors minimum sized.

For the safety-critical applications such as biomedical and automobile electronics, the system failure induced by soft errors becomes a major issue of reliability. However, most of the commercial cell libraries do not include radiation-hardened components to build a safety-critical design. Therefore, a delay-adjustable D-flip-flop (DAD-FF) is proposed together with a design flow to construct a radiation-hardened system by automation. To enable such radiation-hardened design into the current design flow, DAD-FF is characterized as a general cell and compiled as a patch in the NanGate FreePDK45 bulk 45-nm open cell library, as an example. The experimental results show that DAD-FF is capable of reducing $1.3\times 10^{10}\text{X}$ soft errors with respect to the standard flip-flop (STD-FF) and resisting over 99.999997% strikes of heavy ions. Meanwhile, four radiation-hardened benchmark circuits are synthesized with DAD-FF cell, and further used to prove the effectiveness against soft errors compared to a prior work, built-in soft-error resilience (BISER), with 18% area and 40% timing improvement. To sum up, DAD-FF is elaborated from the modeling at the device-level to the validation at the system-level and exhibits its strong robustness to soft errors.

International audience; First, this paper proposes a double-node-upset (DNU)-completely-tolerant (DNUCT) latch, featuring quadruple cross-coupled dual-interlocked-storage-cells (DICEs) with a C-element. Due to the existence of sufficient feedback loops, the latch can achieve complete DNU toleration. Second, this paper proposes an improved DNUCT latch (referred to as the TNUCT latch) by inserting a redundant level of C-elements at the output stage to intercept node-upset errors accumulated in the upstream DICEs so as to completely tolerate any possible triple-node-upset (TNU). Simulation results demonstrate the robustness of the proposed latches. These innovative latches are also cost-effective due to the use of high-speed transmission paths, clock gating, and fewer transistors. Compared with the typical TNU hardened latch (TNUHL) design that can completely tolerate any TNU, the proposed TNUCT latch reduces the delay-power-area product by approximate 98%. The proposed latches have less or equivalent sensitivity to process, voltage, and temperature variation effects compared with reference latches.

Soft errors constitute a crucial reliability concern for the Integrated Circuits (ICs) as the continuous CMOS technology downscaling renders them vulnerable to radiation-induced hazards. Therefore, the Soft Error Rate (SER) evaluation represents a necessary process to design radiation-hardened ICs. A SPICE-oriented electrical masking analysis, combined with a TCAD characterization process, contributes to an accurate SER estimation. The impact of a Static Timing Analysis (STA) methodology on SER and the consideration of the actual interconnect delay are discussed. Experimental results on various benchmarks, synthesized with respect to 45nm and 15nm technology, indicate the SER variation as the device scales down.

Neutrons have been used in a wide field of applications by using various neutron sources. Material science is one of the widest research fields. The activity is supported by nuclear research reactors and high-intensity spallation neutron sources based on a high-intensity proton accelerator. However, it is desired to perform a measurement when researchers want to do and to perform adventuresome experiments that have not yet confirmed its importance. Furthermore, trial and error measurements are necessary to improve a measurement method. Compact accelerator-driven neutron sources are suitable for such usage and in some cases can complement the measurement at a large facility. The use of the compact neutron source has sometimes led to new methods. Other than material science, a new application of soft error acceleration test has been performed at the compact accelerator-driven neutron sources. Another neutron application is radiation therapy called as boron neutron capture therapy. In this field, nuclear reactor neutron sources have been used but many of them shut down. It was desired to construct the BNCT facility near a hospital. Therefore, BNCT facilities based on the compact accelerator have been constructed in the world. Here, the neutron sources and new methods and applications developing at compact accelerator-driven neutron sources are introduced.

The modern automobile industry is rapidly shifting toward the era of self-driving cars. Due to rapid technological development, many mechanical parts in automobiles have been switched to electronic devices. Therefore, the proportion of electronic devices in modern cars is increasing. Even though many parts have been replaced by electronic devices, vehicles still require the periodic maintenance not only for mechanical parts, but also for automotive electronics. To guarantee the high reliability of automotive Application-Specific Integrated Circuits (ASICs), automotive chips are tested during manufacturing for functional and structural defects. Moreover, automobile chips are also tested using several in-field diagnostic techniques (e.g., online Built-In Self-Test (BIST), Software-Based Self-Test (SBST)) while the chips are operating. By using these in-field diagnostic techniques, functional and structural defects in automotive ASICs, which occur in the early-life cycle and normal operation, can be detected. However, automotive semiconductor devices still require testing for aging-induced defects and soft errors to prevent critical functional failures. Moreover, aging-induced defects are hard to detect with conventional in-field diagnostic techniques which is based on BIST techniques. Thus, this work presents a secure Controller Area Network (CAN) -based Test Access Mechanism (TAM) for aging defect diagnosis with efficient soft-error resilient scan cell design for automotive ASICs. The proposed TAM incurs area overhead of 6% to 9% depending upon the selection of mode identification. Further, the proposed Aging monitoring and Soft Error Resilience Flip Flop (ARFF) incurs 22% less area and power as compared to separate implementation of the Built-In Soft Error Resilience (BISER) and the Early Capture Flip Flop (ECFF).

Accepted: 2019-10-20, 資料番号: SA1190196000

In recent years, many researches have been conducted on 6T static memory performance improvements and strengthen it against soft error in sub-threshold region. These studies finally result in some SRAM cell designs with the proper performance in bit-interleaving structure and sub-threshold region in cost of more area consumption. This study presents a new bit-interleaving 7T SRAM cell which occupies less area consumption and has a better performance when compared with other 9T, 10, and 12T bit-interleaving cells. The suggested 7T cell is simulated with HSPICE in 32 nm technology and with multi-Vt transistors considering LP, HP, and standard models for HVt, LVt, and SVt transistors, respectively. The simulation results demonstrate the performance superiority of authors' proposed cell compared with its counterparts. Moreover, the simulation results (VDD = 0.5 V) show the suggested cell in comparison with conventional 6T cell improves read, hold, and write power consumptions 91.42, 91.93, and 68.7%, respectively. Also, cell stability (RSNM) and write margin (WM) parameters improve 172 and 67.2%, respectively.

As minimum area SRAM bit-cells are obtained when using cell ratio and pull-up ratio of 1, we analyze the possibility of decreasing the cell ratio from the conventional values comprised between 1.5-2.5 to 1. The impact of this option on area, power, performance and stability is analyzed showing that the most affected parameter is read stability, although this impact can be overcome using some of the read assist circuits proposed in the literature. The main benefits are layout regularity enhancement, with its consequent higher tolerance to variability, cell area reduction by 25 percent (with respect to a cell having a cell ratio of 2), leakage current improvement by a 35 percent, as well as energy dissipation reduction and a soft error rate per bit improvement of around 30 percent.

We report a detailed analysis of neutron-induced multibit-upset (MBU) clusters measured from flip-flop arrays implemented in a 14-nm trigate CMOS. Depending on the strike location, charge collection efficiency, and circuit topology, the MBU clusters are characterized in terms of size and span, and a qualitative first-order analysis has been presented. A novel MBU analysis framework has been demonstrated that uses a weighted sliding window to characterize MBU clusters efficiently and accurately with minimal double-counting or mischaracterization of cluster size. To further explain the relative MBU cross sections, the unique MBU patterns extracted from measured data have been studied and analyzed to find layout dependencies. The results show the strong correlation between the internode proximity and MBUs. The analysis shows a higher soft error rate (SER) cross section for smaller MBU cluster size and smaller span while the bigger clusters have lower contribution toward overall MBU SER.

Soft error effects due to the alpha particle and terrestrial neutron strike are investigated in a saddle fin DRAM using the 3D TCAD simulation. The strike location and angle dependency are investigated, and the worst-case incidence condition is studied. As the strike time is relevant for the error pattern, the strike during the write period is found to have minor effect, but the strike during the hold period shows data corruption. The inter-active disturbance is effectively suppressed due to the shallow trench isolation, but the inter-active ionizing radiation disturbance can be a potential risk as the capacitance of the storage capacitor continues to reduce with the DRAM technology scaling.

In this paper, quadruple cross-coupled storage cells (QUCCE) 10T and 12T are proposed in 130 nm CMOS technology. The QUCCE 10T and 12T are about $2\times $ and $3.4\times $ the minimum critical charge of the conventional 6T, respectively. Compared with most of the considered state-of-the-art SRAM cells, both QUCCE 10T and 12T have comparable or better soft error tolerance, time performance, read static noise margins, and hold static noise margins, and besides, QUCCE 10T also has similar or lower costs in terms of area and leakage power. The QUCCE 10T is designed for high-density SRAMs at the nominal supply voltage. Furthermore, the QUCCE 12T saves more than 50% the read access time compared with most of the referential cells including the 6T, making it suitable for high speed SRAM designs, and it also has the best read margin, except for the traditional 8T, in terms of $\mu /\sigma $ ratio in the near threshold voltage region among all the other considered cells which nearly have no write failure in that region. Hence, the QUCCE 12T is a promising candidate for future highly reliable terrestrial low-voltage applications.

Near threshold computing (NTC) has significant role in reducing the energy consumption of modern very large scale integrated circuits designs. However, NTC designs suffer from functional failures and performance loss. Understanding the characteristics of the functional failures and variability effects is of decisive importance in order to mitigate them, and get the utmost NTC benefits. This paper presents a comprehensive cross-layer reliability analysis framework to assess the effect of soft error, aging, and process variation in the operation of near threshold voltage caches. The objective is to quantify the reliability of different SRAM designs, evaluate voltage scaling potential of caches, and to find a reliability-performance optimal cache organization for an NTC microprocessor. In this paper, the soft error rate (SER) and static noise margin (SNM) of 6T and 8T SRAM cells and their dependencies on aging and process variation are investigated by considering device, circuit, and architecture level analysis. Their experimental results show that in NTC, process variation and aging-induced SNM degradation is $2.5{\boldsymbol \times }$ higher than in the super threshold domain while SER is $8{\boldsymbol \times }$ higher. At NTC, the use of 8T instead of 6T SRAM cells can reduce the system-level SNM and SER by 14% and 22%, respectively. Besides, we observe that we can find the right balance between performance and reliability by using an appropriate cache organization at NTC which is different from the super threshold.

Susceptibility to soft errors caused by radiation or other noise sources is a major concern for devices operating with limited supply voltages at scaled technology nodes. These errors are occasional abnormalities that give rise to single event effects (SEE), which may corrupt the circuit functionality. Although the insensitivity to timing variations allows quasi delay insensitive (QDI) circuits to be robust against many of the radiation or noise effects that affect the timing behavior of CMOS based synchronous digital circuits, they are still susceptible to soft errors. Various error detection, mitigation, and radiation hardening schemes for QDI circuits exist in the literature. This paper provides a comprehensive overview of the existing techniques and a comparative analysis of their significance, performance, and limitations.

This paper presents single-event upset (SEU) rates in flip-flops (FFs) in EUV 7 nm bulk-FinFET technology. EUV technology achieves high transistor-density, small FF cell-size, and low SEU rate. The alpha-SEU rate in EUV 7 nm FFs is 0.7X of the SEU rates in 10 nm FFs. The neutron-SEU rate in EUV 7 nm FFs is 0.6X of the SEU rates in 10 nm FFs. This paper also discusses the circuit dependence of the SEU rate in Normal-, Reset-, Set-FFs, and a soft-error immune FF (SEIFF), and SRAM.

The unprecedented growth in deep neural networks (DNN) size has led to massive amounts of data movement from off-chip memory to on-chip processing cores in modern machine learning (ML) accelerators. Compute-in-memory (CIM) designs performing analog DNN computations within a memory array, along with peripheral mixed-signal circuits, are being explored to mitigate this memory-wall bottleneck: consisting of memory latency and energy overhead. Embedded-dynamic random-access memory (eDRAM) [1], [2], which integrates the 1T1C (T=Transistor, C=Capacitor) DRAM bitcell monolithically along with high-performance logic transistors and interconnects, can enable custom CIM designs. It offers the densest embedded bitcell, a low pJ/bit access energy, a low soft error rate, high-endurance, high-performance, and high-bandwidth: all desired attributes for ML accelerators. In addition, the intrinsic charge sharing operation during a dynamic memory access can be used effectively to perform analog CIM computations: by reconfiguring existing eDRAM columns as charge domain circuits, thus, greatly minimizing peripheral circuit area and power overhead. Configuring a part of eDRAM as a CIM engine (for data conversion, DNN computations, and weight storage) and retaining the remaining part as a regular memory (for inputs, gradients during training, and non-CIM workload data) can help to meet the layer/kernel dependent variable storage needs during a DNN inference/training step. Thus, the high cost/bit of eDRAM can be amortized by repurposing part of existing large capacity, level-4 eDRAM caches [7] in high-end microprocessors, into large-scale CIM engines.

Soft Error Rate (SER) estimation is an important challenge for integrated circuits because of the increased vulnerability brought by technology scaling. This paper presents a methodology to estimate in early stages of the design the susceptibility of combinational circuits to particle strikes. In the core of the framework lies MASkIt , a novel approach that combines signal probabilities with technology characterization to swiftly compute the logical, electrical, and timing masking effects of the circuit under study taking into account all input combinations and pulse widths at once. Signal probabilities are estimated applying a new hybrid approach that integrates heuristics along with selective simulation of reconvergent subnetworks. The experimental results validate our proposed technique, showing a speedup of two orders of magnitude in comparison with traditional fault injection estimation with an average estimation error of 5 percent. Finally, we analyze the vulnerability of the Decoder, Scheduler, ALU, and FPU of an out-of-order, superscalar processor design. This work has been partially supported by the Spanish Ministry of Economy and Competitiveness and Feder Funds under grant TIN2013-44375-R, by the Generalitat de Catalunya under grant FI-DGR 2016, and by the FP7 program of the EU under contract FP7-611404 (CLERECO).

In this paper, a Soft Error Hardened D-latch with improved performance is proposed, also featuring Single Event Upset (SEU) and Single Event Transient (SET) immunity. This novel D-latch can tolerate particles as charge injection in different internal nodes, as well as the input and output nodes. The performance of the new circuit has been assessed through different key parameters, such as power consumption, delay, Power-Delay Product (PDP) at various frequencies, voltage, temperature, and process variations. A set of simulations has been set up to benchmark the new proposed D-latch in comparison to previous D-latches, such as the Static D-latch, TPDICE-based D-latch, LSEH-1 and DICE D-latches. A comparison between these simulations proves that the proposed D-latch not only has a better immunity, but also features lower power consumption, delay, PDP, and area footprint. Moreover, the impact of temperature and process variations, such as aspect ratio (W/L) and threshold voltage transistor variability, on the proposed D-latch with regard to previous D-latches is investigated. Specifically, the delay and PDP of the proposed D-latch improves by 60.3% and 3.67%, respectively, when compared to the reference Static D-latch. Furthermore, the standard deviation of the threshold voltage transistor variability impact on the delay improved by 3.2%, while its impact on the power consumption improves by 9.1%. Finally, it is shown that the standard deviation of the (W/L) transistor variability on the power consumption is improved by 56.2%.

As emerging memories are utilized in processors as main memory, they must also coexist with CMOS memories; for instance SRAMs, are used to implement smaller, but faster associative memories. These hybrid designs exploit the advantages of both types of memories to achieve better performance. For some applications, the improvement in performance for on-chip associative memories is crucial for the overall computing system. For CMOS memories, soft errors are a major concern because they flip bits and can lead to data corruption and even a system failure. Error Detection and Correction Codes (EDCCs) are commonly used to protect memories against soft errors. In associative memories, an entry is formed by a tag and its associated data (or value). EDCCs are typically used to separately protect the tag and the data. This paper considers the protection of associative memories in which false negatives do not cause a failure. A Combined Tag and Data Parity (CTDP) protection scheme is proposed. This new approach utilizes a single parity bit per entry, so it reduces the number of parity bits needed to protect an entry as well as the memory size. The proposed scheme also reduces the complexity of read operations; it incurs the lowest circuit overhead for the protection circuitry in terms of area, delay and power consumption when compared to other schemes found in the technical literature. This makes the proposed scheme germane to associative memories used in hybrid designs that combine SRAMs and emerging memories. The extension of the proposed scheme to stronger codes is also discussed. This work was supported in part by the ACHILLES Project PID2019-104207RB-I00 and the Go2Edge Network RED2018-102585-T, and in part by the Spanish Ministry of Science and Innovation and by the Madrid Community research project TAPIR-CM under Grant P2018/TCS-4496.

International audience; Germanium is potentially candidate to replace silicon in ultra-scaled transistors. This work analyses the radiation response of germanium in thin layer subjected to atmospheric neutrons simulated with Geant4 and quantifies the underlying mechanisms potentially responsible of single event effects in Ge-based CMOS technologies. From this analysis of interactions at material-level, reliability assessments for Gebased nanoelectronics are tentatively deduced for technological nodes ranging from 180 nm to 5 nm in terms of nature and number of nuclear events susceptible to upset a SRAM memory cell. Finally, first soft error rate projections are performed for germanium SRAMs in 130, 65 and 40 nm based on a simulation methodology previously developed and fully validated on silicon memories also characterized by real-time experiments.

The major design metric for designing a basic SRAM cell includes a high value of RSNM, low power consumption and higher reliability, whereas a radiation-tolerant SRAM cell includes the design metric of soft error robustness. In this paper, a Quad-node 10 transistor (10T) soft error robust SRAM cell was proposed that is more robust than the Quatro 10T cell. The NMOS access transistors of the Quatro 10T cell are replaced by the PMOS access transistors in the proposed 10T cell. The benefit of using access transistors as PMOS is due to their high radiation tolerance. The leakage currents in PMOS access transistors are not affected by the radiation bombardment, whereas they increase rapidly in NMOS transistors. In hold operation, both the cells consume the same amount of power as the access transistors are cut off. We also have smaller gate leakages in the case of PMOS access transistors than NMOS access transistors. In the case of hold operation, both the Quatro and proposed cells are able to recover from 1 → 0 single event transients (SETs). For 0 → 1 single event transients (SETs) in hold operation, the proposed cell shows an increment of 3 µA in the current margin. This improves the hold failure probability of the proposed cell. The increment in the current margin is obtained by compromising the increment in the value of read access time by 2.04%. The rest of the design matrices such as Read Static Noise Margin (RSNM), Hold power, Write Static Noise Margin (WSNM) and Cell Area remain the same.

The Soft-Error (SE) reliability and the effects of Negative Bias Temperature Instability (NBTI) in deep submicron technologies are characterized as the major critical issues of high-performance integrated circuits. The previous scientific research studies provide a comprehensive description that the soft-error vulnerability becomes more severe as the circuit performance degrades with aging. The main reason is the reduction of cell-level critical charge in an aging environment. However, such increased soft-error generation does not necessarily contribute towards circuits' critical functional failures. The proposal of this paper is the experimental investigation of soft error propagation at the aged gate-level by considering the different derating factors like Electrical Derating (EDR), Temporal Derating (TDR), Logical Derating (LDR), and Functional Derating (FDR). As contrary to the previous studies, the results of this work prove that SEU fault propagation probability is reducing in critical paths as time advances while the propagation probability of SET faults is neither reducing nor increasing, but the spot of generation of failure enhancing SETs is shifting within the clock period.

Average power and delay are two essential aspects of measuring device performance in integrated circuits. The tradeoff between the two for a full protected soft error tolerant latch has been observed for MOSFET and two different operating modes of FinFET across 45nm and 32nm technology nodes and a comprehensive comparative analysis has been provided in this paper. The simulations have been conducted on HSPICE simulator and the results show as much as 84% reduction in delay with almost 8 times increase in power consumption for SG FinFET operation. A 13% improvement in power delay product was observed using LP FinFET mode in comparison with prevalent MOSFET technology. The design consideration of device choice and operation mode was also discussed.

Near-threshold computing (NTC) has significant role in reducing the energy consumption of modern very large-scale integrated circuits designs. However, NTC designs suffer from functional failures and performance loss. Understanding the characteristics of the functional failures and variability effects is of decisive importance in order to mitigate them, and get the utmost NTC benefits. This chapter presents a comprehensive cross-layer reliability analysis framework to assess the effect of soft error, aging, and process variation in the operation of near-threshold voltage caches. The objective is to quantify the reliability of different SRAM designs, evaluate voltage scaling potential of caches, and to find a reliability-performance optimal cache organization for an NTC microprocessor. In this chapter, the soft error rate (SER) and static noise margin (SNM) of 6T and 8T SRAM cells and their dependencies on aging and process variation are investigated by considering device, circuit, and architecture-level analysis.

Standard delay cells (SDCs) are commonly used for timing synchronization in digital designs. Due to skewed transistor sizing, the SETs induced in SDCs may be stretched during propagation through the cell, thus increasing the soft error rate. In this work, the simulation analysis of Single Event Transient (SET) effects in 130 nm SDCs is presented. The results have shown that the SETs induced in SDCs may be up to 1.46 ns wide, which is more than twice the width of SETs in other standard logic cells, for the same simulation settings. As the conventional gate-level SET mitigation techniques are not effective against long SETs, we have investigated two hardening solutions for SDCs: (i) complete duplication with a guard gate, and (ii) partial duplication with a guard gate applied only to the most sensitive inverters in the SDC. Both solutions can reduce significantly the generated SET pulse width, with the delay overhead of less than 250 ps. The estimated area overhead per cell is around 115 % for complete duplication and 80 % for partial duplication.

Radiation-hardened IA and ADC circuits are essential for a safe and efficient sensor system. In this paper, three-op-amp IA and SAR ADC were designed using radiation-hardened techniques and measured and proved to be robust to TID and SEE. Both Radiation-hardened IA and ADC were fabricated in a 65nm CMOS process and measured in an ARTI high-level radiation environment. The proposed IA was able to confirm that the voltage gain was accurate against TID effects in the harsh radiation environment. The proposed ADC obtained 9.59 ENOB at 5.54mW power consumption.

Nanoscale digital integrated circuits are getting increasingly vulnerable to soft errors due to aggressive technology scaling. Hence, SER estimation of combinational circuits has been one of the challenges of circuit reliability analysis due to three masking effects. On the other hand, as technology scales further, variations in cell geometries become prominent, as well. According to recent reports, the reliability of a particle strike-induced transient fault for a cell is sensitive to its geometry size, especially to transient faults which induce small charges. Therefore, both process variation impact and soft error effect need to be integrated for accurately estimating SER of nanoscale circuit designs. The impacts of process variations on the characteristics of circuits in nano era make statistical approaches an unavoidable option for SER estimation procedure. In this chapter, we present a statistical SER estimation framework. We introduce a concept called statistical vulnerability window (SVW) which is a unified variation-aware inference of various constraints necessary for a SET to cause soft errors in the circuit considering all three masking factors. Using a level-order backward traversal, SVWs for each circuit gate output are calculated using a computation model. The statistical SER of the circuit is gradually estimated considering a mathematical formulation of SER based on SVW parameters.

Nanometer integrated circuits are getting increasingly vulnerable to soft errors and making the soft error rate (SER) estimation an important challenge. Soft error rate (SER) is a measurement metric which is used to evaluate the sensitivity of a digital circuit to single-event transients (SETs). Efficient and accurate SER estimation of the combinational circuits helps the designers to achieve more reliable integrated circuits. In this chapter, we introduce a methodology for SER estimation of the combinational circuits based on vulnerability evaluation of the circuit gates to soft errors. A concept called probabilistic vulnerability window (PVW) which is an inference of necessary conditions for a SET to cause observable errors in the circuit is presented. Using a computation model, PVWs for each circuit gate output are calculated based on a level-order backward circuit traversing and meanwhile the SER of the circuit is gradually estimated considering a mathematical formulation of SER considering the computed PVW parameters.

International audience; To meet the requirements of both high reliability and low power in low-orbit aerospace applications, this article first presents a single-event Double-Upset (SEDU) self-Recoverable and single-event Transient (SET) Pulse Filterable (DURTPF) latch design with low power. The DURTPF latch mainly consists of eight mutually feeding-back C-elements (CEs) and an SET pulse filterable Schmitt-trigger (ST). To make an ST behave not only as a pulse filterable ST but also as an error interceptive CE, an input-split ST is created, leading to an enhanced-version of the DURTPF latch, namely DURTPF-EV. The DURTPF-EV latch mainly consists of seven mutually feeding-back CEs including an input-split ST. Simulation results demonstrate both the SEDU self-recoverability and SET pulse filterability of the proposed latches at the cost of moderate silicon area. Using the clock gating technology, the DURTPF latch reduces power dissipation by about 63% on average compared with the state-of-the-art SEDU self-recoverable latch designs that are not SET-pulse filterable. Moreover, the DURTPF-EV latch is more cost-effective and its reliability is also enhanced, making it more suitable for low power and low-orbit aerospace applications.