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In this paper, a peak efficiency tracking technique to improve the efficiency of switched capacitor (SC) DC–DC converters as the load varies is presented. A peak efficiency tracking circuit based on feedback control over the switching frequency is implemented for this scope. The basic idea of the proposed technique is to adjust the switching frequency according to the load. The technique is successfully implemented in a SC DC–DC converter to be embedded in detector pixels for the Large Hadron Collider (LHC) experiment at the Conseil Européen pour la Recherche Nucléaire (CERN) of Geneve. It is realized in 65 nm bulk CMOS technology with an occupied area of 1.31 mm2. This converter provides an 800 mV output voltage from a 1.2 V supply. The load of the DC–DC converters is modeled as a resistor, RLOAD, that has 4 Ω nominal value but it can range from 2.67 up to 10 Ω. At 10 Ω RLOAD, a 6% efficiency improvement is reached with respect to the typical approach consisting in keeping constant the switching frequency at the optimum value for RLOAD nominal value.

The reduction of the nominal supply voltage of CMOS technologies with scaling comes with the decrease of the maximum tolerable voltage of the devices. This poses challenges in implementing circuit blocks that are compliant with standardized communication protocols or deal with off-chip signals in voltage domains larger than the nominal supply (e.g., 1.8 V, 3.3 V, 5 V). Design techniques such as cascoding, voltage shifting and adaptive biasing are effective at removing the need for customized voltage resistant input/output (I/O) devices since they prevent intolerable voltage drops. However, at the input of multiple-channel blocks, the design of switches of multiplexers results critical as the input and the output nodes can assume values beyond the signal range, causing harmful biasing configurations. This paper presents the architecture of a switch for input channel multiplexers able to handle signals up to twice the nominal supply voltage of the employed devices. Its effectiveness has been proved by implementing a 1.6V switch with the core MOS transistors of the 28nm CMOS technology with 0.96V nominal supply voltage. The comparison with a benchmark switch based on 1.8V I/O devices showed that both a larger area (slightly more than twice) and static current consumption ( $40\mu \text{A}$ ) are required.

An energy-efficient, wide dynamic-range (DR) CMOS analog front-end (AFE) for chemiresistive sensors is presented. The circuit is specifically designed for the Metal Oxide (MOX) gas sensors, a special technology of chemiresistive sensors, broadly diffused in modern portable devices due to their low-cost and simplicity of use. Energy efficiency is mandatory for the AFE in order to prolong the battery life that supply these devices. The proposed circuit implements the resistance-to-time (R-to-T) conversion of the sensor’s resistance by adopting a relaxation oscillator-based architecture. A limiting resistor in series with the sensor is introduced for reducing the circuit’s energy-per-measurement (EpM), while mitigating the error due to the sensor’s parasitic capacitance. The analysis of the circuit is presented with emphasis on the design trade-off between error due to the sensor’s parasitic capacitance and power consumption on one side and read-out sensitivity on the other. The chip prototype is realized in AMS $0.35 ~\mu m$ process and has been tested in the DR between $100\Omega $ and $4.7M\Omega $ with an accuracy less than 0.1% and a precision less than 0.029%. The efficacy of the presented AFE is proved by adopting the circuit in a real chemical environment with a commercial sensor. The proposed AFE shows a maximum EpM of $296nJ$ which is three times better than the state of the art.

This paper presents a 4th-order low-pass continuous-time Diode-RC filter with 24 MHz cut-off frequency. The filter structure is based on the combination of positive (passive) and negative (using cross-coupled MOS transistors) cells to synthesize complex-conjugate-poles pairs. Moreover, the filter is designed and optimized to have high-linearity along all the filter pass-band. The filter exhibits 16 dBm-$$\text {IIP}_3$$ with 2–3 MHz input tones and 5 dBm-$$\text {IIP}_3$$ with 23–24 MHz, whereas the current consumption remains limited to $$100 \, \upmu \hbox {A}$$ from 1.8 V supply voltage.

An architecture of a switched-capacitor integrator that includes a charge buffer operating in an open-loop is hereby proposed. As for the switched-capacitor filters, the gain of the proposed integrator, which is given by the input/output capacitor ratio, ensures desensitization to process, voltage, and temperature variations. The proposed circuit is suitable for low voltage supplies. It enables a significant power saving compared to a traditional switched-capacitor integrator. This was demonstrated through an analytical comparison between the proposed integrator and a traditional switched-capacitor integrator. The mathematical results were supported and verified by simulations performed on a circuit prototype designed in 16 nm finFET technology with 0.95 V supply. The proposed switched-capacitor integrator consumes 76 &micro, W, resulting in more than twice the efficiency for the traditional closed-loop switched-capacitor filter as an input voltage equal to 31.25 mV at 7 ns clock period is considered. The comparison of architectures was led among the proposed integrator and the state-of-the-art technology in terms of the figure of merit.

This paper presents a 28 nm-bulk-CMOS 3rd-order 132 MHz low-pass filter based on an improved Active-gm-RC stage. Challenges related to the design of analog circuits in 28 nm-bulk-CMOS process node are faced, mitigated and exploited by operating at both architecture and circuit design levels. The filter uses a single-opamp two-stage topology where both poles are used for synthesizing a 3rd-order low-pass transfer function. The proposed filter operates from a single 0.9 V supply voltage, consumes 340 µW and performs high linearity (IIP3 = 11.5 dBm at 21 and 22 MHz input tones) and large Signal-to-Noise ratio (58 dB). This enables one of the higher Figure-of-Merit (163.2 dB) with respect to the state-of-the-art.

This paper analyzes the performance of amplification stages when they are used to buffer reference voltages. This topic is particularly interesting for Successive Approximation Register Analog to Digital Converters (SAR-ADCs) whose efficiency was tremendously pushed down during last years. A conventional solution for a reference buffer including a closed loop single stage opamp is firstly presented in order to individuate its limits. The conventional solution is used as benchmark for the proposed buffer circuit solution. It includes a reconfigurable circuit made by a charge pump, which enables a rapid charge of the output capacitive load. After the charging phase, the circuit is commutated into a closed loop opamp to let the feedback take the control of the output voltage. Both circuits were designed in CMOS 28nm technology with 1V supply. The proposed circuit has about half of the power consumption of the conventional one, 398μW and 774μW respectively, considering the same settling error.

This paper presents a simple structure for a low noise active loop filter, designed in 28nm CMOS process. Design strategies are used for minimizing both thermal and flicker noise at critical frequencies around 1MHz for radar PLL applications. Results show an input referred noise of 2.81 nV/VHz @1MHz for the op-amp of the loop filter, with nominal conditions and 1.8 V power supply, occupying an area of 0.039mm2.

In this letter, a fully-integrated RF-DC converter operating at the HF RFID working frequency (13.56 MHz) and realized in 350 nm CMOS technology is presented. It is based on a Dickson's rectifier, a Pelliconi's charge pump driven by a 50 kHz ring oscillator, and a voltage monitor. Mathematical model is developed and verified through simulations and measurements. Results show a sensitivity of −19 dBm with related output voltage of 0.5 V. Moreover, taking advantage from the internal voltage monitor, the suitability of the proposed architecture to pilot RFID-based sensor boards has been proved.

A single-branch third-order low-pass filter with an ultracompact die size and extensive bandwidth (BW)-power scalability is described. It unifies a source follower , a stackable floating active inductor, and a feedforward capacitor to constitute a transistorized- LC-ladder topology with a stable pole-zero transfer function over a wide range of tunable BW. Differentially, only eight transistors and five untuned capacitors are required. Fabricated in 0.18- μm CMOS, the prototype occupies 0.014- mm2 die size. By scaling the bias current (and, hence, the power), the flexible BW measures 0.8 kHz at 1.25 nW and 0.94 GHz at 3.99 mW.

A 28 nm CMOS-bulk lowpass analogue filter architecture is hereby proposed. The filter is based on an improved Active-Gm -RC structure, where both poles of a Miller-compensated operational amplifier (OPAMP) have been used for synthesising a third-order filter. Several well-known issues related to the 28 nm process node have been hereby mitigated by proper circuit/design techniques, enabling large signal-to-noise ratio (SNR) and 13.5 dBm IIP3. The proposed circuital solution performs 59 dB-SNR at 340 µW power consumption from a single 0.9 V supply-voltage. This allows one of the higher figure-of-merit (156 dB) in sub-1 V analogue filters state of the art.

Power consumption of high-speed low-resolution ADCs can be reduced by means of calibration. However, this solution presents some drawbacks like allocating a calibration time, calibration algorithm complexity, calibration circuit implementation, etc. In alternative, this paper presents a 5-bit 1Gs/s ADC without calibration, realized in a 90nm-CMOS. The device is based on the use of an improved version of double tail dynamic comparators, operating with a fixed bias current. These comparators present a reduced kickback noise, allowing increasing the input transistors sizes in order to improve the matching. The ADC current consumption is equal to 6.9mA from a 1.2V supply.

A low-power high-linearity variable-gain-amplifier (VGA) to be embedded in a multi-standard receiver (WLAN, UMTS and Bluetooth) is reported. The multi-standard receiver architecture presents considerable different VGA requirements (in terms of bandwidth, DC-gain, noise level, and common mode input voltage) for the three telecom standards. The VGA is positioned just after the mixer, and, then, it operates on low- amplitude input signals. This results in stronger noise requirements than linearity ones. Thus a digitally controlled open-loop structure has been used. The prototype VGA is realized in a 0.13 μm CMOS technology and it features gain levels from -10 to 36 dB. For 0 dB DC-gain it exhibits a 25 dBm IIP3 and an input-referred noise voltage lower than 5 nV/√Hz. This gives a 85 dB-DR for the WLAN case. The VGA draws 6.4 mA from a single 2.5 V supply.

In this work, a field effect transistor based on a deoxyguanosine derivative (a DNA base) is demonstrated. Our experiments on transport through the source and drain electrodes interconnected by self-assembled guanine ribbons (Gottarelli et al. Helv. Chim. Acta 1998, 81, 2078; Gottarelli et al. Chem. Eur. J. 2000, 6, 3242; Giorgi et al. Chem Eur. J. 2002, 8, 2143) suggest that these devices behave like p-channel MOSFETs, The devices exhibit a maximum voltage gain of 0.76. This prototype transistor represents a starting point toward the development of biomolecular electronic devices.

In this paper, a 4th-order low-pass continuous-time analog filter is presented, that is implemented with the cascade of two efficient and compact biquadratic cells, realized using the Super-Source-Follower topology. The biquadratic cell uses only two capacitors and four transistors: two transistors for the signal processing and two transistors as current sources for biasing pur- pose. The 4th-order filter prototype has been integrated in 0.18 μm CMOS technology. For a 33 MHz cut-off frequency, the filter per- forms 18 dBm-IIP3 for two tones at 2 MHz and 3 MHz, with total current of 770 μA from a single 1.8 V supply voltage.

This paper describes a chopper stabilized amplifier, obtained using an input chopper for modulation, an AC coupling for offset rejection and a correlated double sampling structure for demodulation, avoiding ripple spurs. The operational amplifier has a rail-to-rail input stage, with a supply voltage range from 1.8V to 5V. It is characterized by a multipath nested Miller compensation network with double pole-zero cancellation. The circuit achieves a simulated 130dB-dc-gain with a current consumption of 20μA, suitable for low-power application. Equivalent input offset has been evaluated by Montecarlo simulations demonstrating a maximum standard deviation of about 4μV.

In this paper a Charge-Sensitive Preamplifier (CSP) for GEM (Gas Electron Multiplier) detectors readout is presented. The CSP is responsible for signal acquisition and the conversion of the input charge into a voltage signal. The design has been realized in 0.13 μm CMOS technology. It has been demonstrated through a detailed analysis that this is the best CMOS technology to be used in this case, as regards power consumption, intrinsic gain, noise and radiation hardness. The aim is to reduce the power consumption while maintaining other performance at the state-of-the-art. The preamplifier is composed by a three-stage nested Miller Operational Amplifier, with a feed-forward compensation. The system is able to manage a 15 pF detector capacitance. The global power consumption is 1.1 mW and the Equivalent Noise Charge is 418 e-.

This paper investigates the improvement margins in term of energy efficiency of analog filters. Starting from a landscape of analog filters presented at ISSCC until 2012, energy limits for most common analog filters architectures (Gm-C and Active-RC) are traced. Active-RC filters with reduced bandwidth requirements have larger margins of improvements compared to Gm-C. Technology scaling impact is also evaluated. Supply reduction that join the technology scaling seems to have a limited effect on Gm-C filters, as their energy limit depends on the SNR only. However, technology scaling enables larger bandwidth opamps, pushing the Active-RC technique at higher and higher frequency, where Gm-C approach generally dominates. Results have been confirmed by the detailed analysis of two of the most performing analog filters from literature.

The A-to-D converter here presented is part of a bigger system able to sense and monitor electrical/physical parameters in particles detectors, for LHC experiments. The CMOS integrated circuits operating in high-energy environments experience large leakage current and voltage/temperature variations. For this reason in LHC experiments, a proper sensing and monitoring system has been designed with the aim to provide real time information about the electrical/physical scenario for the detectors in LHC. The A-to-D converter has a resolution of 12 bits, is based on single slope architecture and is able to manage 32 input analog channels. The design is challenging for several reasons, considering the required conversion accuracy and the critical physical scenario. The entire A-to-D converter has been fully characterized with process-voltage-temperature variations, obtaining a definitive 11bit accuracy in the worst-case simulation corner. The A-to-D has been designed in CMOS 0.13 mu m technology, consumes 350 mu W (including dynamic power due to the digital circuits) and operates at 20MHz clock frequency, for a definitive 2.3kHz sample rate

A low power front-end for GEM (Gas Electron Multiplier) detectors has been developed in 0.13μm CMOS node. The front-end sensitivity is 0.5mV/fC which remains almost unchanged up to a 15 pF detector parasitic capacitance. The input dynamic charge range varies from 30fC to 1pC including only a single (negative) polarity charge. The front-end provides as output signal two different time-domain square-wave signals. The first one indicates the charge detection event and the second one the amount of charge (providing a time-domain impulse, whose duty-cycle is proportional to the effective charge read by the front-end). Proper automatic calibration circuits are then implemented in order to optimize the front-end performance in case of CMOS process and temperature variations. The power consumption is 3.8mW, against 12mW in the existing market solutions [9]. A feed-forward opamp architecture has been exploited in analog part of read-out channel, in order to improve speed and time-response slope.

In this paper the complete design of a Programmable Gain Amplifier embedded in UWB receiver is presented. The receiver is part of a System-On-Chip placed inside the car tire (with the aim to interchange data with the car control unit) where dynamic stress, temperature and aging are very important issues, resulting in severe design constraints for CMOS analog integrated circuits. Furthermore, the SoC is biased by vibration-based energy scavenger, and a as consequence, very low power is available for the integrated circuits. High input impedance is required from system level constraints and this is achieved with MOS input devices, exploiting dual differential input Opamp. The PGA gain is programmable in the 15dB-to-50dB range with 1dB step. For the maximum gain level (50dB), the Input-Referred-Noise power spectral density is lower than 20nV/vHz. From a single 1V supply, for the minimum gain level (15dB), a 0.8Vzero-peak output signal is processed with THD=−40dBc.

A 90 nm-CMOS power-optimized analog baseband chain for ultra-low-power impulse-radio ultra-wideband (IR-UWB) receivers is presented. The proposed device merges the functions of a programmable gain amplifier (PGA) and a low-pass filter (LPF). It consists of the cascade of three biquadratic cells made up by opamps in a series-shunt configuration, which features high input impedance, low load effects in the cascade blocks, and better frequency response. The opamp parameters are included in the overall biquad transfer function. This allows getting very low power performance, since the opamp bandwidth is not required to be much larger than the filter cutoff frequency. Moreover, the current consumption is optimized according to the selected gain level (1.3 mA at 0 dB-gain up to 1.9 mA at 40 dB-gain). The PGA features a 0-40 dB programmable gain range with a 5 dB gain-step. The LPF performs a sixth-order 255 MHz low-pass frequency response. For the overall chain the IIP3 is 14 dBm at 0 dB gain, while the input referred noise is 12.5 nV/√Hz at 40 dB gain. © 2012 IEEE.

In this work a new concept of hybrid lamps burner is presented. The High Intensity Discharge (HID) lamps and the new generation Light Emitting Diodes (LED) lamps can be driven by the same electronic ballast using this hybrid ASIC in 0.35m CMOS technology. In the state-of-art the electronic ballasts are managed by powerful general-purpose devices (usually FPGA or microcontroller). These devices are not customized for the specific application. Thus they have a larger area occupation and power consumption compared to ASIC solution. The designed ASIC power consumption is 35 mW and the package area is about 6.5 cm2 against 550 mW and 6.5 cm2 for commonly used PIC 18FXX2. © 2011 IEEE.

In this paper the design of a 10b 100-MS/s pipeline analog-to-digital converter (ADC) with an optimized bit-stage resolution is presented. A careful analysis of the ADC architecture is presented. The proposed architecture is made by two main stages with opamp-sharing technique and a 3b full-flash ADC. The 1st stage has a 1.5b resolution architecture, the remaining stages have 2.5b resolution architecture. Furthermore, the input sampling is directly performed on the 1st stage. The ADC is implemented in 65nm digital CMOS process technology. It achieves 69.3dB spurious-free-dynamicrange (SFDR), 59.3dB signal-to-noise ratio (SNR), 9.6 effective number of bits (ENOB) for a 49MHz input at full sampling rate. The ADC power consumption is about 12.7mW from a 1.2V supply. The FOM value is about 165fJ/conv. It occupies 0.8mm 2. ©2010 IEEE.

A 90nm-CMOS power-optimized Programmable Gain Amplifier (PGA) for Ultra Low power Low Rate-Ultra Wide Band (LR-UWB) receivers is illustrated. The PGA features a 0-40dB programmable gain range with a 5dB gain-step. In addition it implements a 6th —order 240MHz Bessel lowpass transfer function. The cut-off frequency is about constant, independently on the different gain settings. At 40dB gain, the input 1dBcp is −44.8dBm, and the NF is 14.3dB. The current consumption (1.9mA at 0dB-gain up to 2.9mA at 40dB-gain) is optimized by including the opamp performance in the cell transfer function, and accordingly to the selected gain level.

A microelectronic chip for the ultra-rapid detection of cells in few micro-liters drop samples is presented. The architecture is based on a two-dimentional 640times480 array of microsites. Dielectrophoresis (DEP) is the physical phenomenon used to manipulate the cells. A corresponding array of photodiodes is used for integrated optical detection. The chip implements a column-parallel, reconfigurable read-out and A/D conversion. The single readout channel is composed by a pre-amplifier with programmable gain and an algorithmic analog-to-digital converter with a 1.5-bit/stage architecture. The chip is implemented in 0.35 mum CMOS technology with a 3.3 V supply.

In this paper the design of a programmable gain amplifier (0 dBdivide15 dB, 3 dB per step) embedded in the analog base-band chain for UWB Receivers in a standard 90 nm CMOS technology is presented. The design has been realized using a proper Matlab procedure. Due to the large bandwidth required in the UWB Receivers, the procedure takes into account the second order effects related with the opamp parasitic capacitance and finite bandwidth. In this way the model guarantees to satisfy the IRN and transfer function accuracy requirements and to avoid linearity performance degradation. Thanks to the results obtained by the Matlab procedure, no capacitance are used in the PGA schematic. From a single 1.2 V supply voltage, the PGA total current consumption is 3.5 mA, the inband IIP3 is 15 dBm and out-of-band IIP3 is 23 dBm, the maximum IRN is 16nV/radicHz at 15 dB gain.

An integrated readout circuit for Lab-on-a-Chip applications is presented. The overall system consist of a 640times480 array of capacitor sensors and actuators. Sensors detect dielectric permittivity variation thanks to dielectrophoresis (DEP) process. Usually for this kind of applications an off-chip analog-to-digital converter is used. As a consequence, the noise floor increases and high signal-to-noise ratios are difficulty achieved. On the other hand, these applications requires a stringent noise floor specification (>10b) and a relaxed linearity (ap8b). In this design, the noise coupled to the signal at the chip pad is reduced by using an on-chip analog-to-digital converter. The complete sensor readout channel is composed by two main blocks: a pre-amplifier with programmable gain and an algorithmic analog-to-digital converter with a 1.5-bit/stage architecture. Each one is realized with fully differential switched capacitor technique. In order to save chip area and power consumption a time sharing technique has been taken into account using a single operational amplifier for the preamplification stage and the conversion stage. The proposed A/D converter has 11b resolution, a sampling rate of about 100 ksample/s and an input full-scale range of 1.2 Vp-p differential. Simulation results show a SNR=65.7 dB and an ENOB value of 10.6b. Its power consumption is about 150 muW. Readout chain is implemented in 0.35 mum CMOS technology with a 3.3 V supply voltage.

In this paper two different design approaches for a large tuning range LP filter for DVB-T Receivers are presented. The LP filter is placed at the beginning of the receiver chain, before to the RF and base band blocks, so that the design is challenging because high out-band frequencies rejection is required while maintaining low input referred noise. Closed-loop topologies have been investigated to comply with the in-band linearity requirements. A system level analysis has been developed using a proper Matlab procedure. This procedure allows optimizing the basic filter parameters - opamp bandwidth, R and C values - in order to satisfy the filter transfer function requirements. Two different design approaches will be considered. The first proposal is based on a 2(nd) order biquadratic cell. High quality factor is synthesized while guaranteeing the out-of-band frequencies rejection. The second implementation is based on the cascade of two biquadratic cells with more relaxed quality factor requirement. The design is realized using the 90nm CMOS technology. The simulation results for both implementations are presented. The minimum out-of-band rejection is maintained lower than -30dB, the maximum IRN in both cases is 4nV/root Hz and the IM3 is lower than -30dB fort wo in-band input tones

The counting of the consecutive ionization clusters in a drift chamber is a very promising technique for particle identification purposes. Although this technique features a number of advantages, the bottleneck for its implementation is represented by the difficulties in realizing a low cost, high-speed electronic interface. In fact, typical time separation between each ionization act in a helium-based gas mixture is from a few ns to a few tens of ns. Thus the read-out interface has to be able to process such a high-speed signals. It will be demonstrated that a read-out channel composed of a fast, large bandwidth preamplifier and of a large conversion rate Analog-to-Digital converter fullfil all the requirements for cluster counting. The recent scaled CMOS integrated circuit technologies allows to realize such a low-cost high-speed front-end, opening the possibility of realizing efficient cluster-counter-based detectors. In this paper, a CMOS 0.13 μm integrated readout circuit, including a fast preamplifier (with a -3B bandwidth of 500MHz) and lGS/s-6bit ADC is designed for the central tracker of a future collider (ILC, super-B). The performance and the design issues associated to this architecture are discussed. © 2007 IEEE.

In this paper the design of the analog baseband chain for UWB receivers in a standard 90 nm CMOS technology is presented. The baseband chain is composed by the 5th order elliptic analog low-pass filter and a programmable gain amplifier (with up to 60 dB gain). Due to the large UWB signal bandwidth (250 MHz), the design has been carried-out using a MATLAB model taking into account the capacitance parasitics effect and the opamp finite bandwidth impact on the filter transfer function. From a single 1.2 V supply voltage, the total power consumption is 13 mA per channel, the in-band and out-of-band IIP3 is 20 dBm and the maximum IRN for G>15 dB is 9 nV/radicHz.

In this paper advances on analog filter design for telecom transceivers are addressed. Portable devices require a strong power consumption reduction to increase the battery life. Since a considerable part of the power consumption is due to the analog baseband filters, improved and/or novel analog filter design approaches have to be developed. In this paper some advances on this field reported in last years are summarized. Each design (developed for different standards) exploits the standard specifications with different architectures and circuit strategies devoted to power consumption reduction. The first is for reconfigurable Bluetooth/UMTS/WLAN receivers, the second is for very-low voltage (550mV) WLAN receivers, the third one is for impulse-radio UWB receivers, while the fourth is for very low-power OFDB-UWB receivers. © 2008 EDAA.

An analog baseband chain for a multistandard (Bluetooth, WCDMA/UMTS, and WLAN) reconfigurable receiver in a 0.25 mum CMOS uses 1.65 mm . The structure is composed by an open-loop programmable-gain amplifier (PGA1), an active-Gm-RC low-pass filter (LPF), and a closed loop programmable-gain amplifier (PGA2). The chain gain can be programmed in the range -10divide68dB, while the input-referred noise (IRN) is 5nV/radicHz. In terms of linearity, the device features an in-band output referred intermodulation intercept point (OIP3) of 21dBm in UMTS mode, and a 1dB compression point of 1.3 dBm in WLAN mode. A dynamic range (DR) larger than 78 dB is achieved for a 1% total harmonic distortion (THD). The current consumption is minimized and adjusted for the different operation conditions, down to 11 mA for the full chain.

In this paper a 4th order low-pass continuous- time filter for a WLAN receiver is presented. The filter is designed to satisfy high-linearity performance while operating at very-low supply voltage. An improved bias circuit is used to operate with different opamp input and output common-mode voltages. The filter is realized in a standard 0.13 mum CMOS technology with VTHNap250 mV and VTHPap300 mV. The filter is optimally operating with supply voltage as low as 550 mV and slightly below. The filter architecture is composed by two active Gm-RC biquadratic cells, which use a single opamp per-cell with a unity-gain-bandwidth comparable to the filter cut-off frequency. This reduces the total cell power consumption. The -3 dB frequency is at 12 MHz (for WLAN applications) and this is higher than any other low-voltage continuous-time filter. The -3 dB frequency can be adjusted by means of a digitally- controlled capacitance array. The filter total area occupancy is 0.47 mm2 and the total power consumption is 3.4 mW from a single 550 mV supply. A 8 dBm-in-band IIP3 and a 13.3 dBm-out-of-band IIP3 demonstrate the validity of the proposal.

Low Data Rate Ultra-Wideband (LR-UWB) systems have an enormous potential and compare favorably to other communication systems, in terms of capacity and low-complexity. This stems from the channels located at rather high frequencies (3.5GHz-10GHz), which offer each a large signal bandwidth (500MHz). However, these aggressive broadband frequency properties of UWB systems make the design of low-power receivers quite challenging. In this paper the circuit blocks that constitute an LR-UWB receiver are illustrated. They are designed in CMOS 90nm technology. The RF section, including LNAs and oscillators is considered first. Secondly, the problems and the circuit solutions related to the base-band section, including filters and programmable gain amplifiers are addressed. © 2007 IEEE.

We report here the results of some laboratory experiments performed to validate the effectiveness of a technique for the self tuning of integrated continuous-time, high-speed active filters. The tuning algorithm is based on the application of a pseudo-random input sequence of rectangular pulses to the device to be tuned and on the evaluation of a few samples of the input-output cross-correlation function which constitute the filter signature. The key advantages of this technique are the ease of the input test pattern generation and the simplicity of the output circuitry which consists of a digital cross-correlator. The technique allows to achieve a tuning error mainly dominated by the value of the elementary capacitors employed in the tuning circuitry. The time required to perform the timing is kept within a few microseconds. This appears particularly interesting for applications to telecommunication multi-standard terminals. The experiments regarding the application of the proposed tuning algorithm to a baseband multi-standard filter confirm most of the simulation results and show the robustness of the technique against practical operating conditions and noise

In this paper a complete design of an analog 4th order base band filter for WLAN receivers operating at 600mV supply voltage is presented. The design is based on the use of different input and output opamp common mode voltages and on the Input Common Mode Feedback circuit The ICMFB allows maximizing the overdrive voltages of the opamp input differential pair MOS, guarantying the right operating point The filter is designed using the 0.13μm CMOS technology and features a wide swing performance (DR=68dB@THD=40dBc when a 800mVpp,differential signal is applied at the filter output nodes) and a low power consumption (3.6mW). © 2007 IEEE.

In this paper an analytical procedure to design the single-opamp active-RC Rauch biquadratic cells is presented. The design procedure optimizes the trade-off between the opamp input referred noise and the thermal noise due to the filter resistors, in order to minimize the current consumption. The proposed procedure is validated by means of a benchmark of a biquadratic cell for an UMTS and WLAN applications. The design is realized using the 0.13 mu m CMOS technology with a 1.2V supply voltage

This paper presents a reconfigurable analog baseband channel for multistandard receivers. The circuit, consisting of two variable gain amplifiers and a low-pass filter, fulfills the requirements of GSM, WCDMA (UMTS), WLAN (IEEE 802.1 la/b/g), and Bluetooth. The gain, bandwidth and power consumption of the circuit are changed through a digital control word depending on the selected standard. Simulation results, including all of the tests prescribed by the different standards, confirm the validity of the proposed solution. The in-band IIP3 evaluated with maximum gain (68dB/39dB) is 5dBm/1dBm for UMTS/WLAN respectively, while the power consumption is 51.7mW/55mW in the two cases. © 2006 IEEE.

In this presentation several solutions for operating analog circuits at low power and/or low voltage will be discussed. Different approaches will be presented at transistor level, at circuit level and at system level.

This paper presents a reconfigurable universal mobile telecommunication systems [(UMTS) and wireless local area network (WLAN) mode)] analog baseband transmitter channel composed of a current steering digital-analog converter (DAC), a transimpedance stage, and a low-pass reconstruction filter. The device operates from a single 1.2-V supply voltage while guaranteeing the high-linearity UMTS/WLAN standard requirements. It can be digitally programmed to process WLAN 802.11a/b/g and UMTS signals, by adjusting the DAC conversion frequency and the low-pass filter cutoff frequency. For the WLAN mode, the DAC operating frequency and the filter bandwidth are set to 100 and 11MHz, respectively, while for the UMTS mode, they are equal to 50 and 2.11MHz. The device is realized in a 1.2-V 0.13-μm standard CMOS technology. The die area occupation, equal to 0.9mm2, has been minimized by optimizing the component sharing for the two operation modes. The proposed circuit achieves a 30.4 dBm third-order output referred intermodulation intercept point (OIP3) for the WLAN mode, and a 31.5 dBm-OIP3 when configured for the UMTS mode, while the spurious-free dynamic range is 58 dB for WLAN mode, and 60 dB for UMTS mode. The power consumption is optimized according to the operation mode and is 19.44 mW in WLAN mode and 16.8 mW in UMTS mode. © 2006 IEEE.

A 3-to-5GHz quadrature analog correlation RX for UWB impulse radio draws 16mA at 20Mpulses/s, making it suitable for low-power low-data-rate applications. The RX is fully integrated in a CMOS 0.18mum process and comprises an LNA, quadrature LO generation and mixers, baseband filtering, an integrator, timing circuitry, and an ADC

Two versions of a baseband block composed by a 8-bit current-steering DAC and a fourth-order low-pass reconstruction filter are realized in a 0.13-μm CMOS technology to be embedded in multistandard wireless transmitters. In order to satisfy the specifications of WLAN IEEE 802.11a/b/g, UMTS, and Bluetooth standards, the proposed devices can be digitally programmed, adjusting the DAC conversion frequency and the low-pass filter cut-off frequency. For the WLAN case, the DAC operating frequency and the filter bandwidth are set to 100 MHz and 11 MHz, respectively, for the UMTS case, they are equal to 50 MHz and 2.5 MHz, and for the Bluetooth case, they are equal to 50 MHz and 1 MHz. The first device is reconfigurable between WLAN and UMTS, and the second one between WLAN and Bluetooth. The two fabricated devices operate from a single 1.2-V supply voltage and occupy a 0.8 mm2 and 0.7 mm2 die area, respectively. The power consumption is optimized according to the operation mode and is 8 mW in WLAN mode, 8.4 mW in UMTS mode, and 5.4 mW in Bluetooth mode. For all the considered standards, the measured OIP3 is larger than 28 dBm, while the SFDR is 54 dB for WLAN, 61 dB for UMTS, and 63 dB for Bluetooth. © 2006 IEEE.

A low-power high-linearity Variable-Gain-Amplifier, VGA, in a 0.13μm CMOS technology to be embedded in a multi-standard receiver (WLAN, UMTS, GSM, and Bluetooth) is reported. This multi-standard receiver architecture presents considerable different VGA requirements (in terms of bandwidth, DC-gain, and common mode input voltage) for the four telecom standards to be processed. Thus the proposed VGA, in addition to the power control, is demanded to accommodate the different standards requirements and feed the one channel filter. The prototype VGA features gain levels from -10dB to 36dB, with a 25dBm IIP3 and an input-referred noise voltage lower than 5nV/√Hz at 0dB DC-gain. This gives a 85dB-DR for the WLAN case. The VGA draws 6.4mA from a single 2.5V supply. © 2006 IEEE.

A new type of transistor is presented. It is realised by using a metalloprotein; namely, azurin. Thanks to their natural functional characteristics, which involve inter- and intramolecular electron transfer, metalloproteins are good candidates for biomolecular nanoelectronics. The implementation of a prototype of protein transistor operating in air and in the solid state based on self-organised films of azurins is reported. Experimental current–voltage characteristics are shown. The new device presents an ambipolar behaviour as the gate bias voltage is changed. Exploiting this peculiar characteristic, a fully integrated logic gate which can be a good starting point for a new class of nanoelectronics devices has been realised.

A fully balanced variable gain amplifier (VGA) in 0.13 /spl mu/m CMOS technology to be used in a multistandard receivers (WLAN, UMTS, GSM, and Bluetooth) is reported. The overall architecture where the VGA is embedded presents considerable different requirements (bandwidth, dc-gain, and common mode input voltage) for the four telecom standards to be processed. The VGA features 4 gain steps with a IIP3 better than 30dBm and an input-referred noise voltage lower than 5nV//spl radic/Hz at 0dB dc-gain.

Molecules are attractive to develop nano-electronic devices. In this paper a new type of transistor is realized by using self-organized films of the Guanosine molecule, a modified DNA base. With its 40 nm channel length the transistor is a good starting point for a new class of nano-electronics devices. Experimental current-voltage characteristics are shown. A circuital model is also proposed.

In this work, a field effect transistor based on deoxyguanosine derivatives (a DNA basis) is demonstrated by means of systematic transport experiments. Our nanodevices were fabricated starting from a deoxyguanosine derivative (dG(C-10)(2)) layer interconnecting planar nano-electrodes, with separation in the 20-40nm range. The three terminal devices exhibit a maximum voltage gain of 0.76. Though the quick aging and the reproducibility of the devices have to be improved, the realization of a transistor-like device represents a starting point towards the development of planar solid-state bio-molecular electronic devices.

A low-power analog filter able to be reconfigured in order to be used in UMTS and WLAN applications is reported. The 4th order low-pass continuous-time filter is going to be included in the receiver path of a reconfigurable terminal. The filter is made up by the cascade of two Active-Gm-RC low-pass biquadratic cells. The unity-gain-bandwidth of the opamps embedded in the Active-Gm-RC cells is comparable to the filter cut-off frequency. Thus, the power consumption of the opamp can be strongly reduced. In addition, the filter can be programmed in order to process UMTS and WLAN signals, while a little area overhead is required since the filter can share capacitors as well as opamps in both operations modes. The cut-off frequency deviation due to the technological spread, aging and temperature variation is adjusted by using a tuning circuit.The full device in a 0.13 μm CMOS technology occupies a 2.8 mm2area. © 2005 Springer Science + Business Media, Inc.