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Gut microbiota, a complex microbial community inhabiting human or animal intestines recently regarded as an endocrine organ, has a significant impact on human health. Probiotics can modulate gut microbiota and the gut environment by releasing a range of bioactive compounds. Escherichia coli (E. coli) strain Nissle 1917 (EcN), a Gram-negative bacterial strain, has been used to treat gastrointestinal (GI) disorders (i.e., inflammatory bowel disease, diarrhea, ulcerative colitis, and so on). However, endotoxicity of lipopolysaccharide (LPS), a major component of the cell wall of Gram-negative bacteria in the gut, is known to have a strong influence on gut inflammation and maintenance of gut homeostasis. Therefore, characterizing the chemical structure of lipid A which determines the toxicity of LPS is needed to understand nonpathogenic colonization and commensalism properties of EcN in the gut more precisely. In the present study, MALDI multiple-stage mass spectrometry analysis of lipid A extracted from EcN demonstrates that hexaacylated lipid A (m/z 1919.19) contains a glucosamine disaccharide backbone, a myristate, a laurate, four 3-hydroxylmyristates, two phosphates, and phosphoethanolamine (PEA). PEA modification of lipid A is known to contribute to cationic antimicrobial peptide (CAMP) resistance of Gram-negative bacteria. To confirm the role of PEA in CAMP resistance of EcN, minimum inhibitory concentrations (MICs) of polymyxin B and colistin were determined using a wild-type strain and a mutant strain with deletion of eptA gene encoding PEA transferase. Our results confirmed that MICs of polymyxin B and colistin for the wild-type were twice as high as those for the mutant. These results indicate that EcN can more efficiently colonize the intestine through PEA-mediated tolerance despite the presence of CAMPs in human gut such as human defensins. Thus, EcN can be used to help treat and prevent many GI disorders.

A new pixel structure is proposed for wide dynamic range CMOS image sensors. A pixel based on a three-transistor active pixel sensor has two linear responses and a logarithmic response using additional circuits. The photogate surrounding the n+/p-sub photodiode exists for the second linear response. The logarithmic response is due to the biased MOS cascode. The proposed pixel was designed and fabricated using a 0.35- $\mu \text{m}$ 2-poly 4-metal standard CMOS process. The dynamic range of the pixel is higher than 106 dB. A test chip with a pixel pitch of $10 \times 10~\mu \text{m}^{2}$ and a $160 \times 120$ pixel array is evaluated.

This paper presents a wide dynamic range complementary metal oxide semiconductor (CMOS) image sensor with column capacitorand feedback structure. The designed circuit has been fabricated by using 0.18im 1-poly 6-metal standard CMOS technology. This sen-sor has dual mode operation using combination of active pixel sensor (APS) and passive pixel sensor (PPS) structure. The proposedpixel operates in the APS mode for high-sensitivity in normal light intensity, while it operates in the PPS mode for low-sensitivity inhigh light intensity. The proposed PPS structure is consisted of a conventional PPS with column capacitor and feedback structure. Thecapacitance of column capacitor is changed by controlling the reference voltage using feedback structure. By using the proposed struc-ture, it is possible to store more electric charge, which results in a wider dynamic range. The simulation and measurement results dem-onstrate wide dynamic range feature of the proposed PPS.Keywords: CMOS image sensor, Column capacitor, Feedback structure, Dual mode

This paper presents an extension of the dynamic range in a complementary metal-oxide-semiconductor (CMOS) active pixel sensor(APS) using a stacked photodiode and feedback structure. The proposed APS is composed of two additional MOSFETs and stackedP+/N-well/P-sub photodiodes as compared with a conventional APS. Using the proposed technique, the sensor can improve the spectralresponse and dynamic range. The spectral response is improved using an additional stacked P+/N-well photodiode, and the dynamicrange is increased using the feedback structure. Although the size of the pixel is slightly larger than that of a conventional three-transistorAPS, control of the dynamic range is much easier than that of the conventional methods using the feedback structure. The simulation andmeasurement results for the proposed APS demonstrate a wide dynamic range feature. The maximum dynamic range of the proposedsensor is greater than 103 dB. The designed circuit is fabricated by the 0.35- um 2-poly 4-metal standard CMOS process, and itscharacteristics are evaluated.

A dynamic range extension technique is proposed based on a 3-transistor active pixel sensor (APS) with gate/body-tied p-channel metal oxide semiconductor field effect transistor (PMOSFET)-type photodetector using a feedback structure. The new APS consists of a pseudo 3-transistor APS and an additional gate/body-tied PMOSFET-type photodetector, and to extend the dynamic range, an NMOSFET switch is proposed. An additional detector and an NMOSFET switch are integrated into the APS to provide negative feedback. The proposed APS and pseudo 3-transistor APS were designed and fabricated using a 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) process. Afterwards, their optical responses were measured and characterized. Although the proposed pixel size increased in comparison with the pseudo 3-transistor APS, the proposed pixel had a significantly extended dynamic range of 98 dB compared to a pseudo 3-transistor APS, which had a dynamic range of 28 dB. We present a proposed pixel that can be switched between two operating modes depending on the transfer gate voltage. The proposed pixel can be switched between two operating modes depending on the transfer gate voltage: normal mode and WDR mode. We also present an imaging system using the proposed APS.

"Memory" is an essential building block in learning and decision-making in biological systems. Unlike modern semiconductor memory devices, needless to say, human memory is by no means eternal. Yet, forgetfulness is not always a disadvantage since it releases memory storage for more important or more frequently accessed pieces of information and is thought to be necessary for individuals to adapt to new environments. Eventually, only memories that are of significance are transformed from short-term memory into long-term memory through repeated stimulation. In this study, we show experimentally that the retention loss in a nanoscale memristor device bears striking resemblance to memory loss in biological systems. By stimulating the memristor with repeated voltage pulses, we observe an effect analogous to memory transition in biological systems with much improved retention time accompanied by additional structural changes in the memristor. We verify that not only the shape or the total number of stimuli is influential, but also the time interval between stimulation pulses (i.e., the stimulation rate) plays a crucial role in determining the effectiveness of the transition. The memory enhancement and transition of the memristor device was explained from the microscopic picture of impurity redistribution and can be qualitatively described by the same equations governing biological memories.

In this paper, we propose a vision system using a field programmable gate array(FPGA) and a smart vision chip. The output of the vision chip is varied by illumination conditions. This chip is suitable as a surveillance system in a dynamic environment. However, because the output swing of a smart vision chip is too small to definitely confirm the warning signal with the FPGA, a modification was needed for a reliable signal. The proposed system is based on a transmission control protocol/internet protocol(TCP/IP) that enables monitoring from a remote place. The warning signal indicates that some objects are too near.

Nanoscale memristive devices using tungsten oxide as the switching layer have been fabricated and characterized. The devices show the characteristics of a flux-controlled memristor such that the conductance change is governed by the history of the applied voltage signals, leading to synaptic behaviors including long-term potentiation and depression. The memristive behavior is attributed to the migration of oxygen vacancies upon bias which modulates the interplay between Schottky barrier emission and tunneling at the WOX/electrode interface. A physical model incorporating ion drift and diffusion effects using an internal state variable representing the area of the conductive region has been proposed to explain the observed memristive behaviors. A SPICE model has been further developed that can be directly incorporated into existing circuit simulators. This type of device can be fabricated with low-temperature processes and has potential applications in synaptic computations and as analog circuit components.

In this paper, a dynamic range(DR) extension technique based on a 3-transistor active pixel sensor(APS) and dual image sampling is proposed. The feature of the proposed APS is that the APS uses two or more photodiodes with different sensitivities, such as a high-sensitivity photodiode and a low-sensitivity photodiode. Compared with previously proposed wide DR(WDR) APS, the proposed approach has several advantages, such as no-external equipments or signal processing, no-additional time-requirement for additional charge accumulation, simple operation and adjustable DR extension by controlling parasitic capacitance and sensitivity of two photodiodes. Approximately 16 dB of DR extension was evaluated from the simulation for the situation of 10 times of sensitivity difference and the same size of parasitic capacitance between those two photodiodes.

We have designed and fabricated an active pixel sensor(APS) using an optimized n-well/gate-tied p-channel metal oxide semiconductor field effect transistor(PMOSFET)-type photodetector with a built-in transfer gate. This photodetector has a floating gate connected to n-well and a built-in transfer gate. The photodetector has been optimized by changing the length of the transfer gate. The APS has been fabricated using a 0.35 standard complementary metal oxide semiconductor(CMOS) process. It was confirmed that the proposed APS has a wider dynamic range than the APS using the previously proposed photodetector and a higher sensitivity than the conventional APS using a p-n junction photodiode.

We report studies on a nanoscale resistance switching memory structure based on planar silicon that is fully compatible with CMOS technology in terms of both materials and processing techniques employed. These two-terminal resistance switching devices show excellent scaling potential well beyond 10 Gb/cm2 and exhibit high yield (99%), fast programming speed (5 ns), high on/off ratio (10(3)), long endurance (10(6)), retention time (5 months), and multibit capability. These key performance metrics compare favorably with other emerging nonvolatile memory techniques. Furthermore, both diode-like (rectifying) and resistor-like (nonrectifying) behaviors can be obtained in the device switching characteristics in a controlled fashion. These results suggest that the CMOS compatible, nanoscale Si-based resistance switching devices may be well suited for ultrahigh-density memory applications.

The suppression of sneak paths in a cross-point RRAM array, one of the most challenging tasks in high density RRAM integration, has been successfully demonstrated by utilizing a Field Assisted Superlinear Threshold (FAST) selector (1, 2). The FAST selector provides a volatile switching behavior at the critical electric field. Excellent selector performance is presented, including high selectivity of > 107, sharp switching slope of 1011. Furthermore, the volatile switch based selector offers various benefits such as small operation voltage overhead in the 1S1R (1 selector 1 resistor) integration, large sensing margin and increased memory ON/OFF ratio.

A novel high-sensitivity active pixel sensor (APS) with a variable threshold photodetector has been presented and for the first time, a simple SPICE model for the variable threshold photodetector is presented. Its SPICE model is in good agreement with measurements and is more simpler than the conventional model. The proposed APS has a gate/body-tied PMOSFET-type photodetector with an overlapping control gate that makes it possible to control the sensitivity of the proposed APS. It is a hybrid device composed of a metal-oxide-semiconductor field-effect transistor (MOSFET), a lateral bipolar junction transistor (BJT) and a vertical BJT. Using sufficient overlapping control gate bias to operate the MOSFET in inversion mode, the variable threshold photodetector allows for increasing the photocurrent gain by 10 5 at low light intensities when the control gate bias is -3 V. Thus, the proposed APS with a variable threshold photodetector has better low-light-level sensitivity than the conventional APS operating mode, and it has a variable sensitivity which is determined by the control gate bias. The proposed sensor has been fabricated by using 0.35 μm 2-poly 4-metal standard complementary MOS (CMOS) process and its characteristics have been evaluated.

In this paper, a complementary metal oxide semiconductor (CMOS) binary image sensor based on a gate/body-tied (GBT) MOSFET-type photodetector is proposed. The proposed CMOS binary image sensor was simulated and measured using a standard CMOS 0.18-μm process. The GBT MOSFET-type photodetector is composed of a floating gate (n+- polysilicon) tied to the body (n-well) of the p-type MOSFET. The size of the active pixel sensor (APS) using GBT photodetector is smaller than that of APS using the photodiode. This means that the resolution of the image can be increased. The high-gain GBT photodetector has a higher photosensitivity compared to the p-n junction photodiode that is used in a conventional APS. Because GBT has a high sensitivity, fast operation of the binary processing is possible. A CMOS image sensor with the binary processing can be designed with simple circuits composed of a comparator and a Dflip- flop while a complex analog to digital converter (ADC) is not required. In addition, the binary image sensor has low power consumption and high speed operation with the ability to switch back and forth between a binary mode and an analog mode.

In this paper, we propose a stacked-photodiode structure to extend the dynamic range of the CMOS active pixel sensor (APS). The proposed APS uses two photodiodes with different sensitivities and two additional MOSFETs in comparison with a conventional 3-transistor APS. Although the size of pixel is slightly larger than that of conventional 3-transistor APS, extension of the dynamic range is much easier than conventional methods by adjusting the reference voltage. The dynamic range of the proposed APS was greater than 103 dB. The designed circuit has been fabricated by using 0.35 µm 2-poly 4-metal standard CMOS technology and its characteristics have been evaluated.

A double-photodiode feedback structure to extend the dynamic range (DR) of the CMOS active pixel sensor (APS) has been proposed in this paper. Since the proposed APS requires one additional photodiode and two additional nMOSFETs in comparison with a conventional 3-transistor (TR) APS, the size of pixel is slightly larger than that of conventional 3-TR APS. However, extension of the dynamic range is much easier than conventional methods by adjusting the reset voltage and photo current of the additional photodiode. The proposed APS exhibits a wide and variable dynamic range with high sensitivity at low illumination and low sensitivity at high illumination.

Various approaches have been utilized to extend the dynamic range of the CMOS image sensor, which are based on a linear-logarithmic CIS, overflow integration capacitor and multiple sampling or individual pixel resetting. These approaches, however, suffer from noise, nonlinearity, lower sensitivity, reduced operating speed and lower resolution. In order to overcome these problems, we have previously proposed a dynamic range extension method by combining output signals from two photodiodes with different sensitivities, such as a high-sensitivity photodiode and a low-sensitivity photodiode. The proposed active pixel sensor has been fabricated by using 2-poly 4-metal standard CMOS process and its characteristics have been measured. It is found that charges in the high- and low-sensitivity photodiodes could be mixed each other and the lost image information of the high-sensitivity photodiode could be regenerated using the charges in the low-sensitivity photodiode, as shown by simulation results. Dynamic range extension of the proposed active pixel sensor has been experimentally verified.

A vision system for remote surveillance has been proposed using a field programmable gate array (FPGA) and a smart vision chip. Because of the vision chip's characteristics, the output value is less fluctuated by illumination condition. The system based on transmission control protocol / internet protocol (TCP/IP) enables to monitor the remote place. Light emitting diode (LED) was used as an indicator which expresses the warning signal from the system.

We report studies on nanoscale Si-based memristive devices for memory and neuromorphic applications. The devices are based on ion motion inside an insulating a-Si matrix. Digital devices show excellent performance metrics including scalability, speed, ON/OFF ratio, endurance and retention. High density non-volatile memory arrays based on a crossbar structure have been fabricated and tested. Devices inside a 1kb array can be individually addressed with excellent reproducibility and reliability. By adjusting the device and material structures, nanoscale analog memristor devices have also been demonstrated. The analog memristor devices exhibit incremental conductance changes that are controlled by the charge flown through the device. The performances of the digital and analog devices are thought to be determined by the formation of a dominant conducting filament and the continuous motion of a uniform conduction front, respectively.

A memristor is a two-terminal electronic device whose conductance can be precisely modulated by charge or flux through it. Here we experimentally demonstrate a nanoscale silicon-based memristor device and show that a hybrid system composed of complementary metal−oxide semiconductor neurons and memristor synapses can support important synaptic functions such as spike timing dependent plasticity. Using memristors as synapses in neuromorphic circuits can potentially offer both high connectivity and high density required for efficient computing.

A dynamic range (DR) extension technique based on a 3-transistor (3-Tr.) active pixel sensor (APS) and dual image sampling has been proposed. The feature of the proposed APS was that the APS used two photodiodes with different sensitivities, a high-sensitivity photodiode and a low-sensitivity photodiode. Operation of the proposed APS was simulated by using a 128×128 pixel array. Compared with previously proposed wide DR (WDR) APS, the proposed approach has several advantages; no-external equipments or signal processing for combining images, no-additional timerequirement for additional charge accumulation, adjustable DR extension and no temporal disparity.

In this paper, a highly sensitive gate/body-tied p-channel metal oxide semiconductor field effect transistor (PMOSFET)-type photodetector with an overlapping control gate is proposed. The proposed photodetector has an overlapping control gate that makes it possible to control the sensitivity of the proposed photodetector. This sensitivity controllability extends the dynamic range and provides a high sensitivity in a low-light environment. The body of the proposed gate/body-tied PMOSFET-type photodetector is connected to the floating gate, and the control gate is placed on top of the floating gate. The proposed device was fabricated using a 0.35 µm standard complementary metal oxide semiconductor (CMOS) process. The amplified photocurrent of the proposed device was more than 100 times larger than that of a conventional n+/p-sub photodiode with the same area. The area of the proposed photodetector is 3.8×4.4 µm2, which is 24% smaller than that of a conventional gate/body-tied PMOSFET-type photodetector with a transfer gate. Therefore, the proposed photodetector can be suitable for high-sensitivity active pixel sensors (APSs) because of its much higher responsivity than that of a conventional n+/p-sub photodiode.

We report studies on nanoscale resistive memory devices that exhibit diodelike I-V characteristics at on-state with reverse bias current suppressed to below 10−13 A and rectifying ratio >106. The intrinsic diodelike characteristics are robust during device operation and can survive >108 write/erase programming cycles. The devices can be programmed at reduced programming voltages compared to earlier studies without the initial high-voltage forming process. Multibit storage capability was also reported. The intrinsic diode characteristics provide a possible solution to suppress crosstalk in high-density crossbar memory or logic arrays particularly for those based on bipolar resistive switches (memristors).