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This article focuses on the characterization and architecture of a new mixed design approach to monolithic CMOS-silicon-photomultiplier (SiPM), where the mixed-signal circuitry as well as the logical concepts are implemented at the die level. The new architecture contains two key areas: 1) a method for sampling, filtering, and converting the electrical signal generated by the SiPM to the digital domain by taking advantage of the nature of the SiPM as an “optical-to-digital converter” and 2) a fully digital configurable method, which requires just one clock generator, enabling sampling at an adjustable time window (gating method) and reduces background noise. We report the design, simulation, and measurement results. The system was fabricated at a low-cost $0.18~\mathrm {[{\mu {\mathrm{ m}}}]}0.18$ - $\mu \text{m}$ CMOS process yet achieves a clock rate of 1 GHz, high timing and photon counting resolution, and low jitter. The reported demonstrator may be applied to 3-D range measurements, light detection and ranging (LIDAR), time-of-flight (ToF) system, and gaming systems.

We report here the formation of porous silicon under alternating current conditions. Instead of applying the usual direct current electrochemical process, an alternating current was applied with a given frequency and peak voltage. The porous silicon layer properties are equivalent to the properties that would be achieved by the standard direct current formation technique (i.e., same porosity level). The main advantages of this process are: (a) The alternating current formed porous silicon exhibits higher mechanical stability during the drying step than layers formed using the standard direct current technique. (b) The alternating current process can be performed without a deposited backside contact. These simplify the process and permit its integration with high temperature processing steps and clean furnaces of a modern very large sale-integrated technology.

1/f noise currents have been measured in HgCdTe photodiodes and gate‐controlled diodes as a function of gate bias, diode voltage, and dark (leakage) currents. The diodes are fabricated by ion implanting boron (n+) on bulk p‐type material with x=0.22. Native anodic sulfide in combination with deposited ZnS is used for surface passivation. The measurements demonstrate that the dominant mechanism that produces 1/f noise in HgCdTe photodiodes is tunneling. With the gated diodes it is possible to separate bulk and surface related mechanisms responsible for the 1/f noise currents. 1/f noise currents are produced by surface‐induced tunneling at pinched‐off depletion regions adjacent to accumulated surfaces and by tunneling across field‐induced junctions underneath inverted surfaces. Bulk trap‐assisted tunneling that limits the R0A product below 50 K but is masked by diffusion at 77 K, is responsible for the 1/f noise currents at optimized surface potentials, (i.e., approximately flat‐band conditions) at low bias...

Noise measurements of the 1/f noise in p-MOS and n-MOS transistors for analog applications are reported under wide bias conditions ranging from subthreshold to saturation. Two implementations (in "regular" and SOI wafers) of the 0.35 /spl mu/m CMOS process are compared and it is found that they exhibit similar 1/f noise. The results of this characterization of the 0.35 /spl mu/m process are compared with the similar characterization results of the 0.5 /spl mu/m CMOS process. The results of this study are useful in the design and modeling of 1/f noise of CMOS analog circuits.

Design, operation and measurement results of a CMOS camera implemented within a SOI wafer are presented. The peak of photodiode quantum efficiency is obtained for the wavelengths of 400-500 nm. In addition, noise measurements of the 1/f noise in P-MOS and N-MOS transistors for analog applications are reported under wide bias conditions ranging from subthreshold to saturation. Two implementations (in regular and SOI wafers) of 0.35 /spl mu/m CMOS analog process are compared and it is found that they exhibit similar 1/f noise. The results of this study are useful to the design and modeling of 1/f noise of CMOS analog circuits.

Trap‐assisted tunneling in Hg1−xCdxTe photodiodes (with x≂0.22) is modeled quantitatively. The model takes into consideration two types of deep traps: one type of energy trap is located at Et1≂40 meV (∼Eg/3) and the other type is located at Et2≂75 meV (∼2Eg/3). The density of trapped electrons at Et1∼Eg/3 is relatively high (nt1≂1014 cm−3) and is practically independent of temperature while the density of the trapped electrons at Et2≂2Eg/3 is low (nt2≂1010–1012 cm−3) and increases with temperature. An excellent fit is systematically obtained between the calculated and measured dc dark current characteristics of typical ion implanted n+p photodiodes, in a wide range of reverse bias voltages (0

Hg1−xCdxTe metal‐insulator‐semiconductor (MIS) devices with x≂0.22 often exhibit very short storage times that are determined by minority‐carrier dark currents. This study describes a novel system, for measuring the fast collapse of such devices. The measurement and modeling of the dark current during the fast collapse process is presented. A quantitative correlation is noticeable between the experimental results and theoretical calculations which assume that thermal‐trap‐assisted tunneling is the dominant dark process. The results demonstrate the importance of trap‐assisted tunneling in narrow band‐gap HgCdTe, and that this process causes short storage times.Hg1−xCdxTe metal‐insulator‐semiconductor (MIS) devices with x≂0.22 often exhibit very short storage times that are determined by minority‐carrier dark currents. This study describes a novel system, for measuring the fast collapse of such devices. The measurement and modeling of the dark current during the fast collapse process is presented. A quantitative correlation is noticeable between the experimental results and theoretical calculations which assume that thermal‐trap‐assisted tunneling is the dominant dark process. The results demonstrate the importance of trap‐assisted tunneling in narrow band‐gap HgCdTe, and that this process causes short storage times.

A new experimental setup for the study of 1/ f noise of metal‐oxide‐semiconductor transistor under nonsteady state conditions is presented. The noise measurements demonstrate for the first time that, by interposing periods of negative bias corresponding to accumulation between the monitored periods of positive bias corresponding to inversion, the low‐frequency noise sampled in the positive bias intervals is reduced.

The 1/f noise currents and the dc dark current–voltage characteristics are measured over a wide range of reverse bias voltages (0≤Vd≤−1.5 V) and operating temperatures (30–120 K). The diodes are fabricated by ion implanting boron (n+) on bulk p‐type material with x≊0.22. Native anodic sulfide in combination with deposited ZnS is used for surface passivation. The dc dark currents of the photodiodes are modeled to extract the tunneling currents from the measured dark currents. The modeling takes into consideration diffusion, generation–recombination, and the two types of tunneling currents (trap assisted tunneling and band to band tunneling). The measurements demonstrate that the dominant mechanism that produces 1/f noise in HgCdTe photodiodes is tunneling, in particular trap assisted tunneling. The correlation between the 1/f noise currents and the dc tunneling currents is given by In=α(It)β(f )−1/2, where It is the tunneling current. The empirical factors β and α are approximately β≊0.5 and α≊1×10−6 for a...

The cutoff wavelength λco at 77 K of implanted n+‐on‐bulk p‐type Hg1−xCdxTe photodiodes is calculated with the minority‐carrier lifetime of the bulk material as a parameter: 1.24/λco=[T+81.9/3.267×104(1+x)] {18.88−53.61x− 1/2 ln [(kT/q) μnτn]} −0.3424+1.838x+0.148x4 (eV). The composition x is obtained from the zero‐intercept transmission spectra measured at 300 K. The minority‐carrier lifetime τn of the photodiodes and its temperature dependence have been obtained from the photodiode dynamic resistance at zero‐bias voltage versus reciprocal temperature 1/T data. The temperature dependence of the minority‐carrier mobility μn is also taken into account. The results indicate that the lifetime in the bulk p‐type material is determined by Shockley–Read generation‐recombination centers. For undoped, p‐type substrates obtained from Cominco Inc., the trap energy is approximately 45 meV. Gold‐doped crystals grown by the method of solid‐state recrystallization exhibit a trap energy of the order of 30–35 meV.

Measured capacitance and dynamic conductance characteristics of metal–insulator–semiconductor (MIS) devices as a function of gate bias, frequency, and temperature are reported. The results demonstrate the quality of the interface for the realization of photodiodes and MIS devices on p‐type HgCdTe. The measured small‐signal dynamic resistance of the p‐type semiconductor is compared with the R0 A product of photodiodes fabricated on the same substrates. The correlation between the measured R0 A of the substrate and the R0 A of the photodiodes suggests that the R0 A product is essentially determined by the substrate. The temperature dependence of the R0 A of the substrates, as determined from the MIS devices, shows that both diffusion and generation–recombination mechanisms contribute to the dark current in p‐type Hg1−x Cdx Te with x=0.2. This is in contrast to n+ p photodiodes where the dominant mechanism is diffusion.

A novel growth process of Hg1−xCdxTe epitaxial layers by a combination of open‐tube vapor phase epitaxy (VPE) and liquid phase epitaxy (LPE) techniques is described. Device‐quality layers with improved morphology, reduced misfit dislocations, and a reflecting boundary with very low surface recombination velocity at the substrate interface are obtained by this method. High performance photodiodes operating at both 77 and 193 K with cut‐off wavelengths of 6.2 and 5.3 μm respectively were fabricated. The epitaxial layers obtained on bulk CdTe by the combination of VPE and LPE are in some respects better than layers grown by LPE on alternate substrates such as CdZnTe. off