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In this article, we propose a novel chaotic neuron circuit with memristive neural synapses, construct an architecture of memristive chaotic neural network (MCNN) and implement associative memory application of bipolar images. The proposed neuron circuit mainly consists of synapse module and neuron module with chaotic dynamics characteristics. The synapse module is composed of memristors which represent synaptic weights. The neuron module employs voltage feedback operational amplifiers to accomplish integral operation and output function. MCNN utilizes a memristor crossbar array to perform matrix operations and can process the information in parallel. In addition, the proposed circuit of MCNN can accomplish continuous recursive operations and meet different applications due to the programmability of the memristor. The ex-situ method is utilized to train the memristor crossbar array. Furthermore, the associative memory applications of bipolar images are carried out based on the constructed circuits of MCNN with three and nine neurons. The simulation results in PSPICE software testify the functions of the MCNN circuit.

Spike-timing-dependent plasticity (STDP) is a fundamental synaptic learning rule observed in biology that leads to numerous behavioral and cognitive outcomes. Emulating STDP in electronic spiking neural networks with high-density memristive synapses is, therefore, of significant interest. While one popular method involves pulse-shaping the spiking neuron output voltages, an alternative approach is outlined in this article. The proposed STDP implementation uses time-varying dynamic resistance [ ${R}$ ( ${t}$ )] elements to achieve local synaptic learning from spike-pair STDP, spike triplet STDP, and firing rates. The ${R}$ ( ${t}$ ) elements are connected to each neuron circuit, thereby maintaining synaptic density and leveraging voltage division as a means of altering synaptic weight (memristor voltage). Example ${R}$ ( ${t}$ ) elements with their corresponding behaviors are demonstrated through simulation. A three-input-two-output network using single-memristor synaptic connections and ${R}$ ( ${t}$ ) elements is also simulated. Network-level effects, such as nonspecific synaptic plasticity, are discussed. Finally, spatiotemporal pattern recognition (STPR) using ${R}$ ( ${t}$ ) elements is demonstrated in simulation.

Voltages and currents in a memristor crossbar can be significantly affected due to nonideal effects such as parasitic source, line, and neuron resistance. These nonideal effects related to the parasitic resistance can cause the degradation of the neural network’s performance realized with the nonideal memristor crossbar. To avoid performance degradation due to the parasitic-resistance-related nonideal effects, adaptive training methods were proposed previously. However, the complicated training algorithm could add a heavy computational burden to the neural network hardware. Especially, the hardware and algorithmic burden can be more serious for edge intelligence applications such as Internet of Things (IoT) sensors. In this paper, a memristor-CMOS hybrid neuron circuit is proposed for compensating the parasitic-resistance-related nonideal effects during not the training phase but the inference one, where the complicated adaptive training is not needed. Moreover, unlike the previous linear correction method performed by the external hardware, the proposed correction circuit can be included in the memristor crossbar to minimize the power and hardware overheads for compensating the nonideal effects. The proposed correction circuit has been verified to be able to restore the degradation of source and output voltages in the nonideal crossbar. For the source voltage, the average percentage error of the uncompensated crossbar is as large as 36.7%. If the correction circuit is used, the percentage error in the source voltage can be reduced from 36.7% to 7.5%. For the output voltage, the average percentage error of the uncompensated crossbar is as large as 65.2%. The correction circuit can improve the percentage error in the output voltage from 65.2% to 8.6%. Almost the percentage error can be reduced to ~1/7 if the correction circuit is used. The nonideal memristor crossbar with the correction circuit has been tested for MNIST and CIFAR-10 datasets in this paper. For MNIST, the uncompensated and compensated crossbars indicate the recognition rate of 90.4% and 95.1%, respectively, compared to 95.5% of the ideal crossbar. For CIFAR-10, the nonideal crossbars without and with the nonideal-effect correction show the rate of 85.3% and 88.1%, respectively, compared to the ideal crossbar achieving the rate as large as 88.9%.

Hybrid memristor-CMOS techniques have been recently proposed to build large-scale neural networks with learning capabilities. The intrinsic characteristics of memristors make them specially suited to implement synaptic connections between layers of spiking neurons, undergoing STDP learning (Spike-Timing-Dependent Plasticity) mechanisms when processing spikes with particular shapes. In a previous work, we proposed a tunable spiking neuron circuit which can generate spikes with controllable shape. In this work, the spike generator circuit has been implemented in FDSOI 28nm technology, and it has demonstrated its capability to produce spikes with pulse widths in the range between $8\mu {s}$ and 100ms.

International audience; Brain-inspired computing architectures, brought by Artificial Neural Networks (ANNs), are an attractive solution to reduce the energy consumption of the conventional von Neumann's computation, with an excellent parallel processing capability. Therefore, critical applications, such as Space & Satellite, which impose severe constraints in terms of power consumption and computing efficiency, are excellent candidates to embed such networks. Nonetheless, integrated circuits operating during long-term and cumulative exposure to incidence levels of ionizing radiation may have their physical components degraded, thus drastically reducing their reliability and expected lifetime. A possible solution to enhance the radiation hardening characteristics of a conventional bulk CMOS device is to use the non-standard gate geometry referred to as Enclosed Layout Transistor (ELT). In this work, we propose to harden the design of an existing OxRAM-based neuron circuit [1] through the inclusion of ELTs, i.e., to improve the radiation hardening characteristics of a preexistent convenient neuron circuit topology by using the enclosed gate geometry for the n,pMOS devices. Electrical simulations, considering a standard commercial bulk CMOS fabrication process, in a 180 nm technology, have been carried out to validate our proposed design. The simulation results, supported by the analysis of former works regarding the incidence of ionizing radiation in OxRAM and ELTs, indicate that the proposed hardened neuron circuit is a feasible solution to embed neuromorphic computing in aerospace applications.

To address the ever-increasing computational demands of machine learning applications, neuromorphic computing has emerged as a possible solution. The goal is to design a platform able to mimic the processing strategies of the brain. A neuromorphic system is composed by artificial neurons and synapses implemented in hardware with high level of integration. Such implementations entail challenges including power-efficiency, compactness and biophysical resemblance. This work proposes a new implementation of a neuron circuit, initially introduced by Wijekoon and Dudek. We show that the proposed neuron, designed in a standard 0.18µm CMOS process, consumes 58.5fJ/spike at 0.2V supply voltage. The area covered by the circuit is 16.8% of the area of the state-of-the-art implementation. This result was achieved by lowering the membrane capacitance and the number of transistors. In addition, spiking activity unfolds on a biological time scale - rather than accelerated. The circuit preserves the possibility of being adjusted by external biases to attain different firing patterns.

Spiking neural networks (SNNs) are widely used in many fields because they work closer to biological neurons. However, due to its computational complexity, many SNNs implementations are limited to computer programs. First, this paper proposes a multi-synaptic circuit (MSC) based on memristor, which realizes the multi-synapse connection between neurons and the multi-delay transmission of pulse signals. The synapse circuit participates in the calculation of the network while transmitting the pulse signal, and completes the complex calculations on the software with hardware. Secondly, a new spiking neuron circuit based on the leaky integrate-and-fire (LIF) model is designed in this paper. The amplitude and width of the pulse emitted by the spiking neuron circuit can be adjusted as required. The combination of spiking neuron circuit and MSC forms the multi-synaptic spiking neuron (MSSN). The MSSN was simulated in PSPICE and the expected result was obtained, which verified the feasibility of the circuit. Finally, a small SNN was designed based on the mathematical model of MSSN. After the SNN is trained and optimized, it obtains a good accuracy in the classification of the IRIS-dataset, which verifies the practicability of the design in the network.

The pure circuit implementation of STDP is a worthwhile work. In this study, a novel spiking neuron circuit and STDP learning circuit based on memristors are designed. The proposed spiking neuron circuit, which is based on conventional leaky integrate-and-fire neuron and utilizes the nonlinear variation of memristance, is served to generate spikes. Different release thresholds and amplitudes of the spikes can be obtained through tuning circuit parameters. Extending on the spiking neuron circuit, a STDP learning circuit is built to perform unsupervised learning behaviors. Furthermore, a crossbar array architecture is finally considered to fabricate multi-input multi-output spiking neural network which also perform STDP learning effectively. Circuit simulation results in PSPICE prove the availability of the two proposed circuits.

Adaptive response to timely constant stimuli is a common feature of biological neurons. Implementation of neurons with such features is important for achieving biologically plausible networks using electronic systems. Emerging memristor devices open new horizons in electronically implementation of neural networks with high integration density and low power consumption. Promising potential applications can be considered for mem-elements (memristor, memcapacitor, and meminductor) with their built-in memory-properties. Since the dynamics of mem-elements makes them suitable for direct emulation of biological features of real neurons, it is expected that implementation of real neurons with complicated behavior to be straightforward using mem-element without complicating the implementation of the whole neuron circuit. Mem-elements are still unavailable commercially, so we utilize the mem-elements emulators to evaluate the feasibility of using these elements in the implementation of adaptive neurons. To ensure that there is the possibility of practical implementation of our neuron circuit, we used mem-elements emulators in SPICE simulations instead of mem-elements behavioral models. This work is among the first papers in the implementation of adaptive neurons using mem-elements. Here, using memristor and memcapacitor emulators the neuristor with adaptive behavior is implemented in SPICE environment. We use two different methods for induction of adaptive behavior to the neuristor response. In the first method, the capacitor in the primary circuit of neuristor is replaced with memcapacitor. Alternatively, the coupling resistor in the primary circuit of neuristor is replaced with the memristor in the second method. Results show that, the feature of memristor/memcapacitor in changing its resistance/capacitance during time upon excitation with current or voltage, makes the neuristor behavior to be adaptive in both methods, i.e. the neuristor shows the spike-frequency adaptation behavior in response to the continuous external stimulus, where the frequency of generated spikes depends on the duration of the external input stimulus.

The nonvolatility and resistance variability of memristor make it a candidate for emulating complex dynamic behaviors in the neural system. In this paper, the memristive neuron with homeostatic plasticity is implemented. The memristor is applied to the neuron circuit, and its memristance represents the membrane sensibility of neurons. Composed of a trigger module, a pulse generation module and a feedback module, the memristor-based neuron can adaptively adjust the firing rate of neuron and maintain it in the inherent firing rate range, which shows similarities to its biological counterpart. The proposed design can mimic firing rate behaviors of the electrophysiological experiment performed in rodent, where the homeostatic plasticity of neuron is inhibited by sleep signal and promoted by wake signal. Furthermore, all the simulations are conducted in Cadence PSPICE, and the functionality of the design is proved with the simulation.

We have developed a cellular neural network formed by simplified processing elements composed of thin-film transistors. First, we simplified the neuron circuit into a two-inverter two-switch circuit and the synapse device into only a transistor. Next, we composed the processing elements of thin-film transistors, which are promising for giant microelectronics applications, and formed a cellular neural network by the processing elements. Finally, we confirmed that the cellular neural network can learn multiple logics even in a small-scale neural network. Moreover, we verified that the cellular neural network can simultaneously recognize multiple simple alphabet letters. These results should serve as the theoretical bases to realize ultra-large scale integration for brain-type integrated circuits.

We present a low-power compact circuit for the event-driven readout of tactile sensors. The taxel is based on the POSFET device, a sensotronic unit where a piezo-electric material is deposited on the gate of a transistor, integrated with a Leaky-Integrate and Fire neuron circuit. This device encodes the applied force with trains of digital pulses, using the asynchronous Address Event Representation protocol. The instantaneous output spiking frequency is directly proportional to the force applied to the taxel. We show a full characterization of the device as well as quantitative measurements from a prototype fabricated on AMS CMOS 350-nm process. The taxel can reliably distinguish applied forces from 0.1 N up to 1.5 N.

The authors present a spike-triggered adaptive neuron circuit with input current modulation. Unlike adaptive neuron circuits where adaptation is realised by leakage modulation, the circuit presented in this Letter modulates the input current to membrane capacitor. Therefore, it is possible to reduce extra power consumption originating from increased leakage. Threshold voltage modulation of silicon on insulator (SOI) MOSFET by back gate effect is used to change the amount of injected current for the same input voltage. Through this method, the circuit in this work consumed 25.9% less power than the one modulating leakage.

International audience; CMOS neuron circuits used to implement neuromorphic chips require extensive circuitry to program the memristive cell, thus eliminating most of the density advantage gained by the adoption of memristive synapses. This paper presents a CMOS neuron circuit that provides a compact and cost-efficient programming interface in which semiconductor capacitors are replaced by a memristive device. The neuron circuit also features an adjustable firing threshold with a strict control of the power consumption during the learning process.

Silicon neuron circuits emulate the electrophysiological behavior of real neurons and conductances. A detailed model mapped onto silicon neuron can be beneficial to the improvement of circuit design. Here we present a dynamic systems approach to obtain a detailed mathematical model describing the dynamics of a biophysically realistic silicon neuron. The approximate analytic solution of its firing rate fits simulation data from our neuron chip fabricated using a 130 nm CMOS process very well. Meanwhile, transistors that contribute critically to variation of firing activities are discovered, which helps the improvement of neuron mismatch.

The brained-inspired spiking neural networks (SNNs), which can be applied on visual information processing and speech recognition, is attracting great attention especially when combined with emerging electronic synapse (i.e. memristor). The neuron, transmitting and receiving spiking signals, is a vital component to realize the biological rules of SNNs, such as leaky-integrate-and-fire (LIF), inhibitory period, winner takes all (WTA) and bidirectional transmission. In this work, we propose and implement a novel spiking neuron circuit based on complementary- metal-oxide-semiconductor (CMOS) technology. Experimental results show that the neuron circuit can generate spiking pulses, realize lateral inhibition and change the weight of synapse.

In this paper, we propose two emulator circuits. Firstly, we present a novel memristor emulator based on operational transconductance amplifier (OTA) which is different from classical TiO2 memristor. This memristor emulator has a threshold switching mechanism. Secondly, we create a novel neuron circuit using proposed memristor, which is capable of generating spiking and bursting firing behaviors, with a biologically plausible spike shapes. The behavior of this neuron circuit can be adjusted by changing only one external biasing voltage. This neuron circuit mimics the behavior of cortical neurons, such as regular spiking (RS), intrinsic bursting (IB), chattering (CH) and fast spiking (FS). Proposed emulator circuits are compatible with VLSI systems and they can also be implemented by using discrete circuit components for different applications.

Adaptive firing rate of neuron plays an indispensable role in stabilizing the neural system, which means that the firing rate of neuron could be adjusted adaptively within an inherent range. In this paper, two aspects of implementing the adaptive firing rate are proposed at the circuit level. First, a memristor model is used in the neuron circuit to represent membrane sensitivity. Second, the threshold voltage of neuron circuit can be adjusted adaptively to change the firing rate. Combined these two methods, the adaptive firing rate of neuron circuit is realized effectively, which is in accordance with its biological counterpart. Furthermore, the proposed neuron circuit is applied in the spiking neural network to verify its functionality, where pattern recognition could be realized. All the simulations are carried out on PSPICE.

Current-mode active components provide linearity, wider bandwidth, and low power dissipation. Current conveyors which are a type of current mode active elements find large application area in circuit designs. In this paper, we present a novel neuron circuit based on a negative-type second-generation current conveyor (CCII‐). The circuit consists of only one CCII‐ and five MOS transistors and capable of generating fast-spiking firing behavior. Two transistors of them are used as capacitors in proposed neuron circuit. All simulation results are obtained as expected. The presented only-MOS based neuron circuit is compatible with VLSI systems.

Spiking neural circuits have been designed in which the memristive synapses exhibit spike timing-dependent plasticity (STDP). STDP is a learning mechanism where synaptic weight (the strength of the connection between two neurons) depends on the timing of pre-and post-synaptic action potentials. A known capability of networks with STDP is detection of simultaneously recurring patterns within the population of afferent neurons. This work uses SPICE (simulation program with integrated circuit emphasis) to demonstrate the spatio-temporal pattern recognition (STPR) effect in networks with 25 afferent neurons. The neuron circuits are the leaky integrate-and-fire (I&F) type and implemented using extensively validated ambipolar nano-crystalline silicon (nc-Si) thin-film transistors (TFT) models. Ideal memristor synapses are driven by a nanoparticle memory thin-film transistor (np-TFT) with a short retention time attached to each neuron circuit output. This device serves to temporally modulate the conductance path from post-synaptic neurons, providing rate-based and timing-dependent learning. With this configuration, the use of a crossbar structures would also be possible, providing dense synaptic connections and potentially reduced energy consumption.

In this paper, a ring-oscillator (RO) based sub-1V leaky integrate-and-fire (I&F) neuron circuit is proposed, that can support user programmable refractory period and spike-frequency adaptation. Designed in CMOS 65-nm TSMC process, the neuron can operate from 0.9 V and has the unique feature that the same circuit can be programmed to operate either at biological time-scales or at accelerated time-scales. As ring-oscillators in nanometer CMOS are small compared to capacitors used in existing I&F silicon neuron (SiN), a large number of RO-based neurons can be integrated along with complex digital circuits to realize a single-chip Neuromorphic-SoC.

We propose an integrate-and-fire neuron circuit and synaptic devices with the floating body MOSFETs. The synaptic devices consist of a floating body MOSFET to imitate biological synaptic characteristics. The synaptic learning is performed by hole accumulation. The synaptic device has shortterm and long-term memory in a single silicon device. I&F neuron circuit emulate the biological neuron characteristics such as integration, threshold triggering, output generation, and refractory period, using floating body MOSFET. The neuron circuit sends feedback signal to the synaptic transistor for long-term memory.

Neuromorphic engineering is related to the existing analogies between the physical semiconductor VLSI (Very Large Scale Integration) and biophysics. Neuromorphic systems propose to reproduce the structure and function of biological neural systems for transferring their calculation capacity on silicon. Since the innovative research of Carver Mead, the neuromorphic engineering continues to emerge remarkable implementation of biological system. This work presents a simulation of an elementary neuron cell with a carbon nanotube transistor (CNTFET) based technology. The model of the cell neuron which was simulated is called integrate and fire (IF i.e CNTFET on the design of such architecture in terms of power consumption and technology integration density.

Neuron is the basic entity that transmits and process information through generated action potential or spikes in neuromorphic systems. In real scenario there is no fixed threshold in the cortical neuron but it varies for every neuron. In this work, the neuron with threshold modulation capability is implemented in analog VLSI using CMOS technology. The proposed neuron circuit generated time varying threshold voltage that applies to neuron input. The circuit is capable of generating a variety of different spiking patterns with diversity similar to that of real biological neuron cell. The paper describes how threshold modulation is achieved besides operation of the circuit. Simulation results of different patterns are presented along with threshold modulation to the circuit as well as power analysis for each pattern. The circuit is implemented in 0.18µm technology in Cadence Design Environment. The neuron circuit is efficient to be used in microcircuits as it consumes low power.

Neuromorphic systems that densely integrate CMOS spiking neurons and nano-scale memristor synapses open a new avenue of brain-inspired computing. Existing silicon neurons have molded neural biophysical dynamics but are incompatible with memristor synapses, or used extra training circuitry thus eliminating much of the density advantages gained by using memristors, or were energy inefficient. Here we describe a novel CMOS spiking leaky integrate-and-fire neuron circuit. Building on a reconfigurable architecture with a single opamp, the described neuron accommodates a large number of memristor synapses, and enables online spike timing dependent plasticity (STDP) learning with optimized power consumption. Simulation results of an 180nm CMOS design showed 97% power efficiency metric when realizing STDP learning in 10,000 memristor synapses with a nominal 1M{\Omega} memristance, and only 13{\mu}A current consumption when integrating input spikes. Therefore, the described CMOS neuron contributes a generalized building block for large-scale brain-inspired neuromorphic systems., Comment: This is a preprint of an article accepted for publication in International Joint Conference on Neural Networks (IJCNN) 2015

We propose an asynchronous spiking chaotic neuron circuit for temporal coding networks based on coincidence detection and spatio-temporal chaotic dynamics. In the proposed circuit, we take into account the coincidence detection among input spikes, continuous-time interspike intervals, relative and absolute refractoriness, an analog internal state value, a continuous output function, an output spike generation delay, and synaptic weight. We implement the neuron circuit with a 0.5@mm CMOS semiconductor process by means of analog circuitry. Moreover, we make most of the model parameters externally controllable so that we can control the behavior of the neuron. As a consequence, by properly setting its circuit parameters, the neuron can function as either a coincidence detector or an integrator. We show the measurement results from the prototype chip. In particular, we show coincidence detection of the input spikes in a short time-window. In addition, we illustrate complex responses of the neuron circuit, providing bifurcation diagrams of the internal state value and the interspike intervals of the output spikes. The proposed neuron circuit is useful for exploring a possible spatio-temporal coding paradigm by constructing a neural network based on the coincidence detection and the spatio-temporal chaotic dynamics.

We present a design of a majority neuron circuit with non-volatile synaptic weights. It is based on an analog majority circuit composed of controlled current inverters (CCIs). The proposed circuit is immune to device parameter fluctuations, and its fan-in is estimated about 1000. Synaptic weights are realized on the neuron circuit by adding variable resistors. We consider a design of a non-volatile synaptic weight by using a three-terminal magnetic domain-wall motion (DWM) device. The operation of a fully connected recurrent neural network composed of the proposed circuits has been confirmed by SPICE simulation.

Artificial neural networks have the potential for parallel processing with integrated circuit technology. Over 1 million gates are now available in the latest FPGA (Field Programmable Gate Array). However, the sum-of-product circuit used for evaluating inputs of the neuron model is complex and not effective for hardware implementation by FPGAs. In this paper, an improved calculation algorithm of the perceptron-type neuron model is proposed, based on multidimensional binary search. Since the search does not need the sum-of-product circuit, the designed neuron circuit is small and fast. It is suitable for hardware implementation. © 2001 Scripta Technica, Electr Eng Jpn, 138(2): 24–32, 2002

In order to install a chaotic neural network to solve the traveling salesman problem (TSP) on an integrated circuit, a chaotic neuron circuit is designed by using a current mode circuit. First, the characteristics of the output function of the neuron circuit are determined by numerical simulation so that they have excellent capability to solve the TSP. Next, the network is designed such that the chaotic neural network consisting of the designed neuron circuits can seek the optimum solution efficiently. Further, a circuit is proposed which realizes chaotic annealing in order to improve the convergence of the chaotic neural network. The ability of the proposed network using the annealing circuit to derive an optimum solution of the TSP is studied. From the simulation results, it is confirmed that the proposed chaotic neuron circuit is suitable for integration of the chaotic neural network to solve the TSP. © 1999 Scripta Technica, Electron Comm Jpn Pt 3, 82(9): 52–62, 1999

A spiking neuron circuit based on a carbon nanotube (CNT) transistor is presented in this paper. The spiking neuron circuit has a crossbar architecture in which the transistor gates are connected to its row electrodes and the transistor sources are connected to its column electrodes. An electrochemical cell is incorporated in the gate of the transistor by sandwiching a hydrogen-doped poly(ethylene glycol)methyl ether (PEG) electrolyte between the CNT channel and the top gate electrode. An input spike applied to the gate triggers a dynamic drift of the hydrogen ions in the PEG electrolyte, resulting in a post-synaptic current (PSC) through the CNT channel. Spikes input into the rows trigger PSCs through multiple CNT transistors, and PSCs cumulate in the columns and integrate into a 'soma' circuit to trigger output spikes based on an integrate-and-fire mechanism. The spiking neuron circuit can potentially emulate biological neuron networks and their intelligent functions.

Fabrications and characterizations of high electron-mobility transistors (HEMTs) with a ferroelectric gate (F-HEMTs) are presented. The F-HEMT is a memory device whose threshold voltage can be changed even after it is fabricated, by using remanent polarization of the ferroelectric gate. Furthermore, the F-HEMT is promising of neural network applications, because it can act as a high-speed analog memory which stores synaptic weights in a neuron circuit. From I/sub D/-V/sub G/ characteristic measurements of F-HEMTs, it is demonstrated that the threshold voltage is shifted by 0.3 V by remanent polarization. The result indicates that F-HEMTs are sufficiently applicable for the high-speed analog memory.

A novel CMOS synapses circuit for using in neuron circuit is presented. The proposed new type CMOS synapses circuit with the accurate weights is composed with the CMOS inverters which have resistors inserted inside. A design of the neural-based A/D converter using the proposed CMOS synapses circuit is also presented to show a practical application.

A basic optoelectronic circuit of an artificial synaptic connection was fabricated in which analogue weights were varied electrically. Circuit simplicity and low current level operation, necessary for a large scale OEIC, were realised.

A basic optoelectronic circuit of an artificial neuron was realised in which synaptic weights were varied electrically. A primitive content addressable memory was constructed using an optical interconnection. The experimental results showed the feasibility of large-scale networks and a one-chip OEIC.