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This brief presents a linearization technique for open-loop amplifiers. It utilizes the exponential ${V}{-}{I}$ transfer of MOS transistors in weak-inversion together with a weak form of resistive degeneration. By using a specific relationship between the input transconductance and the source degeneration resistance, the amplifier is shown to have a significant reduction ( $\sim 50\times $ ) in its third-order distortion component. Based on this linearization principle, two amplifier topologies are proposed by implementing the degeneration in (a) pseudo-differential and (b) common-mode configuration. The pseudo-differential degeneration scheme allows the amplifier to achieve more than 80dB linearity for 150mV $_{\text {pp-diff}}$ input swing at the expense of 35% lower power-efficiency. The common-mode degeneration eliminates this power penalty but exhibits ~10dB worse linearity. To ensure an optimal linearity over process variation, a foreground calibration scheme is used to detect the nonlinearity. The nonlinearity correction is done by adjusting the bias current of the amplifier. The proof-of-concept amplifiers are constructed on a stripboard to demonstrate the effectiveness of the proposed linearization technique. With an input signal of 50mV $_{\rm pp{-}diff}$ , the two topologies achieve −105dB and −95dB HD3, respectively, improving the linearity of the state-of-the-art open-loop amplifiers by at least 30dB.

This paper presents a closed-loop class-AB residue amplifier for pipelined analog-to-digital converters (ADCs). It consists of a push–pull structure with a “split-capacitor” biasing circuit that enhances its power efficiency. The amplifier is inherently quite linear, and so incomplete settling can be used to save power while still maintaining sufficient linearity. This also allows the amplifier’s gain to be corrected by adjusting its bias current. When combined with digital gain-error detection, in this case the split-ADC technique, the result is a power-efficient gain calibration scheme. In a prototype pipelined ADC, this scheme converges in only 12 000 clock cycles. With a near-Nyquist input, the ADC achieves 66-dB SNDR and 77.3-dB SFDR at 53 MS/s. Implemented in 40-nm CMOS, it dissipates 9 mW, of which 0.83 mW is consumed in the residue amplifiers. This represents a 1.8 $\times $ improvement in power efficiency compared to state-of-the-art class-AB residue amplifiers.

This paper presents a new dynamic residue amplifier topology for pipelined analog-to-digital converters. With an input signal of 100 mVpp,diff and 4 $\times$ gain, it achieves −100-dB total harmonic distortion, the lowest ever reported for a dynamic amplifier. Compared to the state of the art, it exhibits 25 dB better linearity with twice the output swing and similar noise performance. The key to this performance is a new linearization technique based on capacitive degeneration, which exploits the exponential voltage-to-current relationship of MOSFET in weak inversion. The prototype amplifier is fabricated in a 28-nm CMOS process and dissipates only 87 $\mu \text{W}$ at a clock speed of 43 MS/s, thereby improving the energy per cycle by 26 $\times$ compared with that of state-of-the-art high-linearity amplifiers.

This paper presents a new dynamic residue amplifier for pipelined ADCs. With an input of 100mV pp, diff and 4x gain, it achieves −100dB THD, the lowest ever reported in dynamic amplifiers. Compared to the state-of-the-art, it exhibits >25dB better linearity with >2x larger output swing and similar noise performance. The key to this is a new linearization technique based on capacitive-degeneration. Fabricated in a 28nm CMOS, the prototype amplifier dissipates 87μW at a clock speed of 43MS/s and maintains −100dB THD up to 150MS/s.