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Optical lithography is a critical technique to fabricate nano-scale semiconductor devices by replicating the layouts of integrated circuits from the lithography mask onto the silicon wafer. As the critical dimension of integrated circuits continuously shrinks, source and mask optimization (SMO) methods are extensively used to improve the resolution and image fidelity of lithography patterning. However, the theoretical lower bound of the lithography pattern error in the SMO framework is not yet understood. This paper introduces an informational lithography approach to unveil the information transmission mechanism in lithography systems under freeform illumination configurations. The lithography system is regarded as an information channel, where the mask pattern and the print image on the wafer are modeled as the statistical input and output signals, respectively. Subsequently, we derive the optimal information transfer (OIT) of the lithography system, which represents the best information transfer strategy rendering the least image distortion. Based on the OIT, we derive a lower bound for the lithography pattern error, and the corresponding optimal source pattern and optimal mask probability distribution. Finally, we propose a new SMO algorithm based on the information theoretical framework to effectively improve the lithography image fidelity compared to the existing gradient-based SMO algorithm.

Process windows based on Mean CD (“Critical Dimension”) have been an analysis workhorse for estimating and comparing the robustness of semiconductor microlithography processes for more than 30 years. While tolerances for variation of CD are decreasing in step with the target CD, the acceptable number of printed defects has remained flat (Hint: Zero) even as the number of features increases quadratically. This disconnect between two key process estimators, CD variability and defect rate, must be addressed. At nodes that require EUV lithography, estimating the printed defects based solely on a Mean CD process window is no longer predictive. The variability / distribution of the printed CDs must be engineered so that there are no failures amongst the billions of instances, rendering the Mean CD, often measured on just hundreds or thousands of instances, a poor predictor for outliers. A “defect-aware” process window, where the count of printed defects is considered in combination with more advanced statistical analysis of measured CD distributions can provide the needed predictability to determine whether a process is capable of sufficient robustness. Determining process robustness where stochastics and defects are taken into account can be simplified by determining the CD process margin. In this work we study dense via/contact hole arrays exposed with 0.33NA single exposure EUV lithography after both the lithography and etch steps. We describe a methodology for expanding the analysis of process windows to include more than the mean and $3{{\sigma }}$ of the data. We consider the skew and kurtosis of the distribution of measured CD results per focus-exposure condition and compare/correlate the measured CD process window results to the CD process margin.

The development of photoresists is crucial for the progress in lithographic technologies and integrated circuit altogether. For instance, the development of novel EUV resists is a critical enabler of future technology nodes, particularly towards the deployment of high-NA EUV lithography into high-volume manufacturing. Within the scope of a joint resist screening program between PSI and ASML, the development of EUV resists is investigated using EUV interference lithography. In this work, we provide a review of the recent progress in EUV resists by considering several resist platforms provided by different vendors. Lines/spaces patterning is extensively investigated as a function of film processing parameters. The challenge in developing resists is admittedly governed by a resolution-roughness-sensitivity (RLS) performance tradeoff, therefore performance results are presented with critical dimension (CD), dose-to-size (DtS), line-width-roughness (LWR) as well as the z-factor metric associated to the RLS tradeoff. We consider LS patterning between 16 and 13 nm half-pitch to identify materials matching current high-volume manufacturing specifications. We then investigate high-resolution resists for patterning down to 8 nm half-pitch, therefore potential candidates for high-NA EUVL. Further process optimization perspectives are finally discussed towards enabling future technology nodes.

Although extreme ultraviolet lithography (EUVL) has potential to enable 5-nm half-pitch resolution in semiconductor manufacturing, it faces a number of persistent challenges. Line-edge roughness (LER) is one of critical issues that significantly affect critical dimension (CD) and device performance because LER does not scale along with feature size. For LER creation and impacts, better understanding of EUVL process mechanism and LER impacts on fin-field-effect-transistors (FinFETs) performance is important for the development of new resist materials and transistor structure. In this paper, for causes of LER, a modeling of EUVL processes with 5-nm pattern performance was introduced using Monte Carlo method by describing the stochastic fluctuation of exposure due to photon-shot noise and resist blur. LER impacts on FinFET performance were investigated using a compact device method. Electric potential and drain current with fin-width roughness (FWR) based on LER and line-width roughness (LWR) were fluctuated regularly and quantized as performance degradation of FinFETs.

Contact holes are traditionally designed as squares or rectangles on the mask. The lithography tool acts as a low-pass filter of the spatial frequencies and is not able to image the corners. Therefore, the contact holes will appear as circles or ellipses on the wafer, even if they are square on the mask. Nevertheless, the presence of the designed corners imposes a limit to the center-to-center distance that can be obtained in certain contact hole configurations. Indeed, as the distance between contact holes is decreased, these corners are the first features to create violations in the Mask Rule Check (MRC). Rounded contact hole corners therefore give more design freedom. The recent introduction of multi-beam mask writing makes writing curvilinear shapes on actual masks practical, including contact holes with corner rounding. While the benefits to design freedom are obvious, there is a need for studies identifying the impact of this additional corner rounding parameter on the imaging properties. In this work, we investigate the imaging impact of corner rounding on pitch-40nm contact holes, exposed with an EUV scanner (ASML NXE:3400B at imec). The study aims to experimentally establish the difference in imaging quality introduced by the corner rounding. More specifically, we first characterize the pattern fidelity on the mask by means of mask CD-SEM images. Next, we assess the impact of corner rounding on imaging properties such as Local Critical Dimension Uniformity (LCDU), Mask Error Enhancement Factor (MEEF) and Exposure Latitude.

In this paper, we will report the modeling of behaviors of low-energy secondary electrons (LSEs) in a charge effect correction system (CEC), which compensates image placement errors predicted by writing layout data, on mask blanks with and without a charge dissipation layer (CDL). For the demand of low line edge roughness and high critical dimension uniformity, the more dose-sensitivity of resist is lowered, the more a contribution of LSE is made in charge effect, because the number of primary electrons generating LSEs also increases. In such a situation of advanced lithography, we have tackled challenges of CEC system in terms of blanks with and without CDL. On blanks without CDL, CEC needs to predict the complicated charge distribution including that of LSE which is affected by electromagnetic field of optical system and already-existing resist surface charge. On blanks with CDL, CEC needs to predict LSE charge diffusing on the resist surface. In order to address these challenges, NuFlare Technology (NFT) has developed models of CEC on blanks with and without CDL. In order to verify these models, we evaluated the surface charge effect in the writing on blanks with resist of 100 μC/cm2 dose-sensitivity on electron beam mask writer EBM-9000/9500. Furthermore, as another solution besides CEC and CDL, NFT has developed a charge effect reduction (CER) system which prevents LSEs from re-entering into the resist surface. We have verified CER by comparing the experimental results between EBM9500 and EBM9500PLUS, which is the NFT’s latest variable-shaped beam with CER system.

ArF lithography is still applied to the majority of critical layers, even with increasing of extreme ultraviolet lithography in leading-edge production. As wafer design shrinks, conventional 6% phase shift mask (PSM) becomes hard to meet the ArF lithography requirements especially for array dot on mask (hole on wafer). Therefore, transmission dependency was evaluated by mask 3D simulation, and it was found that 30% transmission has the best lithographic performances for array dot. Based on these results, mask blank and mask making process for new 30% PSM were developed. Wafer printability test using negative tone development demonstrated that new 30% PSM has better process window and mask error enhancement factor (MEEF) than conventional 6% PSM for array dot (hole on wafer). To investigate further application of new 30% PSM, lithography performances of various patterns were evaluated by mask 3D simulation and aerial image measurement system (AIMSTM). The results indicated that new 30% PSM has larger lithography margin than 6% PSM for iso dot, iso line and logic pattern. Additionally, wafer printability test demonstrated that new 30% PSM has better process window than 6% PSM for iso dot. Defect control is also an important factor in high volume manufacturing. Therefore, it is necessary to evaluate the repairability and printability of the defects on new 30% PSM. We repaired various types of defects by electron-beam repair tool and confirmed the repairability by AIMS. And the defect printability of new 30% PSM and 6% PSM to critical dimension (CD) on wafer was evaluated by program defect mask that has pin dot, extrusion and intrusion defects.

Mask process correction (MPC) played a key part improving yield in 14 nm technology node and below using deep ultraviolet lithography (DUVL). Extreme ultraviolet lithography (EUVL) is entering an industry production phase for 7 nm logic and is under development for next node logic and memory applications. A key benefit of EUVL for logic interconnect lithography comes from the ability to pattern layers at aggressive pitch using a single exposure. Mask critical dimension targeting was found to be a critical factor for yielding wafer process, MPC will be necessary to correct for mask process errors. This paper will focus on building MPC models for EUV mask processes exposed on a variable shape beam lithography tool.

Nanoimprint lithography (NIL) is a promising technology on next generation lithography for the fabrication of semiconductor devices. NIL is a one-to-one lithographic technology with a contact transfer methodology using templates. Therefore, critical dimension (CD) error and defect performance of templates has direct impact on wafer performance. The previous paper reported that the self-aligned double patterning (SADP) process on master template had better performance on resolution and defect performance [2]. In proceeding with development of SADP template process technology, we found that CD errors occurred in the area with a pattern density change. CD control over any pattern density is one of the critical issues. In this report, we have investigated the impact of the proximity effect correction (PEC) and fogging effect correction (FEC) parameters for electron beam writing on gap space and core space. It was found that the optimal PEC parameter for resist CD is not the best for the core space and the gap space. The resist CD is uniform, but there is a difference in resist shape on the local pattern density variation. It was also found that the core space had dependency on global pattern density even if the optimal FEC parameter for resist CD was applied. FEC can correct resist CD, but it cannot adjust resist shape. By using the optimal PEC and FEC parameters for SADP process, the gap space range of 0.6 nm and the core space range of 0.5 nm were successfully obtained.

Extreme ultraviolet lithography (EUVL) has been adopted into high volume production for advanced logic device manufacturing. Due to the continuous size scaling requirement for interconnect fabrication, EUVL with self-aligned double patterning (SADP) formation has attracted substantial research attention. The current challenge in EUV SADP is the pattern transfer process from lithography to mandrel formation. In this step, the target critical dimension (CD) of the feature needs to shrink by half from the lithography CD during the etch process. The increasing aspect ratio during this etch potentially deteriorates the pattern validity and the line edge roughness (LER). In addition to these challenges, EUVL has a fundamental bottleneck due to stochastic effects, which can lead to device degradation by defect formation and edge placement error (EPE). LER of the line and space pattern is one of the main contributors to EPE. Effective methods of LER reduction in both process and integration are needed in order to reduce pattern variation and boost device performance. In our study, we examine a technique to reduce LER on the EUV SADP line pattern. This technique involves the surface modification on the spin-on carbon (SOC) layer in the patterning stack and tone inversion process. We had found a trend between surface hydrophobicity of the SOC and the EUV SADP LER performance. The condition that increased the hydrophobicity of the SOC resulted in a lower LER performance after tone inversion. The tested conditions include direct current superposition (DCS) function with H2 plasma, fluorocarbon plasma, and the combination of DCS with H2 plasma and trimethylsilane dimethylamine deposition. On 20-nm pitch EUV SADP, this technique shows 26% of LER improvement from lithography to SADP formation. PSD analysis recorded about 6% and 30% of the LER improvement at the correlation length of >200 nm and 200 to 30 nm, respectively. A demonstration of this technique for a further scaling to 15-nm pitch also shows an LER reduction of 30% from lithography to SADP formation.

Extreme ultraviolet lithography (EUVL) has been adopted into high volume production for advanced logic device manufacturing. Due to the continuous size scaling requirement for interconnect fabrication, EUVL with self-aligned double patterning (SADP) formation has attracted substantial research attention [1]–[6]. Double patterning techniques in EUVL achieve pitch halving in the final feature by using the spacer defined approach and self-aligned block (SAB) mitigates the block placement error by leveraging etch selectivities and material filling capability. The current challenge in EUV SADP is the pattern transfer process from lithography to mandrel formation. In this step, the target critical dimension (CD) of the feature needs to shrink by half from the lithography CD during the etch process. The increasing aspect ratio during this etch potentially deteriorates the pattern validity and the line edge roughness (LER) [5]. In addition to these challenges, EUVL has a fundamental bottleneck due to stochastic effects which can lead to device degradation by defect formation and edge-placement-error (EPE) [7]–[10]. LER of the line and space pattern is one of the main contributors to EPE. Effective methods of LER reduction in both process and integration are needed in order to reduce pattern variation and boost device performance. In our research, we examine three approaches to reduce LER on the EUV SADP line pattern. This includes photoresist surface smoothing techniques, patterning layer material study, and tone inversion integration. The photoresist surface smoothing techniques involve a specific plasma process on the EUV chemical amplified resist (CAR) to achieve > 15% of improvement on LER from lithography to post etch performance. The patterning layer material study reveals an optimum patterning stack to minimize etch-induced line wiggling and etch selectivity requirements for LER performance. Finally, a first demonstration of EUV SADP tone inversion process integration is presented as a method to provide additional benefits to LER reduction. A detailed analysis of line performance from each processing step will be examined.

Spin-transfer torque magnetic random-access memory (STT-MRAM) is considered as the most promising candidate to replace the complementary metal-oxide-semiconductor (CMOS) based memories that are dominating the market in the last few decades. What makes STT-MRAM superior to other memories is the high read and write speeds, non-volatility, good cycling endurance and near-zero leakage. Moreover, with the perpendicular device topology and the single transistor cell configuration, it becomes a very promising candidate for further device scaling which is essential to increase the memory densities. This paper focuses on the experiments performed using different lithography approaches in order to explore the smallest printable pitches for orthogonal array magnetic tunnel junction (MTJ) pillars, which are the main components of the STT-MRAM. Considering the high impact of the MTJ patterning process on the robustness of the memory device, several post-litho performance parameters such as wafer critical dimension uniformity (WCDU), local critical dimension uniformity (LCDU) and pillar circularity have also been measured and compared.

In semiconductor fabs, top-down critical dimension scanning electron microscopes (CD-SEMs) are key enablers for metrology and process control, and in order to continue to address the increasing metrology requirements of the semiconductor industry, additional applications that exploit the potential of CD-SEM equipment have being developed. More recently, the uses of contour extraction have expanded to encompass other applications that serve newer technologies, such as ILT (Inverse Lithography Technology), photonics, and DSA (Directed Self Assembly), where the characteristics of the 2D curvilinear patterns are such that standard measurement solutions are no longer an option. The applications for these newer technologies have driven the need for highly accurate contour metrology algorithms. In turn, the need for standardization of what is meant by “accurate” contour metrology has emerged. This paper explores the concept of accuracy as it relates to contour metrology and applies the fundamental methodologies of TMU analysis to the problem of finding the best methods of determining contour metrology accuracy. During the development of this methodology, it was discovered that the application of TMU analysis to contour metrology reveals unexpected conceptual challenges that force a deeper understanding of accuracy and how it pertains to contour metrology. The paper resolves these challenges and proposes a standardization for contour metrology accuracy assessment. Results from analysis of the extracted contours validates the usefulness of the proposed accuracy methodology and establishes the quality of the accuracy of the extracted contours.

The NanoImprint Lithography (NIL) technology by using a soft stamp is today ready for high volume manufacturing (HVM) with the global solution proposed by EVG1. This UV-based imprint, using a transparent stamp is now a standard technology and the most common option for the full wafer imprint, meaning the size of the stamp correspond to the size of the wafer to print. Previous work has shown promising results with strong repeatability and uniformity in terms of critical dimension (CD)2. In 2017, larges features, bigger than 500 nm period, and shallow aspect ratio were qualified3. Latter in 20194, lithography and etching through a Si/SiO2 stack were demonstrated for 25 wafers imprinted in a single run: - Depending on several diameters contact (from 100 to 50 nm) and densities (from 1:3 to 1:15). - For line and space arrays with a density of 1:4 and variable spaces widths (from 100 to 50 nm). In this paper we demonstrate that the limit of the patterns dimension can be pushed to sub-50 nm features thanks to EVG SmartNIL technology, the optimized EVGNIL-UV/AS2 soft stamp material with matching resist as well as the improvement of pattern transfer by dry etching. Based on CDSEM metrology, and SEM cross-sections, high fidelity and reproducibility were demonstrated, with 25 replications in a single run using the same soft stamp. Transfer compatibility of the imprint material was validated until 45 nm line, with 1:4 density. Furthermore, the process window of this NIL technology and its compatibility with applications as photonics and 3D patterning are discussed. The specific developments achieved around stripping of the substrates and the perspectives for low defectivity process are pointed out.

In our manufacturing process for the hard disk drive (HDD) recording heads, the home-brew pixelated-based inverse lithography is being employed in some critical lithography layers, providing significant improvement on pattern fidelity and process stability. Generally, the process-aware (defocus and dose) inverse lithography is realized through the stochastic gradient decent (SGD) method. In this paper, a widely used search algorithm Adam is introduced for our inverse lithography framework. The new algorithm utilizes the first and second moments of gradients to adapt the learning rate for each individual pixel during the stochastic searching process. Unlike SGD, such derived learning rate is invariant to the magnitude of gradient. In our experiment, we demonstrated reduced edge placement error (EPE), enlarged process window and tighter critical dimension (CD) distribution with Adam on our test cases of isolated features. We believe that the inverse lithography with Adam algorithm is also applicable to dense features with the similar benefits.

In the field of semiconductor manufacturing, there is still a continuous search for techniques to improve the Critical Dimension Uniformity (CDU) across the wafer. CDU improvement and general defectiveness reduction increase the industrial yield and guarantee high reliability standards. In the KrF Dual-Damascene module integration, at a lithographic level, deep trench planarization is mandatory to minimize interference patterns of the photoresist known as the swing curve effect. Swing curve models explain why small changes in the film thickness of the photosensitive material can create wide critical dimensions changes. Different approaches have been developed to improve the CDU, like the etch-back approach and partial via filling. Within the plethora of materials studied to improve the performances, the Marangoni-effect based underlayers are now showing their potential. In the past, an extensive testing of a double-layer solution comprising one Marangoni-effect-based material and one standard underlayer has been carried out with success. Despite this, double-layer spinning brings drawbacks at manufacturing level, increasing the cost and limiting the tools’ throughput. A new solution, resulting from the chemical tuning of the material exploiting the Marangoni effect has brought to the synthesis of a new single-layer planarization material, with properties similar to the previously tested double-layer approach. This advanced material opens the pathway to an alternative and cost-effective way to solve the issues typical of this module integration.

Current applications of silicon photonic devices are strongly limited by waveguide performance. Rough sidewalls scatter electromagnetic radiation and lead to significant losses. Prototyping of state-of-the-art silicon photonic devices on full wafer scale requires maskless manufacturing. Therefore, variable shaped electron-beam lithography in chemically amplified photoresists and anisotropic etching processes are used. As a result, size and roughness errors in the photoresist structures are directly transferred to the silicon-waveguides. In this study a high-resolution chemically amplified negative photoresist for electron-beam writing was run in and optimized for photonic device manufacturing successfully. The investigation of the photoresist contrast and critical dimensions enabled the production of smooth and critical dimension stable lines in photoresist, which exhibit vertical sidewalls as well as a resolution limit far below 100 nm.

Scalable fabrication of Si nanowires with a critical dimension of about 100 nm is essential to a variety of applications. Current techniques used to reach these dimensions often involve e-beam lithography or deep-UV (DUV) lithography combined with resolution enhancement techniques. In this study, we report the fabrication of λ = 248 nm) by adjusting the exposure dose. Irregular resist profiles generated by in-plane interference under masking patterns of width 800 nm were optimized to split the resulting features into twin Si nanowires. However, masking patterns of micrometre size or more on the same photomask does not generate split features. The resulting resist profiles are verified by optical lithography computer simulation based on Huygens−Fresnel diffraction theory. Photolithography simulation results validate that the key factors in the fabrication of subwavelength nanostructures are the air gap value and the photoresist thickness. This enables the parallel top-down fabrication of Si nanowires and nanoribbons in a single DUV lithography step as a rapid and inexpensive alternative to conventional e-beam techniques.

This work reports a novel, simple, and resist-free chemo-epitaxy process permitting the directed self-assembly (DSA) of lamella polystyrene-block-polymethylmethacrylate (PS-b-PMMA) block copolymers (BCPs) on a 300 mm wafer. 193i lithography is used to manufacture topographical guiding silicon oxide line/space patterns. The critical dimension (CD) of the silicon oxide line obtained can be easily trimmed by means of wet or dry etching: it allows a good control of the CD that permits finely tuning the guideline and the background dimensions. The chemical pattern that permits the DSA of the BCP is formed by a polystyrene (PS) guide and brush layers obtained with the grafting of the neutral layer polystyrene-random-polymethylmethacrylate (PS-r-PMMA). Moreover, data regarding the line edge roughness (LER) and line width roughness (LWR) are discussed with reference to the literature and to the stringent requirements of semiconductor technology.

Shot-to-shot, or pixel-to-pixel, dose variation during electron-beam lithography is a significant practical and fundamental problem. Dose variations associated with charging, electron source instability, optical system drift, and ultimately shot noise in the e-beam itself conspire to critical dimension variability, line width/edge roughness, and limited throughput. It would be an important improvement to e-beam based patterning technology if real-time feedback control of electron-dose were provided so that pattern quality and throughput would be improved beyond the shot noise limit. In this paper, we demonstrate control of e-beam dose based on the measurement of electron arrival at the sample where patterns are written, rather than from the source or another point in the electron optical column. Our results serve as the first steps towards real-time dose control and eventually overcoming the shot noise.

With development of advanced lithography processes, simultaneous reduction of line width and edge roughness along with the shrinkage of critical dimension of main feature is a continuous challenge. Recent years, unbiased roughness characterization was introduced in pattern roughness analysis by applying power spectral density method. Through power spectral density analysis, the data of all measurement points from scanning electron microscope are processed by Fourier transform, and the roughness behaviors of inspected pattern are converted from spatial domain to frequency domain. Autocorrelation analysis is an effective means to identify the periodic behavior of line width or edge roughness. In our research, roughness of dense lines under different lithography conditions, including reflectivity of bottom anti-reflection coating materials, photoresist, illumination and post exposure bake temperature, was characterized using power spectral density, autocorrelation methods as well as with standard deviation.

In low $\mathrm{k}_{1}$ regime, the lithography resolution is close to the optical diffraction limit. Ignoring the impact of lenses aberration for such precise lithography processes is questionable. The aberration of lithography lenses in circular pupil is typically represented by Zernike polynomials. In theory, even Zernike aberrations mainly induce pattern critical dimension (CD) variation and odd Zernike aberrations mainly induce pattern position variation. We study the CD and position simulations in various lithography configurations, such as numerical aperture (NA), illumination sigma, defocus, wafer stack, and pattern pitch. Based on the above data, this paper comprehensively discusses the impact of each Zernike aberration on pattern CD and position. The conclusion is useful to accurately predict pattern CD and position variations and to further implement aberration-aware optical proximity correction (OPC) for actual lithography lenses.

Advanced DRAM technology relies heavily on 193nm immersion lithography. Negative tone develop (NTD) layers are becoming increasingly important particularly in nodes below 20nm. NTD is particularly useful for patterning holes on the wafer. Cut layers for multi-patterning (MP) applications and bit line contact structures are common uses of NTD in DRAM. Patterning these structures pose lithographic challenges around process window (PW), layer-to-layer overlay, and critical dimension (CD) control. The mask plays a critical role in optimizing all of these attributes. In this paper, we explore multiple mask enhancements to optimize wafer performance for NTD contacts. These include mask process and mask blank conditions, as well as a data enhancement technique generally known as mask process correction (MPC). Specifically, we implement a litho-aware MPC Application (LAMA) to optimize mask pattern fidelity. Finally, we harmonize these mask enhancements with optimizations to wafer exposure conditions and optical proximity correction (OPC) to demonstrate capability improvement in NTD contact lithography.

Investigations on the application of aqueous ethyltrimethylammonium hydroxide (ETMAH) as an alternative developer solution for extreme ultraviolet lithography (EUVL) were carried out. Utilizing a widely-used chemically amplified resist, it was found that the ETMAH developer solution has no negative impact on lithographic performance; resolution, line width / line edge roughness, and sensitivity (compared to the de facto standard aqueous tetramethylammonium hydroxide or TMAH). Stochastic defectivity analysis was performed by considering the effect of line-break (in the overdose region) and line-bridge defects (in the underdose region), on exposure latitude (ELX) and critical dimension or CD margin (CDMX). Results show that the ETMAH improves ELX and CDMX by around 10% and 5%, respectively at a lower developer solution concentration of 0.20N. These results confirmed the capability of the ETMAH in reducing resist-based stochastic defects, demonstrating its potential as an alternative developer solution for EUVL.

Moving from monolithic scaling to the second (2D) and to the third dimension (3D) is becoming increasingly important within industry. In the last years heterogeneous and chiplet integration, utilizing advanced packaging technologies, has increased in complexity as well as in variability. Higher performance, wider bandwidth and lower power consumption and space requirements drive the approach toward 3D integration, whereas the need of finer RDL line/spacing as well as smaller μ-bumps and μ-pillars critical dimension tighten integration design rules at the package and substrate level. Individual chiplet's I/O bumps and interconnects pitch scaling nowadays moves towards 2/2μm L/S. Although the flexible re-integration of larger dies from smaller chiplets, from various technology nodes to partitioned dies has shown numerous advantages over monolithic SoC technologies with larger freedom of design, this approach shifts the complexity into the integration and with it into the lithographic patterning processes. In this work a profound evaluation of common advanced packaging high resolution, thin and thick resists for RDL & μ-bump/μ-pillar manufacturing is presented, utilizing maskless exposure to demonstrate its patterning performance. Resolution tests, focal position & exposure matrices, including resist sidewall profiles are discussed in view of the 2/2μm L/S requirements for heterogeneous integration. Furthermore, the high-speed digital processing meets the needs for design flexibility and scalability for a wide range of packaging technologies by enabling both, die- and wafer-level designs, fast tape-out changes together with sub-μm adaptability.

In 2019 we have seen the first 7 nm logic devices, manufactured on ASML NXE:3400 scanners, hitting the market. In this paper we will give an update on the performance improvements to further optimize these systems for High Volume Manufacturing (HVM), related to the lithographic performance, productivity and uptime. We will also demonstrate that for the 5 nm logic node and 10nm-class DRAM, excellent overlay, focus, and critical dimension (CD) control have been realized. In combination with intrinsic tool stability and holistic control schemes, including (resist and tool) performance improvements addressing stochastics issues, this provides the required performance for HVM for these nodes. Finally we will discuss the ASML roadmap for meeting the requirements for the 3 nm node and beyond.

Local critical dimension uniformity (LCDU) for contact holes may be correlated with stochastic defects (missing or merged holes), but metrology noise will bias the LCDU measured by a CD-SEM. In this work, large contact hole data sets will be collected with varying SEM measurement recipes, such as different numbers of frames of averaging. Additionally, multiple measurements of the same after-etch features will be used to quantify the impact of metrology noise on the biasing of measured LCDU. Finally, a recommendation will be made as to an approach that minimizes, or eliminates, bias in LCDU measurements.

In twenty years, consequent technical developments have been achieved to make the soft stamp nano imprint lithography (NIL technology mature for high volume production [1]. Today the up to date technology and materials from EVG have shown high repeatability and uniformity in term of critical dimension (CD) and advanced rules-based have been proposed [2],[3]. Based on this progress, this paper will focus on line width roughness (LWR) and line edge roughness (LER) extraction as a new metric to monitor quality of imprint. Evolution of these metrics are studied to provide information on stability of the imprint process.

In this paper, we demonstrate the use of Aerial Imaging Metrology System (AIMS™) during mask fabrication to deliver duplicate photomasks with matching iso-dense bias (IDB) to a reference photomask. The photomask IDB trend based on AIMS™ feedback showed a direct correlation to on-wafer IDB performance. We also show that the AIMS™ threshold energy is correlated to the photomask critical dimension (CD) mean to target (MTT), and correlates to the on-wafer exposure dose for both line/space and via mask levels in the 14nm technology node. This technique will enable improved photomask matching taking into account 2D and 3D mask effects comparable to wafer processing on lithography exposure tools. With AIMS™ metrology, corrections can then be applied to photomask rebuilds prior to shipment to Wafer Manufacturing Sites.

The investigation aims at the metal trench critical dimension (CD) and overlay variation monitoring methodology with voltage-contrast (VC) inspection. The VC inspection with negative charging mode was performed to detect metal trench CD and overlay variation issue, at NDC film deposition layer post second metal layer chemical and mechanical polish. Dark VC (DVC) defects were found at extreme wafer edge, which would cause end of line (EOL) yield loss by data retention soft bin failure. DVC defects were identified by inline SEM review results with high voltage and PFA analysis results. It was demonstrated that the defects were induced by metal trench CD and overlay variation. Furthermore, the defects impacted factors, including uniformity of thin film deposition and chemical and mechanical polish (CMP), the etching rate performance of all in one etch process, and even the e-chuck accumulated contamination of lithography, were also investigated. By increasing the relative process tools' offline monitor frequency and optimizing the prevent maintenance method of lithography tool, defects were fixed and trend low. The study here extended the usage of VC inspection to detect CD and overlay minor variation.

Lithography patterning is controlled by aerial images and photoresist behaviors. The projected aerial images could be changed by the reflectivity of material and topography. The photoresist process can be affected by baking, development, and local thickness changes. In this paper, we report a study of the optical contribution and the photoresist local/global loading effect from topography, showing a substantial influence on CD (critical dimension) control. Therefore the consideration of photoresist thickness and the refection from underlayers is a must when patterns locate on a complicated topographical environment.

The shrinkage of critical dimension requires more delicate lithography leveling; otherwise, it will easily leads to various pattern failures. Worse wafer back-surface flatness caused by repetitive BEOL backside clean leads to worse lithography leveling and defocuses follow. BEOL lithography leveling performance of a 28 nm node wafer is significantly improved by retaining its back-surface nitride during a novel SMT nitride remove process. The thin back-surface nitride layer could resist the corrosion of backside clean chemicals and maintain wafer back-surface flatness in a more preferable level. In this study a conventional one-step batch SMT nitride remove wet process is replaced by two continuous steps. The first one is a single wafer front-side wet process, and the second one is a conventional batch one. The via-5 leveling data demonstrate a 60% to 80% improvement of leveling range from novel two-step SMT nitride remove wafers. These wafers are defocus free, while the baseline wafers still suffer various kinds of defocus defects. Average CP yield improvement is about 0.5%.

Scanning electron microscope (SEM) measurement is the dominant method to obtain critical dimension (CD) in lithography. In SEM measurement, electron beam exposed on photo resist (PR) will affect PR physical-chemically and cause PR shrinkage inevitably. This phenomenon is well-known in lithography and also studied by many researchers. In this paper, we reviewed previous research results and investigated the PR shrinkage effects on CD measurement of 193nm immersion photo resist in 14nm node. With patterns sizing down, it is important to choose an appropriate voltage, current and frame to avoid large amount shrinkage in the measurement. A 30nm size CD shrinks more than 10% until getting saturation. Different patterns and CD sizes possess different through pitch shrinkage performance, which means PR shrinkage will also impact OPC model setup.

The patterning of silk allows for manufacturing various structures with advanced functionalities for optical and tissue engineering and drug delivery applications. Here, we propose a high-resolution nanoscale patterning method based on field-emission scanning probe lithography (FE-SPL) that crosslinks the biomaterial silk on conductive indium tin oxide (ITO) promoting the use of a biodegradable material as resist and water as a developer. During the lithographic process, Fowler-Nordheim electron emission from a sharp tip was used to manipulate the structure of silk fibroin from random coil to beta sheet and the emission formed nanoscale latent patterns with a critical dimension (CD) of ∼50 nm. To demonstrate the versatility of the method, we patterned standard and complex shapes. This method is particularly attractive due to its ease of operation without relying on a vacuum or a special gaseous environment and without any need for complex electronics or optics. Therefore, this study paves a practical and cost-effective way toward patterning biopolymers at ultra-high level resolution.

Currently, the IC industry has been steadily advancing towards 7 nm and 5 nm nodes with further reductions projected in the near future to progressively create large number of inputs and outputs (IOs) at finer pitch. Today the high-density interconnect (HDI) organic redistribution layer (RDL) can only achieve an IO density of about 40 IOs per mm per layer with line and space of 6 μm and microvia diameter of 20 μm at 50 μm pitch. However, to achieve further increases in IO density, RDL with 1 μm routing lines and spaces together with 1 to 2 μm diameter microvias are required. Such advances in the RDL technology are of great importance to accomplish IO densities of 500 IOs/mm/layer to enable high bandwidths of 500 Gb/s at low cost. In this paper we present the latest progress at the Packaging Research Center, Georgia Institute of Technology in the following 4 key areas.1. Fine line photolithography: Various methods that can achieve 1 μm critical dimension (CD) are discussed and recent results on 1 μm L/S using both dry film and liquid photoresists together with advanced lithographic tools are presented.2. Small microvia creation: Microvia is the most important barrier limiting the RDL to achieve high IO density and fine IO pitch. In this paper, microvia diameter scaling down to 2 μm along with the feasibility to achieve 1 μm and via pitch of 4 to 8 μm using both photo and picosecond pulsed UV laser will be presented.3. Low Dk and Low Df dielectric materials: Dielectric material layers are an important part of RDL. For achieving multi-functional high speed and/or low loss systems and modules, dielectric layers with low Dk and/or low Df materials are critical. The material requirements, availability and process challenges will be addressed in this paper.4. Process methodology: The semi-additive process (SAP) has been the process of record for RDL fabrication. In this paper, the conventional SAP and its modifications such as modified-SAP (m-SAP) and advanced SAP (a-SAP) together with alternative organic damascene process (ODP) along with back-end- of-line (BEOL) will be reviewed and compared.Finally, considerations for future trends are presented.

Wafer-level packaging with high density fan-out (HDFO) requires multiple redistribution layers (RDL) to handle the high-density interconnections and the large data transfer rates between chips in the package. Decreasing the critical dimension (CD) of lines in an RDL enables electrical performance that meets the system requirements with fewer layers, which lowers costs. Reducing RDL line CD also requires reducing the CD for the interconnections (via) in the dielectric layer. The lithographic imaging of small via openings presents multiple challenges. The first challenge is obtaining good lithographic performance of the permanent photosensitive polymer used to define the dielectric layer between the metal layers. The second challenge is the increased difficulty of imaging a via compared to imaging a line of the same critical dimension, due to both the smaller area of light modulation used to transfer the pattern and the diffraction of the light as it passes through the imaging system. To address these challenges, in this study we relax the dimension of the round via in the direction parallel to the RDL line, creating an elongated via. This design change significantly improves the intensity distribution at the wafer (aerial image) for the via, which increases the effective process window [1].In this paper we investigate the performance of a negative-tone photosensitive permanent dielectric for 1.0 - 2.0 pm CD vias. The permanent photosensitive polymer material is used in a dual damascene RDL process, and previous studies have demonstrated sufficient resolution and process capability [2]. We investigate multiple length-to-width ratios for the vias using both lithographic simulation and experiment to determine the optimal via shape to maximize the process window. In this paper we present both modeled and experimental lithography test results. The process window for the elongated vias shows significant improvement compared to the symmetric via for fine-pitch RDL applications.

Directed Self-Assembly of block copolymers is a lithographic technique being developed to reach sub-10 nm technological nodes. Recently, high chi block copolymers have been developed to achieve higher resolution. In this paper, the high chi system investigated is a modified polystyrene-b-poly(methyl methacrylate)(PS-b-PMMA) presenting a pitch of 18 nm. One critical step for its integration is the PMMA removal selectively to the PS. Two approaches to remove the PMMA phase are presented, highlighting the challenges encountered due to its smaller dimensions. The first one is a full dry approach based on a CH4/N2 chemistry, which presents some bridge formation due to intensive sidewalls passivation and to a species confinement effect accentuated by the small 9-nm critical dimension of the lines. Therefore, the main high chi PS-b-PMMA dry etching difficulties come from the trade-off between obtaining high selectivity and avoiding bridge formation. The second approach is a mixed wet and dry PMMA removal process based on UV exposure followed by solvent rinse. An Ar/O2 dry brush layer opening was developed and the pattern transfer into the SiO2 and Si underlayers is demonstrated for the high chi PS-b-PMMA.

A methodology of obtaining the local critical dimension uniformity of contact hole arrays by using optical scatterometry in conjunction with machine learning algorithms is presented and discussed. Staggered contact hole arrays at 44 nm pitch were created by EUV lithography using three different positive-tone chemically amplified resists. To introduce local critical dimension uniformity variations different exposure conditions for dose and focus were used. Optical scatterometry spectra were acquired post development as well as post etch into a SiN layer. Reference data for the machine learning algorithm were collected by critical dimension scanning electron microscopy (CDSEM). The machine learning algorithm was then trained using the optical spectra and the corresponding calculated LCDU values from CDSEM image analyses. It was found that LCDU and CD can be accurately measured with the proposed methodology both post lithography and post etch. Additionally, since the collection of optical spectra post development is non-destructive, same area measurements are possible to single out etch improvements. This optical metrology technique can be readily implemented inline and significantly improves the throughput compared to currently used electron beam measurements.

As future patterning processes reach the limit of lithographic printability, continuous innovation in mandrel trim or shrink strategies are required to reach sub-20 nm line-space patterning. Growing concerns of lithography defectivity, mask selectivity, line edge roughness (LER), line width roughness (LWR), and critical dimension uniformity (CDU) present significant challenges towards this goal. The authors compare various alternative mandrel trim strategies to highlight potential solutions and drawbacks towards enabling successful printing of mandrels used in extreme ultraviolet (EUV) multi-patterning schemes. Through this comparison, the authors demonstrate the challenges of maintaining adequate pattern transferability while keeping aspect ratio-driven line roughness and material selectivity under control. By process partitioning, the limitations of traditional lithography and etch trimming strategies are highlighted, suggesting the need for new methods of CD reduction after the pattern has been transferred. These new trimming methods offer flexibility in CD control without negatively impacting the mandrel profile and demonstrates better tunability across different material sets, allowing for evaluation of different mask and mandrel material combinations for downstream process optimization.