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Summary: The sharp increase in the leakage part of the total power of the very large scale integration (VLSI) circuits is a significant concern in the deep submicron CMOS process. The NOT gates, Gate Diffusion Input (GDI) cells, restorer NMOS–PMOS transistors for full‐swing operation, and any path from the power voltage to the ground are the main sources of leakage power dissipation as well as short‐circuit in the VLSI CMOS circuits/chips. The input controlled leakage restrainer transistor (ICLRT) is a new circuit‐level method that is proposed in this paper. The ICLRTs can be deliberately added to any VLSI CMOS circuit to largely diminish the total power dissipation especially by the reduction of its leakage and short‐circuit parts. The full adders are vital parts in various VLSI circuits/systems, especially in circuits used for fulfilling arithmetic operations. Those are often placed in the critical paths for multiplication and division, so influence the throughout the efficiency of the system. To test the proposed technique, ICLRTs added to five best 1‐bit hybrid full adders in the deep submicron process to fit the needs of the day. The efficiency of the proposed method is evaluated using SPICE simulations in 22‐nm CMOS BSIM4 process. Evaluation outcomes with 1‐V power supply verified that the power dissipation and power‐delay product (PDP) of the hybrid full adders based on ICLRT technique relative to corresponding original designs are reduced 65.67–95.7% and 35.85–87.37%, respectively. Mismatch analysis and Monte Carlo simulations prove the robustness and stability of the presented circuits in the presence of the process, voltage, and temperature (PVT) variations. [ABSTRACT FROM AUTHOR]

The leakage power, a.k.a. static power, increases in deep-submicron technologies due to short-channel effects. This article proposes a novel input-controlled leakage restrainer transistor (ICLRT)-based technique to reduce leakage power as well as the short-circuit power. The main idea is to place a PMOS and an NMOS ICLRT on top of the pull-up network (PUN) and at the bottom of the pull-down network (PDN), respectively, on all paths from either the supply voltage or the ground to the output. The ICLRTs are deliberately used as a stack structure while being controlled by the input signals to lead the output to stronger low and high logic levels. In fact, the proposed technique reduces the leakage and short-circuit currents and, consequently, powers by increasing the threshold voltage and decreasing the gate-source voltage of the main transistors. Using the proposed technique, logical NOT, NAND, NOR, XOR, and XNOR static gates are designed and evaluated by SPICE simulations in 22-nm BSIM4 (level-54 parameters) CMOS technology. Simulation results with 0.9-V power supply voltage show that power–delay product (PDP) is reduced by 27.66%, 16.7%, and 21.58% for NOT, NOR, and XOR with respect to its best counterpart and by 32.62%, 47%, 49.23%, and 38.77% for NOT, NAND, NOR, and XOR with respect to the conventional static CMOS structures. Furthermore, Monte Carlo analysis is also performed to ensure the stability and robustness of the circuit's performance in the presence of the process, voltage, and temperature (PVT) variations. [ABSTRACT FROM AUTHOR]

A novel full-swing, low-power and energy-aware full adder using hybrid logic scheme is presented in this paper. At first, a new energy-efficient 10T XOR-XNOR cell is designed by modifying inverter and pass transistor based 3T XOR-XNOR gates combined with a feedback loop. The performance of this new cell is compared with some reported ones and then, using this new cell and two other modules, a novel full adder circuit is proposed and evaluated in TSMC 0.18 μm CMOS process technology. Post-layout simulations using Cadence Virtuoso tool showed 33%–74% and 35%–81% improvement in terms of power consumption and power-delay product (PDP), respectively, compared with some well-known counterparts in the literature. Furthermore, high-performance claim of our proposed full adder cell is verified through the process, voltage and temperature (PVT) variations' simulation of the adders. Finally, implementation of different full adders in 4-bit ripple carry adders (RCAs) proved our new design has high performance in the aspects of power dissipation and PDP. [ABSTRACT FROM AUTHOR]

To maintain performance increase and reliability, power supply and threshold voltages will have to continually scale, in CMOS technology. With threshold voltage scaling and thinner gate-oxide thickness, sub-threshold and gate tunneling leakage powers are expected to become a significant portion of the total power in CMOS VLSI systems. A self-control leakage-suppression block (SCLSB) for leakage power reduction of static CMOS gates is proposed in this paper. The proposed SCLSB consists of two PMOS and two NMOS transistors that are located between pull-down network (PDN) and pull-up network (PUN). In any combination of input signals, one PMOS and one NMOS transistor of SCLSB turn on and the rest turn off, hence the resistance between the power supply voltage rail to the ground rail increased and leakage currents greatly reduced. The basic static CMOS gates such as inverter, NAND, NOR, and XOR circuits are designed based on SCLSB and their performance is evaluated using SPICE simulations in 22 nm CMOS BSIM4 process. Evaluation outcomes with V DD = 0.9 V depict that power-delay product (PDP) is diminished by 9%, 12.8%, 6%, and 15.25% for inverter, NAND, NOR, and XOR compared to the best counterpart (LECTOR) and by 9%, 35%, 21.5% and 33.8% compared to the conventional CMOS gates. The mentioned features of the proposed static-CMOS circuits are achieved while sustaining the full-swing behavior. To ensure the stability and robustness of the circuits in the presence of the process, voltage, and temperature (PVT) variations, Monte Carlo analysis is also performed. • Proposing a self-control leakage-suppression block (SCLSB) for leakage power reduction of static CMOS gates. • The proposed SCLSB technique is compatible with single threshold CMOS technology. • The proposed SCLSB consists of two PMOS and two NMOS transistors that are located between PDN and PUN. • Increasing the resistance between VDD to GND because in any combination of input signals at least two transistors turn OFF. • The proposed SCLSB has effectiveness in power and PDP reduction of sequential circuits such as D-latch and D flip-flop. [ABSTRACT FROM AUTHOR]