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The impact of dynamic variability due to low-frequency fluctuations on the operation of CMOS inverters, which constitute the basic component of SRAM cell, is investigated. The experimental methodology to characterise the effect of dynamic variability in a CMOS inverter is first established based on fast I-V measurements of the load current following the application of a ramp input voltage Vin(t). It is shown that, for small ramp rise times, the load current characteristics IDD(Vin) exhibit a huge sweep-to-sweep dispersion due to low-frequency noise. The impact of such dynamic variability sources on the inverter's output characteristics Vout(Vin) is finally demonstrated, revealing a 20% noise margin reduction for the smallest inverter cell. [ABSTRACT FROM AUTHOR]

Abstract: Extensive investigation of the low-frequency noise in n-channel and p-channel MOSFETs, with high-k gate stack and channel length varying from 1.8μm down to 26.4nm, has been carried out. The results demonstrate that the carrier number fluctuation with correlated mobility fluctuations describes accurately and continuously the 1/f noise for all operation regions, i.e. from weak to strong inversion and from linear to saturation. It has been found that the product of the Coulomb scattering coefficient and the effective carrier mobility is constant over a wide range of the drain current due to the interplay of the Coulomb scattering coefficient αsc and the effective carrier mobility μeff variations. In addition, a non-linear increase in the square root of the input gate voltage noise with the gate voltage overdrive was observed explained by the surface roughness scattering. The overall results lead to an analytical expression for the 1/f noise model, enabling to predict the noise level of a transistor with any channel dimensions using its transfer characteristic. This finding makes the noise model suitable for circuit simulation tools. [Copyright &y& Elsevier]

A new full gate voltage range methodology using a Lambert W function based inversion charge model, for extracting the electrical parameters in FDSOI nano-MOSFET devices, has been developed. Split capacitance–voltage measurements carried out on 14 nm technology FDSOI devices show that the inversion charge variation with gate voltage can be well described by a Lambert W function. Based on the drain current equation in the linear region including the inversion charge described by the Lambert function of gate voltage and the standard mobility equation enables five electrical MOSFET parameters to be extracted from experimental I d – V g measurements (ideality factor, threshold voltage, low field mobility, first and second order mobility attenuation factors). The extracted parameters were compared with those extracted by the well-known Y-function in strong inversion region. The present methodology for extracting the electrical MOSFET parameters was verified over a wide range of channel lengths on nano-scale FDSOI devices, demonstrating its simplicity, accuracy and robustness. [ABSTRACT FROM AUTHOR]

Highlights: [•] Impact of UTBOX with GP and local Vb on bitcells performance improvement. [•] The V T variation increases when opposite GP doping is used for NMOS and PMOS. [•] As the BOX thickness is reduced this V T variation versus Vb increases. [•] Back bias improve bitcells performance in FBB and RBB as in bulk. [•] For gated and STI diodes, hybrid technology improves TLP at the same level as bulk. [ABSTRACT FROM AUTHOR]