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Accurate characterization of radiation-induced soft errors is a critical step toward understanding the impact of these glitches on circuit and system reliability. With process scaling, there has been exponential increase in number of transistors that can be packed on a die which, in turn, results in higher sensitive node count and persistent soft error susceptibilities. In this work, a novel circuit technique employing higher sensitivity toward soft errors is proposed. The circuit makes use of current-starved gates with bias knobs to fine-tune both measurement resolution and strike sensitivity enabling accelerated and efficient induction of errors in a limited-time irradiation test environment. The back-sampling chain (BSC) circuit can measure individual radiation-induced transient pulse with as low amplitude as $0.3\times $ VDD while maintaining a high measurement resolution for pulsewidth characterization. The bias knobs allowing tuning of sensitivity and resolution enable, for the first time, a strike pulse waveform reconstruction methodology that can be used to calibrate current pulse models for assessing soft error rate (SER) sensitivity of standard logic gates. [ABSTRACT FROM AUTHOR]

This work presents measured data showcasing neutron-radiation-induced single-event transient (SET) pulse widths in distinct standard logic gate types, together with a detailed analysis on the choice of design parameters impacting the corresponding sampled pulsewidth distributions. The SET pulsewidth distributions are obtained from a high-density, array-based characterization vehicle, implemented in 65-nm planar CMOS and 16-nm FinFET processes, featuring a tunable, high-resolution pulse shrinking chain together with a closely embedded sampling circuit to avoid width distortion effects. The proposed macro uses standard logic gate chains in varying lengths, threshold voltages ($V_{\mathrm {TH}}$), and transistor width flavors as the devices under test (DUTs). The measured irradiation data for a range of operating voltages from nominal down to near-threshold reveal the relative impact of the chosen design parameters such as VDD, $V_{\mathrm {TH}}$ , device width, and the logic chain length and their interplay, impacting the overall soft error susceptibility and the sampled pulsewidth distributions among the different standard gate types. [ABSTRACT FROM AUTHOR]

The impact of random telegraph noise (RTN) on circuit delay has been experimentally verified using a dual ring oscillator (ROSC) array test structure. The proposed on-chip monitor utilizes the tested-and-proven beat frequency detection technique to measure RTN-induced frequency shifts with high precision (>0.01%) and short sampling time (>1 \mu \texts ). The main idea is to pair an ROSC in the first array with an ROSC having a similar frequency from a second array, so that the frequency measurement resolution is not compromised at sub-0.5-V supply voltages. RTN-induced frequency shifts at different supply voltages, temperatures, and stress conditions were measured from a 32-nm high-k metal-gate test chip. The impact of RTN on logic and SRAM performance was analyzed based on the measured RTN data. We also present the quantitative results of logic timing margin and SRAM noise margin, with and without RTN. According to this paper, RTN appears to have a modest 1% impact on circuit operating frequency in 32 nm, even under pessimistic conditions (i.e., V\mathrm {dd} = 0.6 V, multiple RTN traps in circuit path). [ABSTRACT FROM PUBLISHER]

Single-poly embedded flash (eFlash) memory is a unique category of embedded nonvolatile memory (eNVM) that can be built in a generic logic technology. Several single-poly eFlash cells have been proposed for cost-effective moderate density eNVM applications. However, the optimal cell configuration of single-poly eFlash is still under debate. In this paper, we compared various single-poly eFlash memory structures in terms of disturbance, program/erase speed, endurance, and retention characteristic based on simulated and experimental data from two eFlash test chips fabricated in a generic 65-nm logic process using standard 2.5 V I/O transistors with 5-nm tunnel oxide. We conclude that a 5T eFlash cell structure combining a pMOS coupling device, an NCAP tunneling device, and an nMOS read/program device with two additional pass transistors to support self-boosting is the most attractive option for logic-compatible eNVMs. [ABSTRACT FROM AUTHOR]

A truly logic-compatible gain cell eDRAM macro with no boosted supplies is presented. A 2T1C gain cell implemented only with regular thin oxide devices consists of an asymmetric 2T cell and a coupling PMOS capacitor. The PMOS capacitor ensures proper operation even without a boosted supply by utilizing a beneficial coupling for read and a preferential boosting for write. A repair scheme based on a single-ended 7T SRAM has features such as a local differential write and shared control with the main 2T1C array. A storage voltage monitor is proposed to track the retention characteristics of a gain cell eDRAM under PVT variations and to adjust its refresh rate adaptively. A 128 kb eDRAM test chip implemented in a 65 nm Low-Power (LP) process operates at a random access frequency of 714 MHz with a static power dissipation of 161.8 µW per Mb for a 500 µs refresh rate at 1.1 V and 85°C. [ABSTRACT FROM AUTHOR]

Negative bias temperature instability (NBTI) in pMOS transistors has become a major reliability concern in present-day digital circuit design. Further, with the recent introduction of Hf-based high-k dielectrics for gate leakage reduction, positive bias temperature instability (PBTI), the dual effect in nMOS transistors, has also reached significant levels. Consequently, designs are required to build in substantial guardbands in order to guarantee reliable operation over the lifetime of a chip, and these involve large area and power overheads. In this paper, we begin by proposing the use of adaptive body bias (ABB) and adaptive supply voltage (ASV) to maintain optimal performance of an aged circuit, and demonstrate its advantages over a guardbanding technique such as synthesis. We then present a hybrid approach, utilizing the merits of both ABB and synthesis, to ensure that the resultant circuit meets the performance constraints over its lifetime, and has a minimal area and power overhead, as compared with a nominally designed circuit. [ABSTRACT FROM AUTHOR]

Leakage power is becoming the dominant component of chip power consumption with continued CMOS scaling. An important but commonly unnoticed fact is that leaky transistors act as resistors that help dampen the mid-frequency power supply noise. This paper focuses on the damping effect of various on-chip current components including the leakage current which becomes significant in scaled technologies. By developing physics-based damping models for active and leakage currents, we show that leakage, particularly gate tunneling leakage, provides more damping than strong-inversion current. The proposed models were validated in a 32-nm predictive CMOS technology under process-voltage-temperature (PVT) variations. Examples on large circuits such as SRAM caches are shown to illustrate the application of the proposed model. Simulation results show that the leakage induced damping effect can compensate the speed degradation at high temperatures by 7% or offer 61% saving in decap area and leakage power. [ABSTRACT FROM AUTHOR]

The article focuses on the analysis of leakage power analysis and reduction for nanoscale circuits. The author contended that leakage current in the nanometer regime has become portion of power dissipation in CMOS circuits. Furthermore, threshold voltage, channel length, and gate oxide thickness have scale downward. Moreover, various technique are available to reduce leakage power in high-performance systems. Various techniques are available to reduce leakage power in high-performance systems. The author looks into the various aspects of leakage components. Various circuit and design time techniques have been implemented to reduce leakage in logic and cache memory.