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In this paper, binary decision diagram (BDD)-based dual-rail precharge logic circuit schemes have been developed to counter differential power analysis attacks, timing attacks, and early propagation attacks. Different precharge logic schemes (top precharging, top–bottom precharging, bottom precharging, and symmetric nMOS bottom precharging) are presented and evaluated. The hallmark of our circuit schemes is that an identical number of switchings is ensured on each circuit path. The transistors are interconnected to create pull-up and pull-down paths to outputs by way of binary decisions based on the input variables, so as to realize the required Boolean function. A simple synthesis algorithm for mapping a given Boolean function to such a BDD-based circuit is also presented. Experimentation has been carried out on two 4-, 16-, 32-, and 64-bits S-boxes to establish resistance of our circuits to power analysis attack and to highlight the low-power characteristics with the help of attributes such as peak power variance, average power, propagation delay, normalized standard deviation of power, and normalized energy deviation. Differential power attacks such as difference of mean and correlation power analysis have been carried out. Resilience to the early propagation effect is also demonstrated. [ABSTRACT FROM AUTHOR]

This paper presents an exploration procedure for mapping given functional specifications of an analog system to the specification parameters of individual component blocks of the system topology. A meet-in-the-middle approach has been followed for constructing the feasible design space. It is constructed as the intersection of an application-bounded specification space and a circuit-realizable specification space. The least squares support vector machine principle is used to accurately identify the actual geometry of the feasible design space. The reduced design space speeds up the exploration procedure. The benefit of our methodology is the ability to obtain practically correct circuit-level specifications of the component blocks of the system in a single pass. The effectiveness of the procedure has been demonstrated by considering a complete system. The simulation results satisfy the desired specifications of the system, validating the overall procedure. [ABSTRACT FROM AUTHOR]