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The search for energy efficiency in the design of embedded systems is leading toward CPUs with higher instruction-level and data-level parallelism. Unfortunately, individual applications do not have sufficient parallelism to keep all these CPU resources busy. Since embedded systems often consist of multiple tasks, task-level parallelism can be used for the purpose. Simultaneous multi-threading (SMT) proved a valuable technique to do so in high-performance systems, but it cannot be afforded in system with tight energy budgets. Moreover, it does not exploit data-level parallel hardware, and does not exploit the available information on threads. We propose software-SMT (SW-SMT), a technique to exploit task-level parallelism to improve the utilization of both instruction-level and data-level parallel hardware, thereby improving performance. The technique performs simultaneous compilation of multiple threads at design-time, and it includes a run-time selection of the most efficient mixes. We have applied the technique to two major blocks of a SDR (software-defined radio) application, achieving energy gains up to 46% on different ILP and DLP architectures. We show that the potentials of SW-SMT increase with SIMD datapath size and VLIW issue width. [ABSTRACT FROM AUTHOR]

Tomorrow's embedded devices need to run high-resolution multimedia applications which need an enormous computational complexity with a very low energy consumption constraint. In this context, the register file is one of the key sources of power consumption and its inappropriate design and management can severely affect the performance of the system. In this paper, we present a new approach to reduce the energy of the shared register file in upcoming embedded VLIW architectures with several processing units. Energy savings up to a 60% can be obtained in the register file without any performance penalty. It is based on a set of hardware extensions and a compiler-based energy-aware register assignment algorithm that enable the de/activation of parts of the register file (i.e. sub-banks) in an independent way at run-time, which can be easily included in these embedded architectures. [ABSTRACT FROM AUTHOR]

This paper presents a modular optimization framework for custom digital circuits in the power - performance space. The method uses a static timer and a nonlinear optimizer to maximize the performance of digital circuits within a limited power budget by tuning various variables such as gate sizes, supply, and threshold voltages. It can employ different models to characterize the components. Analytical models usually lead to convex optimization problems where the optimality of the results is guaranteed. Tabulated models or an arbitrary timing signoff tool can be used if better accuracy is desired and although the optimality of the results cannot be guaranteed, it can be verified against a near-optimality boundary. The optimization examples are presented on 64-bit carry-lookahead adders. By achieving the power optimality of the underlying circuit fabric, this framework can be used by logic designers and system architects to make optimal decisions at the microarchitecture level. [ABSTRACT FROM AUTHOR]

Violations in the timing constraints of a clocked register can cause a synchronous system to malfunction. The effects of parameter variations on the timing characteristics of registers that determine the timing constraints are investigated in this paper. The sensitivity of the setup time and data propagation delay to parameter variations is demonstrated for four different register designs. The robustness of each register design under variations in power supply voltage, temperature, and gate oxide thickness is determined. [ABSTRACT FROM AUTHOR]

Today the demands of power optimized strategies have become one of the biggest challenges for developers. The sooner the aspect of low power is considered in the design process the greater the effect is on power consumption of the system design later on. Therefore the developer should have access to power information at an early stage of the design process. Our approach is to develop a design framework which allows a high level specification of a given algorithm while allowing a consistent hardware implementation of a digital signal processing system across all steps in the tool-chain, from the behavioral specification up to the placed and routed netlist. In this paper we present how to use this framework for the optimization of digital audio processing modules and show some results. [ABSTRACT FROM AUTHOR]

A new method for predicting timing jitter caused by device noise in current-mode logic (CML) frequency dividers is presented. Device noise transformation into jitter is modeled as a linear time-varying (LTV) process, as opposed to a previously published method, which models jitter generation as a linear time-invariant (LTI) process. Predictions obtained using the LTV method match jitter values obtained through exhaustive simulation with an error of up to 7.7 %, whereas errors of the jitter predicted by the LTI method exceed 57 %. [ABSTRACT FROM AUTHOR]

In low power UDSM process the use of reduced supply voltage with high threshold voltages may reverse the temperature dependence of designs. In this paper we propose a model to define the true worst Process, Voltage and Temperature conditions to be used to verify a design. This model will provide an accurate worst case definition for high performance designs where standard design margins are not applicable. This model is validated at either cell level or path level on two different 130nm process. [ABSTRACT FROM AUTHOR]

The work presented here consists of investigating and studying the electronic properties of anodic oxide film (SiO2). This study deals to the determination of interface states density Si/SiO2 and the study of electronic conduction. MOS capacitors with anodic oxides (9nm) were elaborated. The anodic silica films were produced by anodization of monocristalline silicon wafers in pure water in an electrolysis cell (P.T.F.E) at room temperature, with a constant current density of 20 μA/cm2. Film thickness increases linearly as a function of total charge during oxidation Using C(V),G(ω),I(V) measurements, we have determined the interface states density, fixed charges density and conduction mechanism which is of Fowler - Nordheim type for annealed oxides at various temperatures. Keywords: Anodic oxidation,Pure water, Fixed Charges, interface States density, Si/SiO2,Electrical characterisation, MOS Structures, Fowler-Nordheim tunnelling. [ABSTRACT FROM AUTHOR]

In this paper, a novel economically linearized widely tunable very low power and low noise differential transconductor is proposed and compared with the conventional differential pair. The application of the resulted transconductor as a negative resistor is presented. The linearity, power, noise, speed, and tunability performances are simulated, discussed, and compared with the conventional differential pair's. Keywords: Differential transconductors, negative resistors, analog circuits and filters, low noise, low power, widely tunable circuits, GHz range frequencies, continuous-time filters, Q-enhanced active filters, Gm-C filters, RF, VCO. [ABSTRACT FROM AUTHOR]

This paper describes the novel design of an on-chip noise-monitoring device, which can measure the power supply noise of each individual macro and determine the noise interference between different macros. A hierarchical noise-monitoring system is proposed to monitor and store the power supply noise information for core-based design, as part of the built-in-self-test system. The method can be further extended from system-on-chip to system-on-package to provide a complete coverage of noise testing methodology. The circuit of a properly-sized noise monitor has been simulated with the actual VDD and GND noise waveforms of a 4-GHz benchmark microprocessor to verify its functionality. [ABSTRACT FROM AUTHOR]

This paper presents a study of the power dissipation repercussion on the logic and physical synthesis using LUT architectures. It is observed that the same function with different mappings on a LUT show different power dissipation. In concrete, the study reveals that the difference depends on the number of inputs of the Boolean function mapped. A power model based on this concept is developed. The power model is used to analyze the efficiency of the synthesis concerning power dissipation in LUTs. Also, a study of the fan-out and the function mapped is done. A power cost model is created to associate the fan-out and our power model. A set of circuits have been synthesized with an academic FPGA synthesis tool. The synthesis tool is used with the options of optimal delay, optimal area and delay-area trade-off. Our study shows that, in this case, synthesizing for area or delay does not affect the power dissipation. Three different LUT architectures have been studied. Results show that a four input LUT is a good choice concerning power dissipation. [ABSTRACT FROM AUTHOR]

If adjacent wires are brought into a simple specific order of their switching activities, the effect of power optimal wire spacing can be increased. In this paper we will present this order along with a prove of this observation. For this purpose, it is shown how to derive the new power optimal wire positions by solving a geometric program. Due to their simplicity in implementation, both principles reported substantially differ from previous approaches. We also quantify the power optimization potential for wires based on a representative circuit model, with promising results. [ABSTRACT FROM AUTHOR]

Addition is the most important operation in data processing and its speed has a significant impact on the overall performance of digital circuits. Therefore, many techniques have been proposed for fast adder design. An asynchronous ripple-carry adder is claimed to use a simple circuit implementation to gain a fast average performance as long as the worst cases input patterns rarely happen. However, based on the input vectors from a number of benchmarks, we observe that the worst cases are not exceptional but commonly exist. A simple carry-lookahead scheme is proposed in the paper to speed up the worst-case delay of a ripple-carry adder. The experiment result shows the proposed adder is about 25% faster than an asynchronous ripple-carry adder with only small area and power overheads. [ABSTRACT FROM AUTHOR]

Clock distribution has become an increasingly challenging problem for VLSI designs because of the increase in die size and integration levels, along with stronger requirements for integrated circuit speed and reliability. Additionally, the great amount of synchronous hardware in integrated circuits makes current requirements to be very large at very precise instants. This paper presents a new approach for clock distribution in PID controllers based on RNS, where channel independence removes clock timing restrictions. This approach generates several clock signals with non-overlapping edges from a global clock. The resulting VLSI RNS-enabled PID controller, shows a significant decrease in current requirements (the maximum current spike is reduced to a 14% of single clock distribution one at 125 Mhz) and a homogeneous time distribution of current supply to the chip, while keeping extra hardware and power to a minimum. [ABSTRACT FROM AUTHOR]

For static CMOS Clock-Gating is a well-known method to decrease dynamic losses. In order to reduce the static power consumption caused by leakage currents, Power-Gating has been introduced. This paper presents for the first time Clock-Gating and Power-Gating in Adiabatic Logic. As the oscillator signal is both the power and the clock in Adiabatic Logic, a Power-Clock Gating is implemented using a switch to detach the adiabatic logic block from the oscillator. Depending on the technology the optimum switch topology and dimension is discussed. This paper shows that a boosted n-channel MOSFET as well as a transmission gate are good choices as a switch. Adiabatic losses are reduced greatly by shutting down idle adiabatic circuit blocks with Power-Clock Gating. [ABSTRACT FROM AUTHOR]

In this work, the optimization of circuits design by using multiobjective evolutionary algorithm is addressed. This methodology enable to deal with circuit specifications -formulated as objective functions- that can be conflicting and want to be optimize at the same time. After the optimization process, a set of different trade-off solutions for the design of the circuit is obtained. This way, SPEA (Strength Pareto Evolutionary Algorithm) has been tested as optimizer of an hybrid CBL/CMOS configurable cell. As a result, some conclusions about the optimized values of the transistor sizes of this cell in order to minimized some power comsumption and delay timing specifications are obtained. [ABSTRACT FROM AUTHOR]

Due to the development of high performance portable applications associated to the high-density integration allowed by deep submicron processes, circuit optimization under delay constraints has emerged as a critical issue for VLSI designers. The objective of this work is to avoid the use of random mathematical methods (very CPU time expensive), by defining simple, fast and deterministic indicators allowing easy and fast implementation of circuits at the required speed. We propose to extend the method of equal sensitivity, previously developed for combinatorial paths [1], to circuit sizing in order to solve the circuit convergence branch problem. We propose a coefficient based approach to solve the divergence branch problem. Validation is given by comparing with an industrial tool the performance of different benchmarks implemented in a standard 180nm CMOS process. [ABSTRACT FROM AUTHOR]

This paper presents a design automation tool for the generation of sensor interfaces for low-power applications. The tool combines design reuse of known low-power circuits and an efficient optimization algorithm to generate circuits adapted to specific applications. The part of the tool that generates signal filters is described, and the optimization algorithm is compared to other possible optimization methods. Two filters are designed using the tool. Simulation results are compared to existing filters. These results indicate that the filter tool has the desired functionality. [ABSTRACT FROM AUTHOR]

This paper presents temperature aware low power scheduling under resource and latency constraints. We assume resources with different energy delay values are available. These resources are optimized in terms of energy for a certain delay, using variable supply voltage, multiple threshold voltages and sizing techniques. The proposed algorithms are based on temperature and power efficient distribution of slack among the nodes in the data-flow graph. The distribution procedure tries to implement the minimum energy scheduling when there is no temperature critical points. If a functional unit reaches a critical temperature, algorithm tries not to schedule any nodes in the data flow graph to high temperature resources, thus decrease the chip temperature. Experiments with some HLS benchmark examples show that the proposed algorithms achieve significant power/energy reduction. For instance, when the latency constraint is 2 times the critical path delay and one of the resource temperature is critical the average power reduction is 50.8% and utilization of the hot resource is average 1%. [ABSTRACT FROM AUTHOR]

This paper presents the design of a new dynamic addition circuit based on a hybrid ripple-carry/carry-look-ahead/carry-bypass approach. In order to reduce power, the usage of duplicated carry-select stages is avoided. High computational speed is reached thanks to the implemented two-phase running. The latter makes the proposed adder able to exploit the time usually wasted for precharging dynamic circuits to accelerate the actual computation. Limited power dissipation and low area occupancy are guaranteed by optimizations done at both architecture and transistor levels. When realized using the UMC 0.18mm 1.8V CMOS technology, the new 64-bit adder exhibits a power-delay product of only 30.8pJ*ns and requires less than 3400 transistors. [ABSTRACT FROM AUTHOR]

Modern embedded processors use small and simple branch predictors to improve performance. Using complex and accurate branch predictors, while desirable, is not possible as such predictors impose high power and area overhead which is not affordable in an embedded processor. As a result, for some applications, misprediction rate can be high. Such mispredictions result in energy wasted down the mispredicted path. We introduce area-aware and low-complexity pipeline gating mechanisms to reduce energy lost to possible branch mispredictions in embedded processors. We show that by using a simple gating mechanism which comes with 33-bit area overhead, on average, we can reduce the number of executed instructions by 17% (max: 30%) while paying a negligible performance cost (average 1.1%). [ABSTRACT FROM AUTHOR]

Hash functions are widely used in applications that call for data integrity and signature authentication at electronic transactions. A hash function is utilized in the security layer of every communication protocol. As time passes more sophisticated applications arise that address to more users-clients and thus demand for higher throughput. Furthermore, due to the tendency of the market to minimize devices' size and increase their autonomy to make them portable, power issues have also to be considered. The existing SHA-1 Hash Function implementations (SHA-1 is common in many protocols e.g. IPSec) limit throughput to a maximum of 2 Gbps. In this paper, a new implementation comes to exceed this limit improving the throughput by 53%. Furthermore,power dissipation is kept low compared to previous works, in such way that the proposed implementation can be characterized as low-power. [ABSTRACT FROM AUTHOR]

Based on a previously reported request driven technique for Globally-Asynchronous Locally-Synchronous (GALS) circuits this paper presents two significant enhancements. Firstly, the previously required local ring oscillators are avoided. Instead, an external clock with arbitrary phase for each GALS block is used. Details of the required wrapper circuitry, the proposed design flow and performance are provided. Secondly, to reduce supply noise, a novel approach applying individual clock jitter for GALS blocks is proposed. A simulation using the jitter technique shows that for a typical GALS system, the power spectrum of the supply current can be reduced by about 15 dB. [ABSTRACT FROM AUTHOR]

This paper aims at introducing a method to quickly design compact dual-rail asynchronous primitives. If the proposed cells are dedicated to the design of dual-rail asynchronous circuits, it is also possible to use such primitives to design dual-rail synchronous circuits. The method detailed herein has been applied to develop the schematics of various basic primitives. The performances of the 130nm obtained cells have been simulated and compared with more traditional implementations. [ABSTRACT FROM AUTHOR]

The increasing popularity of mobile computers and embedded computing applications drives the need for analysing and optimising power in every component of a system. This paper presents a measurement based instruction-level power consumption model of the popular Texas Instruments TMS320VC5510 Digital Signal Processor. The results provide an accurate and practical way of quantifying the power impact of software. The measurement and characterisation methodology are presented along with the results extracted. Finally some power saving techniques are introduced together with an assesment of their impact. [ABSTRACT FROM AUTHOR]

This paper presents principles and concepts for the secured design of cryptographic IC's. In order to achieve a secure implementation of those structures, we propose to use a Binary Decision Diagrams (BDDs) approach to design and determine the most secured structures in Dynamic Current Mode Logic. We apply a BDD based prediction to the power consumption of some gates, validate our model using SPICE simulations, and use it to mount efficient power analysis attacks on a component of a cryptographic algorithm. Moreover, relying on our simulation results, we propose a complete methodology based on our BDD model to obtain secured IC's, from the boolean function to the final circuit layout. Keywords: Differential Pull Down Networks, Binary Decision Diagrams, Differential Power Analysis, Side-channel attack. [ABSTRACT FROM AUTHOR]

Scan architectures, though widely used in modern designs for testing purpose, are expensive in power consumption. In this paper, we first discuss the issues of excessive peak power consumption during scan testing. We next show that taking care of high current levels during the test cycle is highly relevant so as to avoid noise phenomena such as IR-drop or Ground Bounce. Next, we discuss a set of possible solutions to minimize peak power during all test cycles of a scan testing process. These solutions cover power-aware design solutions, scan chain stitching techniques and pattern modification heuristics. [ABSTRACT FROM AUTHOR]

This paper proposes an approach for reducing energy consumption of computer display. Unlike existing power management schemes, which link the display operation to a key press or movement of the mouse, we employ a video camera to bind the display power state to the actual user's attention. The proposed method keeps display active only if its user looks at the screen. When the user detracts his or her attention from the screen, the method dims the display down or even switches it off to save energy. Experiments show that the method can reduce the display energy significantly in environments which frequently detract the display viewer. [ABSTRACT FROM AUTHOR]

This paper discusses techniques that reduce the complexity and power dissipated by nonlinear operators in a digital signal processing system. In particular, a technique is presented that allows the designer to trade signal quality measured in SNR for power dissipation reduction. Signal quality refers here to the severity of the impact of overflow. The proposed approach is based on the nonlinear operation of saturation, as a means to control overflow. Furthermore, the organization of digital circuits for the computation of powers is discussed. [ABSTRACT FROM AUTHOR]

Contemporary superscalar processors, designed with a one-size-fits-all philosophy, grossly overcommit significant portions of datapath resources that remain unnecessarily activated in the course of program execution. We present a simple scheme for selectively activating regions within the register file and the reorder buffer for reducing leakage as well as dynamic power dissipation. Our techniques result in power savings in excess of 60% in these components, on the average with no performance loss. [ABSTRACT FROM AUTHOR]

Reducing leakage current in memories is critical for low-power designs in deep submicron technology. A common architectural technique consists of lowering the supply voltage to operate SRAM cells in sub-threshold (Vth). This paper investigates stability aspects of sub-Vth SRAM cells, both analytically and by simulation in STMicroelectronics' 90nm CMOS technology. For the first time analytical expressions for the Static Noise Margin in sub-Vth as a function of circuit parameters, operating conditions and process variations are derived. The 3G receiver case study illustrates the leakage saving potential of stable sub-Vth SRAM designs resulting into energy savings of up to 65%. [ABSTRACT FROM AUTHOR]

Memory partitioning has proved to be a promising solution to reduce energy consumption in complex SoCs. Memory partitioning comes in different flavors, depending on the specific domain of usage and design constraints to be met. In this paper, we consider a technique that allows us to customize the architecture of physically partitioned SRAM macros according to the given application to be executed. We present design solutions for the various components of the partitioned memory architecture, and develop a memory generator for automatically generating layouts and schematics of the optimized memory macros. Experimental results, collected for two different case studies, demonstrate the efficiency of the architecture and the usability of the prototype memory generator. In fact, the achieved energy savings w.r.t. implementations featuring monolithic architectures, are around 43% for a memory macro of 1KByte, and around 45% for a memory macro of 8KByte. [ABSTRACT FROM AUTHOR]

DRAM idle power consumption consists for a large part of the power required for the refresh operation. This is exacerbated by (i) increasing amount of memory devoted to cache, that filter out many accesses to DRAM, and (ii) increased temperature of the chips, which increase leakage and thus data retention times. The well-known structured distribution of zeros in a memory, combined with the observation that cells containing zeros in a DRAM do not require to be refreshed, can be constructively used together to reduce the unnecessary number of required refresh operations. We propose a value-based selective refresh scheme in which both horizontal and vertical clusters of zeros are identified and used to selectively deactivated refresh of such clusters. As a result, our technique significantly achieves a net reduction of the number of refresh operations on average of 31%, evaluated on a set of typical embedded applications. [ABSTRACT FROM AUTHOR]

Detailed analysis of CMOS gate behaviour shows that a gate load and input capacitance depends on number of their activated inputs and kind of applied signals i.e. steady state, edge. And in consequence it has an influence on power dissipation. So a reason of the gate switching can be called as the gate driving way. Based on the probability of the gate driving way and associated portion of dissipated energy more accurate model of power dissipation for CMOS gates and circuits is presented. Example of circuits synthesis show power reduction possibilities during design of two-level logic circuits based on information about primary input vector changes - a new circuit activity measure. [ABSTRACT FROM AUTHOR]

The energy efficiency of a 0.25 μm general-purpose FIR filter design, based on two-phase clocking, versus a functionally equivalent benchmark, based on one-phase clocking, is demonstrated by means of measurements and transistor level simulations. Architectural improvements enable already a 20% energy savings of the two-phase clocking implementation. Yet, for the first time, the limitations imposed by the supply voltage (< 2.1 V) and the operating frequency (< 10 MHz) on the actual energy efficiency of this low-power strategy are investigated. Transistor level re-design is undertaken: a new slew-insensitive latch is presented and replaced inside the two-phase implementation. Spectre simulations point out the final 30% savings. [ABSTRACT FROM AUTHOR]

The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multi-input CMOS gate is designed to have the same input to output delay irrespective of which input caused the output to change. A gate which can offer different delays for different input-output paths through it, is known as a variable input delay(VID) gate and the maximum difference in delay between any two paths through the same gate is known as "ub". These gates can be used for minimizing the active power of a digital CMOS circuit using a previosuly described technique called variable input delay(VID) logic. This previous publication proposed three different designs for implementating the VID gate. In this paper, we describe a technique for transistor sizing of these three flavors of the VID gate for a given delay requirement. We also describe techniques for calculating the ub of each flavor. We outline an algorithm for quick determination of the transistor sizes for a gate for a given load capacitance. [ABSTRACT FROM AUTHOR]

Nowadays, verification of digital integrated circuit has been focused more and more from the timing and area field to current and power estimations. The main problem with this kind of verification is on the lack of precision of current estimations when working at higher levels (logic, RT, architectural levels). To solve this problem it is not only necessary to use good current models for switching activity but, also, it is necessary to calculate this switching activity with high accuracy. In this paper we present an alternative to estimate current consumption using logic-level simulation. To do that, we use a simple but accurate enough current model to calculate the current consumption for each signal transition, and a delay model that obtains high accuracy when it is used to measure the switching activity (the Degradation Delay Model -DDM-). In the paper we present the current model for CMOS inverter, the characterization process and the model implementation in the logic simulator HALOTIS that includes the DDM. Results show a high accuracy in the estimation of current curves when compared to HSPICE, and a potentially large improvement over conventional approaches. [ABSTRACT FROM AUTHOR]

In this paper we present an innovative clustering technique which is combined with a simple tool configuration search aimed at power minimisation in LUT (look-up table)-based FPGAs. The goal of our technique is to reduce the capacitance on high power consuming nets by including as many of these nets as possible inside clusters wherein they can be routed on low capacitance lines. We introduce two new metrics for identifying power critical nets based on the switching activity and the number of net-segments that can be totally absorbed by a cluster. The results of our method show an average reduction of 32.8% with a maximum reduction of 48.9% in the net power over that achieved by Xilinx's ISE 5.3i tools. [ABSTRACT FROM AUTHOR]

Embedded hard real-time systems have stringent timing constraints that must be satisfied for the correct functioning of the system. Additionally, there are systems where energy is another constraint that must also be satisfied. In order to satisfy such requirements, a pre-runtime scheduling is presented to find a feasible schedule satisfying both constraints. The proposed approach uses state space exploration for finding feasible schedules taking into account timing and energy constraints. The main problem with such method is the space size, which can grow exponentially. This paper shows how to minimize this problem, and presents a depth-first search method on a timed labeled transition system derived from the time Petri net model. EZPetri is an Eclipse perspective for Petri nets based on PNML. It provides facilities for integrating Petri net applications and existing Petri net tools. In this paper we demonstrate how the plug-in technology of Eclipse was employed to integrate the pre-runtime scheduling synthesis framework with the EZPetri environment. In order to depict the practical usability of the proposed approach, a pulse-oximeter case study is adopted to show how to find a feasible schedule. [ABSTRACT FROM AUTHOR]

We have developed a complete design flow from Verilog/VHDL to layout that generates what is effectively a post-layout power versus delay curve for a digital IC block. Post-layout timing convergence is rapid over the entire delay range spanned by a power versus delay tradeoff curve. The points on the gate-sizing generated power-delay curve, when actually laid out, are extremely close in transistor-level simulated power and delay, using full 3D extracted parasitics. The user can therefore confidently obtain any feasible post-layout power-delay tradeoff from the power-delay curve for a logic block. To the best of our knowledge, this is the first report of such a post-layout capability. [ABSTRACT FROM AUTHOR]

In this communication, RC tree networks are analyzed in terms of the energy dissipated during an input transition. A closed-form analytical model of the energy consumption is derived for arbitrary values of the input rise time by introducing a suitable first-order equivalent RC circuit, which avoids the explicit pole-zero evaluation. The proposed expression of the energy consumption has an evident meaning, thereby affording a deeper understanding of the network dissipation. Moreover, the energy model is sufficiently simple to be used in pencil-and-paper calculations. Extensive SPICE simulations confirm that the model has an adequate accuracy, as its error is typically within 5%. [ABSTRACT FROM AUTHOR]

Critical Path Analysis is always an important task in timing verification. For today's nanometer IC technologies, process variations have a significant impact on circuit performance. The variability can change the criticality of long paths [1]. Therefore, statistical approaches should be incorporated in Critical Path Analysis. In this paper, we present two novel techniques that can efficiently evaluate path criticality under statistical non-linear delay models. They are integrated into a block-based Statistical Timing tool with the capability of handling arbitrary correlations from manufacturing process dependence and also path sharing. Experiments on ISCAS85 benchmarks prove both accuracy and efficiency of these techniques. [ABSTRACT FROM AUTHOR]

In this paper, we present a model, Internode, that unifies the gate functional behavior and the dynamic one. It is based on a FSM that represents the internal state of the gate depending on the electrical load of its internal nodes allowing to consider aspects like input collisions and internal power consumption. Also, we explain the importance of internal power consumption (such effect occurs when an input transition does not affect the output) in three different technologies (AMS 0.6 μm, AMS 0.35 μm, and UMC 130 nm). This consumption becomes more remarkable as technology advances yielding to underestimating up to 9.4% of global power consumption in the UMC 130 nm case. Finally, we show how to optimize power estimation in the SCMOS NOR-2 gate by applying Internode to modeling its consumption accurately. [ABSTRACT FROM AUTHOR]

We present a compact model to estimate quickly and accurately the leakage power in CMOS nanometer Integrated Circuits (ICs). The model has similar accuracy than SPICE and represents an important improvement with respect to previous works. It has been developed to be used for fast and accurate estimation and optimization of the standby power dissipated by large circuits. [ABSTRACT FROM AUTHOR]

CMOS buffers driving high capacitive loads play an important role in determining the overall performances of present-day complex integrated circuits. Ad hoc optimisation techniques require effective models simple enough to enable the optimisation of multi-million gate circuits. However, due to size and supply voltage reduction, the behaviour of deep-sub micron devices may differ significantly from the conventional one and the classical models and techniques need to be improved or radically modified. In the paper the Authors show how the well-exploited assumption of a linear relationship between the channel width and the current meanly conducted during the switching transient may be incorrect for deep-submicron buffer transistors. As direct consequence, it follows that the common practice of widening the channel width of the MOSFET transistors may not lead to the expected results in terms of buffer output resistance reduction. On these bases, a novel expression to estimate the actual effect of a channel widening on the output resistance of CMOS buffer that agrees with HSPICE circuit simulations within 3% error is presented. [ABSTRACT FROM AUTHOR]

As the number of metal layers and the frequency of VLSI continue to increase, the voltage droop on both the package and vias is becoming more pronounced. This paper analyzes the numerical problem encountered in simulation of power/ground networks together with C4 package and via model. A new preconditioned iterative method and associated acceleration technique are introduced to overcome shortages of previous methods. The new method not only is effective to speedup simulation without loosing any accuracy, but also extends the usage of preconditioned method to general circuit simulation using only a few additional memories due to its MNA formulation. [ABSTRACT FROM AUTHOR]

Early circuit performance estimation and easy-to-apply methods for minimum-delay gate sizing are needed, in order to enhance circuit's performance and to increase designers' productivity. In this paper, we present a practical method to perform gate sizing, taking also into account the contribution of fixed wiring loads. Closed-form bounds are derived and a simple recursive procedure is developed that directly calculate the gate sizes required to achieve minimum delay. The designer, using the proposed method, can easily compare different implementations of the same circuit and explore the energy-delay design space, including in the analysis the effect of interconnect. [ABSTRACT FROM AUTHOR]

Compiler-directed dynamic voltage scaling (DVS) is an effective low-power technique in real-time applications, where compiler inserts voltage scaling points in a real-time application, and supply voltage and clock frequency are adjusted to the relationship between the remaining time and remaining workload at each voltage scaling point. In this paper we present the analytical energy model of proportional dynamic voltage scaling in real-time applications. Using the analytical model, we theoretically prove the optimal configuration of voltage scaling points that minimizes energy consumption. Furthermore, in order to seek the optimal configuration taking into account voltage scaling overhead in the most frequent execution case, we propose a configuration methodology, where a profile-based method constructs the abstract execution pattern of an application, voltage scaling points are inserted into the abstract execution pattern by the optimal configuration without taking into account voltage scaling overhead, and then we can find the optimal configuration considering voltage scaling overhead by deleting some voltage scaling points from the execution pattern. Finally, the remaining points are inserted into the application by compiler. The simulation results show that, when taking into account voltage scaling overhead, the configuration methodology reduces energy consumption efficiently. [ABSTRACT FROM AUTHOR]

LCD displays consume a significant portion of the system energy which is a tight constraint for various battery operated portable devices supporting streaming video. With the advent of new LCD technology like Organic-LEDs, and shrinking feature size of I/O controllers, the LCD bus is going to be the major contributor to this power budget for future devices. The data traveling over LCD buses (the images) have high spectral and temporal correlation which can be exploited for reducing the switching activity on the bus. However, there is lack of enough work for exploiting the cross-channel correlation (CCC) for low energy encodings. In this work, we prove the effectiveness of CCC and propose three new algorithms and associated encoding schemes to save as much as 23% switching activity (average 15.5%) and increase the Covering Potential on average by 20% for the LCD bus. [ABSTRACT FROM AUTHOR]

Data transfers and storage are dominating contributors to the area and power consumption for all modern multimedia applications. A cost-efficient realisation of these systems can be obtained by using high-level memory optimisations. This paper demonstrates that the state-of-the-art memory optimisation techniques only partly can deal with code from real-life multimedia applications. We propose a systematic preprocessing methodology that can be applied on top of the existing work. This opens more opportunities for existing memory optimisation techniques. Our methodology is complemented with a postprocessing step, which eliminates the negative effects of preprocessing and may further improve the code quality [7,10]. Our methodology has been applied on several real-life multimedia applications. Results show a decrease in the number of main memory accesses up to 45.8% compared to applying only state-of-the-art techniques. [ABSTRACT FROM AUTHOR]