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In the last decade, the synthesis of reversible logic circuits has become a trending topic because of its future necessity and importance. Many methods have been studied and proposed, for instance, transformation-based, search-based, cycle-based, ESOP-based and BDD-based methods. Each of them has its limitation related to time processing, ancilla and garbage line, quantum cost. This study develops an algorithm that could synthesize quantum circuits based on mixed-polarity Toffoli gate and a variant of binary decision diagram (BDD) called reduced-ordered-complemented edge-bdd (ROCBDD). It is an optimized method of BDD to reduce nodes in the representation of Boolean functions, which leads to adding more lines and quantum gates in the reversible circuit. First, the differences between synthesis using ROCBDD, the traditional BDD and others methods are introduced. Then, we define a new structure consisting of mixed-polarity Toffoli gates relied on nodes of ROCBDD. An efficient algorithm to match BDD representation to the reversible logic circuit is also mentioned. Finally, the experimental results show that our algorithm has better synthesizing costs than previous BDD-based methods.

Heat dissipation is one of the major problems in the construction of electronic devices. Reversible computing is one of the emerging computing paradigms to overcome heat dissipation problem. One of the nanoscale devices that has low power consumption and can be used to construct digital logic components is quantum-dot cellular automata (QCA). In this paper, the benefits of reversible computing of QCA will be used to propose QCA designs for two main reversible gates, the CNOT and the TOFFOLI gates. The proposed CNOT gate has been used to design QCA for double CNOT gate to show its reversibility, and QCA design for the SWAP circuit that contains 3 CNOT gates. The suggested TOFFOLI gate is utilized to construct QCA for double TOFFOLI gate and a reversible circuit which consists of several reversible gates. The suggested QCA designs for double CNOT, double TOFFOLI and reversible circuits such as SWAP circuit have been proposed by adding cells with certain clocks to the wires that connects the proposed gates. The proposed QCA designs show better cell count, area used in the construction, number of majority gate, wire crossover, and/or clock cycle delay when compared with relevant designs in literature.

Quantum-dot cellular automata (QCA) are the potential alternative to complementary metal–oxide–semiconductor-based technology. Ideally, zero power dissipation can be achieved with the help of reversible computing. In this study, a novel design of a reversible priority encoder based on QCA is proposed. The basic building blocks for the design are Toffoli and BJN gates. The proposed design is verified by the QCA designer simulator. The performance analysis of the reversible priority encoder is performed based on the simulation results. The proposed encoder not only overcomes the problem of the messy code but also declines the amount of heat energy dissipation through reversible logic. The proposed reversible circuit could be a major component in future wireless communication because reversible logic accounts for zero loss of information. The estimation of power consumption by proposed QCA circuits is explored that implies QCA can be an ideal platform to implement reversible circuits. The relationship with recently proposed work is also discussed.

Heuristic algorithms play a significant role in synthesize and optimization of digital circuits based on reversible logic yet suffer with multiple disadvantages for multiqubit functions like scalability, run time and memory space. Synthesis of reversible logic circuit ends up with trade off between number of gates, quantum cost, ancillary inputs and garbage outputs. Research on optimization of quantum cost seems intractable. Therefore post synthesis optimization needs to be done for reduction of quantum cost. Many researchers have proposed exact synthesis approaches in reversible logic but focussed on reduction of number of gates yet quantum cost remains undefined. The main goal of this paper is to propose improved Ant Colony Optimization (ACO) algorithm for quantum cost reduction. The research efforts reported in this paper represent a significant contribution towards synthesis and optimization of high complexity reversible function via swarm intelligence based approach. The improved ACO algorithm provides low quantum cost based toffoli synthesis of reversible logic function without long computation overhead.

We show the design and simulation of organic neuromorphic circuits in a hybrid-computation approach that emulates Boolean and reversible logic gates based on multigate organic electrochemical transistors (OECTs). The organic neuromorphic circuits consist of input, hidden, and output layers that can carry out Boolean operations, including the Exclusive OR (XOR) function, with five or less OECTs. The multigate functionality of OECTs is harnessed to perform the summation function of the neurons. Connection weights of the networks are defined in an unconventional way that depends on the value of the drain-source current of the outputting neuron, which changes according to the input values of the circuit. The Boolean circuits can be cascaded together to build higher level circuits and are demonstrated to form a full adder circuit and the Double Feynman and Toffoli reversible logic gates. Using realistic experimental parameters, the energy per computation is estimated to be ~2.3 nJ for circuit designs with a bias voltage of 0.5 V, with ~230 fJ or less being achievable for lower bias voltages.

All-optical reversible logic gates can play crucial roles in the next generation of all-optical computing systems. In this paper, we will propose and design an all-optical Toffoli gate using photonic crystal-based nonlinear ring resonators. The proposed structure has three input and three output ports. There is a one-by-one mapping between the input and output ports; therefore, the proposed structure is a reversible gate with the maximum time delay about 2 ps and suitable for optical communication applications.

We advocate for a fundamentally different way to perform quantum computation by using three-level qutrits instead of qubits. In particular, we substantially reduce the resource requirements of quantum computations by exploiting a third state for temporary variables (ancilla) in quantum circuits. Past work with qutrits has demonstrated only constant factor improvements, owing to the log2(3) binary-to-ternary compression factor. We present a novel technique using qutrits to achieve a logarithmic runtime decomposition of the Generalized Toffoli gate using no ancilla---an exponential improvement over the best qubit-only equivalent. Our approach features a 70x improvement in total two-qudit gate count over the qubit-only decomposition. This results in improvements for important algorithms for arithmetic and QRAM. Simulation results under realistic noise models indicate over 90% mean reliability (fidelity) for our circuit, versus under 30% for the qubit-only baseline. These results suggest that qutrits offer a promising path toward extending the frontier of quantum computers.

The works that have been devoted to the topic of quantum computer design have been examined. The main issues surrounding the development of a quantum computer are explored. The “up to bottom” concept has been presented and supported as a fundamentally novel way to solve the problem of building a really quantum computer. The technique can be accomplished by using nanotriggers made of two-dimensional materials, such as graphene, to visualise the quantum states of qubits in advance. This refers to the visualisation (materialisation) of all states, including entangled states, which primarily determine the quantum computer's theoretically large mathematical resource. The proposal is for an electronic device block diagram based on “a priory” quantum states of q-bits. It is demonstrated that each realised (visualised) Shor's cell should correspond to an element of the electronic system for the execution of quantum computation procedures. A block containing at least 1010 nanotriggers that act as q-bits in quantum computation and are generated using graphene nanoribbons and controlled by a specific element is included in the device. The latter is a self-organizing quantum dot with two essentially different magnetic states. This quantum dot is made from a compound whose molecules are distinguished by intramolular rearrangement. Nanotriggers are used to create reversible logic gates or blocks. Three triggers are included in each gate to perform logical operations. The offered device is an additional electronic unit implanted in a digital computer that allows the computational process to be implemented in accordance with the requirements of quantum physics.

Since reversible logic has promising applications in domains like low-power design and quantum computing, it is necessary to efficiently design high-performance reversible logic circuits. In this paper, in order to reduce the number of qubits while achieving low quantum cost, the Kronecker functional decision diagram (KFDD) based reversible circuit synthesis method is improved by using two strategies. One is to generate a locally optimal reversible cascade for each of the KFDD nodes by performing transformations on the function represented by a node and using a gate library consisting of NOT, CNOT, Toffoli gates and mixed-polarity Peres gates. This strategy helps reduce the quantum cost and the number of qubits. The other is to map KFDD nodes to their locally optimal reversible cascades level by level via breadth-first traversal of the KFDD. This strategy reduces the number of qubits by using the circuit line labeled by an input variable of the KFDD as the target line of a reversible gate. Comparison results are presented in tabular and graphical forms. Compared to the existing decision diagram based reversible circuit synthesis methods, the proposed method can reduce both the quantum cost and the number of qubits in many cases. Compared to other state-of-the-art synthesis methods for reversible circuits, the proposed method can achieve much lower quantum cost but still incurs a high number of qubits for many functions. However, it can achieve the minimum number of qubits for a few irreversible functions while achieving much lower quantum cost. In addition, the proposed method is very time efficient.

Ternary reversible logic synthesis has started gaining the attention of researchers in recent years because of its distinct advantages over binary reversible logic synthesis. However, the existing methods for the synthesis of ternary reversible logic circuits are applicable only to smaller benchmarks. The present paper proposes an efficient synthesis approach in this regard using ternary decision diagrams (TDDs). A TDD is first generated for the function that is to be synthesized. Then, using a gate library of ternary reversible gates, each TDD node is mapped to a sequence of ternary reversible gates that are finally merged together to form the required netlist. The ternary gate library consists of ternary reversible gates such as multi-polarity ternary Feynman gate and multi-polarity ternary Toffoli gate. To estimate the quantum cost, we propose a decomposition approach to represent a ternary reversible gate in terms of ternary elementary gates. We have carried out experimental evaluation on two types of benchmarks. The first type consists of binary reversible benchmarks converted into ternary reversible benchmarks using a transformation approach. The second type is based on ternary non-reversible benchmarks. We have reported the results for benchmarks with up to 13 inputs with a longest runtime of 7 min, which compares favourably with the existing works in the literature.

In accordance with Moore’s law, the size of complementary metal oxide semiconductor (CMOS)-based devices keep shrinking to augment the density on the chip. This scaling influences the execution of CMOS device due to several constraints like energy dissipation and synchronization of different components of the device. In non-reversible logic gates, power loss is the major concerned. Interest in reversible logic-based circuit design is increased as it offers reduced heat dissipation. Quantum dot cellular automata (QCA) is the possible implementation platform for reversible circuits. An encoder is an important component of memory, for address decoding and encoding. In this article, reversible logic-based architecture of 4 to 2 and 8 to 3 priority encoder is proposed and implemented on QCA platform. To design the encoder circuit, a new QCA layout of Feynman gate and Toffoli gate has been employed. The proposed layout of Feynman gate and Toffoli gate outshines the existing state-of-the-art designs. Quantum cost and circuit cost estimation of those encoder circuits are also performed. QCADesigner tool has been used to validate the performance of the proposed QCA reversible encoders.

Quantum circuits of many qubits are extremely difficult to realize; thus, the number of qubits is an important metric in a quantum circuit design. Further, scalable and reliable quantum circuits are based on fault tolerant implementations of quantum gates such as Clifford+T gates. An efficient quantum circuit saves quantum hardware resources by reducing the number of T gates without substantially increasing the number of qubits. This work presents a T-count optimized quantum circuit for integer multiplication with only $4 \cdot n + 1$4·n+1 qubits and no garbage outputs. The proposed quantum multiplier design reduces the T-count by using a novel quantum conditional adder circuit. Also, where one operand to the conditional adder is zero, the conditional adder is replaced with a Toffoli gate array to further save T gates. Average T-count savings of $46.12$46.12, $47.55$47.55, $62.71$62.71 and 26.30 percent are achieved compared to the recent works by Kotiyal et al., Babu, Lin et al., and Jayashree et al., respectively.

It has always happened in human history that when we thought that things were perfect and nothing better can be done or the thing will suffice us forever some problems unforeseen came up same is the case with CMOS (Complementary Metal Oxide Semiconductors), now researchers are looking beyond CMOS to QCA (Quantum-dot Cellular Automata), a technique which was formulated out of the applications of quantum mechanics. Talking about QCA it is an ingenious technique to fabricate new generation processors and other combinational and sequential circuits. The eye-catching and commercially useful properties of QCA that set it apart from any other technique is its extremely low power consumption in meV, small size going up to nanometer scale, high frequency operation (THz) and elimination of short channel effect. Quantum computing aims to use QCA as the building block for upcoming devices. In this paper, we have improved on the design of the Toffoli gate which is a reversible universal gate. We have successfully improved it on parameters such as cell count by more than 20%, total area by 34%, cell area by 29% and we have maintained latency and complexity as the previous optimal designs even by having less cell count. These improvements will help reduce the size of the chip and reduce power dissipation and thus improve efficiency and be compliant with the ever-increasing computational ability and downscaling requirements.

Toffoli-type reversible gates are analyzed. Peres-type ternary gates are introduced for the first time. Conjunctive, disjunctive, majority, XOR types and hybrid control strategies are disclosed. Barenco-type of quantum models for these cases are developed.

We estimate and analyze the error rates and the resource overheads of the repetition cat qubit approach to universal and fault-tolerant quantum computation. The cat qubits stabilized by two-photon dissipation exhibit an extremely biased noise where the bit-flip error rate is exponentially suppressed with the mean number of photons. In a recent work, we suggested that the remaining phase-flip error channel could be suppressed using a 1D repetition code. Indeed, using only bias-preserving gates on the cat-qubits, it is possible to build a universal set of fault-tolerant logical gates at the level of the repetition cat qubit. In this paper, we perform Monte-Carlo simulations of all the circuits implementing the protected logical gates, using a circuit-level error model. Furthermore, we analyze two different approaches to implement a fault-tolerant Toffoli gate on repetition cat qubits. These numerical simulations indicate that very low logical error rates could be achieved with a reasonable resource overhead, and with parameters that are within the reach of near-term circuit QED experiments., Comment: 16 pages, 13 figures

In this paper, a novel reversible Toffoli gate that uses enhanced logic primitives is proposed. These primitives considered are three-input NAND-NOR-Inverter (NNI) gates and five-input majority-of-five gates. The Toffoli gate design is implemented without any inversion operation, which results in area and delay advantages. Furthermore, we adopt the proposed Toffoli gate as the building block to construct a 4–2 reversible priority encoder. Quantum-dot cellular automata technology was used to validate the proposed design. The experimental results show that the proposed design reduces the delay and the area by 46.15% and 28.71%, respectively, compared with the state-of-the-art design.

Quantum is an emerging technology in future computers. Reversibility is the main advantage of quantum computers. In conventional computers, the computation is irreversible i.e. the input bits are lost once the logic block generates the output and input bits cannot be restored but it can be done in reversible computation because in reversible computation the inputs and outputs have a one-to-one correspondence. Therefore, a reversible gate input could even be uniquely determined from their output which leads to less power consumption. Hence the complexity of the digital circuits can be reduced by using reversible computing. In quantum computer to perform reversible operations, we need to implement the reversible gates using quantum gates. In this paper, we discussed various reversible logic gates like Feynman, Toffoli, R, Peres and TR gates using basic quantum gates like CNOT, Pauli, Swap gates and their implementation using IBM quantum experience.

We usually use Mixed-Polarity Multiple-Control Toffoli (MPMCT) gates to realize large control logic functions for quantum computation. A logic circuit consisting of MPMCT gates needs to be mapped to a quantum computing device that has some physical limitation; (1) we need to decompose MPMCT gates into one or two-qubit gates, and then (2) we need to insert SWAP gates such that all the gates can be performed on Nearest Neighbor Architectures (NNAs). Up to date, the above two processes have been independently studied intensively. This paper points out that we can decrease the total number of the gates in a circuit if the above two processes are considered dynamically as a single step; we propose a method to inserts SWAP gates while decomposing MPMCT gates unlike most of the existing methods. Our additional idea is to consider the effect on the latter part of a circuit carefully by considering the qubit layout when composing an MPMCT gate. We show some experimental results to confirm the effectiveness of our method.

Multiplier is one among the essential hardware blocks in present-day communication and digital signal processing (DSP) systems. The primary advantage of Vedic multiplier is that delay increases slowly with the increase of input bits. Vedic multiplier has supreme advantage when compared with other multipliers over regularity of structures and gate delays. In this paper, the different designs of 8 * 8 bit Vedic multiplier are implemented with different adders, and these multipliers and adders are structured using suitable reversible logic gates, that is, Feynman gate, Peres gate, Toffoli gate, DPG gate and modified Fredkin gate. The different designs of Vedic multipliers designed with the help of different adders, that is, ripple carry adder, carry skip adder and carry select adder, and hence compared their implementation time as well as area required for the circuitry. This comparison will help designers to choose the preferable multiplier according to the application specific demands.

To realize fault-tolerant quantum circuits, one of the important task is to reduce the number of T gates (T-count) when we decompose MPMCT (Mixed Polarity Multiple-Control Toffoli) gates into elementary gates. When we have enough auxiliary qubits, we have an efficient decomposition of a single MPMCT gate. However, it has not been studied intensively how to decompose many MPMCT gates efficiently at the same time. Thus, this paper studies what is an efficient decomposition method when we have many MPMCT gates. We consider two situations to reduce T-count when we need to decompose many MPMCT gates. Then, we propose a heuristic method to reorder MPMCT gates if possible so that we can find the two situations as much as possible. Our preliminary experiments show that our heuristic can reduce T-count drastically.

This paper presents a design of a reversible priority encoder that is an important element for encoding and decoding addresses. Promising nanotechnology, Quantum-dot Cellular Automata (QCA), is a possible platform for implementing reversible circuits. In this paper, a reversible 4 to 2 priority encoder architecture is proposed with low complexity on the QCA platform. In order to implement a reversible encoder circuit, the low-cost design of the Toffoli gate is proposed. Structural analysis using the QCADesigner simulation tool is carried out to evaluate the proposed designs.

Testability dramatically enhances the operating cost in reversible logic circuits as it increases the cost metrics such as gate count, quantum cost, number of wires and garbage output. This increase also affects the utilization of resources, which further enhances overall cost of testing. This paper presents a new design for testability methodology for reversible circuits by exploring the properties of multiple controlled Toffoli and Fredkin gates, to produce online testable circuits at lower cost metrics. The method includes simplification and modification of Toffoli circuits to form parity-preserving Toffoli–Fredkin cascades. The testability in these cascades can be achieved by comparing the parity of inputs and outputs using controlled-NOT gates on an additional wire. Single-point failures in reversible logic circuits are targeted by means of detecting bit faults. In contrast to the existing work, the present model is robust, low cost and has lesser design complexity. Experiments are conducted on a set of benchmark circuits to prove the efficacy of the present work. The results show an average reduction by 15.9 % in gate cost and 11.0 % in total operating cost when compared to the most recent existing work formulated on the same platform.

Reversible logic has 100% fault observability meaning that a fault in any circuit node propagates to the output stage. In other words, reversible circuits are latent-fault-free. Our motivation is to incorporate this unique feature of reversible logic to design CMOS circuits having perfect or 100% Concurrent Error Detection (CED) capability. For this purpose, we propose a new fault preservative reversible gate library called Even Target - Mixed Polarity Multiple Control Toffoli (ET-MPMCT). By using ET-MPMCT, we ensure that the evenness/oddness of applied 1’s at input, is preserved at all levels of a circuit including output level unless there is a faulty node. A single fault always destroys the parity of input at the output. Our design strategy has two steps for a given function: 1) implement the function with our proposed reversible ET-MPMCT gate library; and 2) apply reversible-to-CMOS gate conversion. For the first step, we propose two approaches. For our first approach in step 1, we first need to have a reversible form of the given function if it is irreversible. Then, synthesize the reversible function using Mixed Polarity Multiple Control Toffoli (MPMCT) gate library by conventional reversible logic synthesis techniques. Finally, the synthesized circuit is converted to ET-MPMCT constructed circuit which is fault preservative. Our second approach, is an ESOP - Exclusive Sum of Products - based synthesis approach modified for our proposed fault preservative ET-MPMCT gate library. It does work with both irreversible and reversible functions. We synthesize our circuits with both approaches in step 1 and choose the circuit with lower number of reversible gates to be fed to step 2 of our design strategy. In second step of our design strategy, we convert our fault preservative reversible circuits into their CMOS counterparts. The performance of our designs is compared with other CED schemes in the literature in terms of area, power consumption, delay and detection rate. Simulations are done with Cadence Genus tool using TSMC 40nm technology. Clearly, results are in favor of our proposed techniques.

Reversible logic is a circuit which has the ability to reduce the power dissipation. This type of logic circuit is used for the process of running the system both forward and backward.One of the main advantages of using any reversible logic is to get back the original data and to reduce the garbage output. Logic synthesis based on the Kronecker Functional Decision Diagram (KFDD) are generated for different reversible cascade methods both complemented and uncomplemented edge by using different reversible gates such as the CNOT (Controlled NOT), NOT, Toffoli gates, Peres gates, etc., and implemented in a quantum processor. In order to reduce the qubits which in turn reduces the quantum cost, it is implemented using reversible logic synthesis in KFDD method.The proposed method shows the implementation of these reversible circuits in an IBM quantum computer to find the probabilities, as it gives less quantum cost and also consumes less time when compared to other decision diagram. Reversible logic finds a wide range of applications in quantum computing and also in areas which deals with the low power design.This paper presents the implementation of KFDD using quantum circuits in IBM Quantum (IBM-Q) processor using different reversible logics and the output is discussed.

Increasing device density and reducing energy consumption are challenging issues in integrated nanoscale circuits. Reversible logic in quantum-dot cellular automata (QCA) nanotechnology is emerging as a promising candidate to overcome these issues and to introduce new computation paradigms with unique features like nanoscale feature size and ultra-low power dissipation. For the first time, QCA cell-based designs of reversible Feynman, Toffoli, Fredkin, and Peres gates are presented in this paper. These elementary gates are usually used in the synthesis of reversible circuits. The proposed layouts utilize electrostatic interactions between cells within QCA configurations to perform desired functions. All the robust designs are evaluated in terms of hardware complexity and power dissipation using QCADesigner and QCAPro simulation tools. The efficient QCA layouts of proposed gates have notable improvements as compared to the existing ones in terms of gate delay, cell count, area occupation, quantum cost, leakage energy, and switching energy. As a result, the proposed elementary gates via QCA cell level-based design are good candidates for building and developing high-level nanoelectronic reversible circuits.

The quantum of power consumption in wireless sensor nodes plays a vital role in power management since more number of functional elements are integrated in a smaller space and operated at very high frequencies. In addition, the variations in the power consumption pave the way for power analysis attacks in which the attacker gains control of the secret parameters involved in the cryptographic implementation embedded in the wireless sensor nodes. Hence, a strong countermeasure is required to provide adequate security in these systems. Traditional digital logic gates are used to build the circuits in wireless sensor nodes and the primary reason for its power consumption is the absence of reversibility property in those gates. These irreversible logic gates consume power as heat due to the loss of per bit information. In order to minimize the power consumption and in turn to circumvent the issues related to power analysis attacks, reversible logic gates can be used in wireless sensor nodes. This shifts the focus from power-hungry irreversible gates to potentially powerful circuits based on controllable quantum systems. Reversible logic gates theoretically consume zero power and have accurate quantum circuit model for practical realization such as quantum computers and implementations based on quantum dot cellular automata. One of the key components in wireless sensor nodes is the cryptographic algorithm implementation which is used to secure the information collected by the sensor nodes. In this work, a novel reversible gate design of 128-bit Advanced Encryption Standard (AES) cryptographic algorithm is presented. The complete structure of AES algorithm is designed by using combinational logic circuits and further they are mapped to reversible logic circuits. The proposed architectures make use of Toffoli family of reversible gates. The performance metrics such as gate count and quantum cost of the proposed designs are rigorously analyzed with respect to the existing designs and are properly tabulated. Our proposed reversible design of AES algorithm shows considerable improvements in the performance metrics when compared to existing designs.

Unlike conventional CMOS circuits, reversible circuits do not have latent faults, so faults occurring in internal circuit nodes always result in an error at the output. This is a unique feature for online or concurrent fault tolerance and the main motivation of this paper with an aim of achieving highly efficient fault-tolerant CMOS logic circuits. For this purpose, we first implement fault-tolerant reversible circuits. We develop two techniques to make a reversible circuit fault-tolerant by using multiple-control Toffoli gates. The first technique is based on single parity preserving and offers error detection for odd number of errors at the output. The second technique is constructed on Hamming codes, which results in circuits detecting any number of errors unless the number of errors at the output is the order of $d$ or correcting $(d-1)/2$ bit errors, where $d$ is the minimum Hamming distance between any pair of bit patterns. We select $d=3$ in this paper. We also claim that 100% error detection is possible with conservative reversible gates, such as a Fredkin gate. For this purpose, we develop a greedy synthesis algorithm that implements an arbitrary reversible function with multiple-control Fredkin gates. As the next step, we utilize the proposed reversible circuits with conventional CMOS gates. This certainly approves the practical use of the proposed techniques. The effectiveness of our techniques is demonstrated on benchmark circuits, implemented by both reversible and CMOS gates, in terms of fault tolerance performances and area costs. Comparisons with the related studies in the literature as well as with dual-modular redundancy and triple-modular redundancy-based circuits clearly favor the proposed designs.

In this paper, the problem of Boolean function's representation by the reversible circuits constructed of the Toffoli gates is considered. Interest in this problem is connected with actual studies of the possibility for realization of "cold" computations. It means that when performing such computations, there is no heat dissipation. In general, reversible circuits realize reversible functions. Therefore, Toffoli-Fredkin's method for representation of the Boolean function by the reversible function is used. In work, an algorithm for finding the minimal representation of the Boolean function in a class of the reversible circuits, which are constructed from Toffoli elements is described. The algorithm uses the polynomial normal forms or exclusive-or sum-of-products expressions (ESOPs) of the Boolean function in the operator representation and the problem of finding the minimal representation of the Boolean function in the certain class of operator bundles. The chosen class of operator bundles corresponds to a class of the extended polarized Zhegalkin polynomials, which includes a well-known class of the polarized Zhegalkin polynomials or Reed-Muller forms. In conclusion, the computational results of the algorithm for minimizing the Boolean functions in the class of reversible circuits are given.

Reversible logic is expanding grounds with its applicability to various upcoming technologies and quantum computation. Numerous reversible gates has also been proposed for designing logic circuits apart of basic quantum controlled Toffoli and Fredkin gates. A comparative study and analysis of a range of reversible gates from the literature is presented in this paper to obtain an optimal solution for designing these circuits. The gates are synthesized and implemented to obtain equivalent quantum circuits and operating cost in terms of number of inputs, gate cost, quantum cost, garbage output and ancilla input. The comparison is done at two subsequent levels i.e. gates structural level and circuit design level, providing a better solution for designing logic circuits. It is calculated that, basic gates are 50% efficient at gate level and 33% at design level analysis in terms of gate cost, as compared to the most efficient gates proposed in the literature.

Nanotechnologies, remarkably Quantum-dot Cellular Automata (QCA), offer an attractive perspective for future computing technologies. In this paper, QCA is investigated as an implementation method for designing area and power efficient reversible logic gates. The proposed designs achieve superior performance by incorporating a compact 2-input XOR gate. The proposed design for Feynman, Toffoli, and Fredkin gates demonstrates 28.12, 24.4, and 7% reduction in cell count and utilizes 46, 24.4, and 7.6% less area, respectively over previous best designs. Regarding the cell count (area cover) that of the proposed Peres gate and Double Feynman gate are 44.32% (21.5%) and 12% (25%), respectively less than the most compact previous designs. Further, the delay of Fredkin and Toffoli gates is 0.75 clock cycles, which is equal to the delay of the previous best designs. While the Feynman and Double Feynman gates achieve a delay of 0.5 clock cycles, equal to the least delay previous one. Energy analysis confirms that the average energy dissipation of the developed Feynman, Toffoli, and Fredkin gates is 30.80, 18.08, and 4.3% (for 1.0 E k energy level), respectively less compared to best reported designs. This emphasizes the beneficial role of using proposed reversible gates to design complex and power efficient QCA circuits. The QCADesigner tool is used to validate the layout of the proposed designs, and the QCAPro tool is used to evaluate the energy dissipation.

This paper introduces a cryptanalysis of image encryption techniques that are using chaotic scrambling and logic gates/circuits. Chaotic scrambling, as well as general permutations are considered together with reversible and irreversible gates, including XOR, Toffoli and Fredkin gates. We also investigate ciphers based on chaotic permutations and balanced logic circuits. Except for the implementation of Fredkin’s gate, these ciphers are insecure against chosen-plaintext attacks, no matter whether a permutation is applied globally on the image or via a block-by-block basis. We introduce a new cipher based on chaotic permutations, logic circuits and randomized Fourier-type transforms. The strength of the new cipher is statistically verified with standard statistical encryption measures.

The CMOS technology has been plagued by several problems in past one decade. The ever increasing power dissipation is the major problem in CMOS circuits and systems. The reversible computing has potential to overcome this problem and reversible logic circuits serve as the backbone in quantum computing. The reversible computing also offers fault diagnostic features. Quantum-dot cellular automata (QCA) nanotechnology owing to its unique features like very high operating frequency, extremely low power dissipation, and nanoscale feature size is emerging as a promising candidate to replace CMOS technology. This paper presents design and performance analysis of area efficient QCA based Feynman, Toffoli, and Fredkin universal reversible logic gates. The proposed designs of QCA reversible Feynman, Toffoli, and Fredkin reversible gates utilize 39.62, 21.05, and 24.74% less number of QCA cells as compared to previous best designs. The rectangular layout area of proposed QCA based Feynman, Toffoli, and Fredkin gates are 52, 28.10, and 40.23%, respectively less than previous best designs. The optimized designs are realized employing 5-input majority gates to make proposed designs more compact and area efficient. The major advantage is that the optimized layouts of reversible gates did not utilize any rotated, translated QCA cells, and offer single layer accessibility to their inputs and outputs. The proposed efficient layouts did not employ any coplanar or multi-layer wire crossovers. The energy dissipation results have been computed for proposed area efficient reversible gates and thermal layouts are generated using accurate QCAPro power estimator tool. The functionality of presented designs has been performed in QCADesigner version 2.0.3 tool.

Conventional digital circuits consume a considerable amount of energy. If bits of information remain during logical operations, power consumption decreases considerably because the data bits in reversible computations are not lost. The types of reversible gate used in quantum computations are quantum-dot cellular automata (QCA), nuclear magnetic resonance, and optical computations. QCA systems offer low power consumption, high density, section regularity and support new devices designed for nanotechnology. A QCA-based reversible gate has minimal delay, complexity and considering the potential quality of a QCA pipeline, computes at maximum speed. The present study designed a novel $$3 \times 3$$3×3 reversible gate that is universal and testable. A reversible logic gate is also designed based on the majority gate in the QCA and as a QCA reversible (QR) gate. A new 8-bit reversible full adder/subtractor based on the QR gate in QCA with a minimum number of cells and area combines both designs for implementation of a reversible full adder/subtractor in QCA. The performance of these gates was compared with testable Fredkin and Toffoli gates and improved performance of logic functions in terms of complexity and delay over those of the Fredkin and Toffoli gates.

Quantum resource analysis is crucial for designing quantum circuits as well as assessing the viability of arbitrary (error-corrected) quantum computations. To this end, we introduce QUANTIFY, which is an open-source framework for the quantitative analysis of quantum circuits. It is based on Google Cirq and is developed with Clifford+T circuits in mind, and it includes the necessary methods to handle Toffoli+H and more generalised controlled quantum gates, too. Key features of QUANTIFY include: (1) analysis and optimisation methods which are compatible with the surface code, (2) choice between different automated (mixed polarity) Toffoli gate decompositions, (3) semi-automatic quantum circuit rewriting and quantum gate insertion methods that take into account known gate commutation rules, and (4) novel optimiser types that can be combined with different verification methods (e.g. truth table or circuit invariants like number of wires). For benchmarking purposes QUANTIFY includes quantum memory and quantum arithmetic circuits. Experimental results show that the framework's performance scales to circuits with thousands of qubits., Comment: accepted at IEEE Computer Society Annual Symposium on VLSI 2020: Quantum Computing Workshop (QCW) Source code at https://github.com/quantumresource/quantify

Reversible logic is a very significant exposure for low-power consumption and faster computation in recent research areas. The aim of designing a reversible sorting circuit is to reduce power consumption and reliable communication. Two efficient sorting circuits are presented in this paper which can sort binary numbers in descending order. The proposed circuits includes 3 or 4 inputs where each input consists of 3 bits. Fredkin and Toffoli gates have been used to design the comparator. Fredkin gate has also been used for the proposed switch which generates result bit according to the comparator’s input. The proposed circuit needs 102 primary reversible gates for sorting 3 inputs and 170 gates for 4 inputs, 195 garbage outputs for 3 inputs and 325 garbage outputs for 4 inputs, 510 quantum cost for 3 inputs and 850 quantum cost for 4 inputs and (150α + 246β + 96γ) hardware complexity for 3 inputs and (250 + 410β + 160γ) hardware complexity for 4 inputs. In this modern era, sorting is used in many fields like pulse generation, counting and searching operations. Many research have been done regarding reversible sequential and combinational circuits but reversible sorting circuit is still an unexplored area, so this may be one of the pioneering works in this field.

There is an ever increasing demand for low-power and high-speed designs due to the emergence of portable, handheld gadgets which run on batteries. More and more research works in VLSI are concentrated on different methodologies to reduce the power consumption of a system and also increase its throughput. Multiplication is an important operation in almost all computations. Design of multipliers with low power utilization and increased throughput will lead to systems with reduced power usage and high speed. Vedic Multipliers based on the Urdhava Tiryakbhyam sutra delivers results faster than the customary methods. Reversible logic gates when used in a circuit lead to little or no power dissipation. The paper proposes a system which employs Vedic multipliers and reversible gates to perform multiplications with increased throughput and using very little power. The designed system is optimized by combining the low power strategy of reversible logic and the high speed calculation of Urdhava Tiryakbhyam Vedic multiplier.

In this paper, three optical reversible logic gates including Toffoli, Peres and Fredkin gates utilizing graphene-silicon slot waveguides are presented and investigated. The introduced Toffoli, Peres and Fredkin gates are consisting of cascaded Mach-Zehnder interferometers and multimode interference couplers. In each Mach-Zehnder interferometer, graphene-silicon slot waveguides are designed to be phase shifters. As the chemical potential varies, a big change in the real part of the effective refractive index of our designed graphene-silicon slot waveguide would be formed, and thus relatively compact and broadband Toffoli, Peres and Fredkin gates are achieved. At 1550 nm, when the chemical potential varies from 0.60 to 0.90 eV, 3-dB bandwidth of 20.84 GHz,Vπ Lπ of 40.46 Vμ m and 0.40 pJ/bit energy consumption can be obtained for the designed graphene-silicon slot waveguide with 5-nm-thick ZrO2spacers. For the corresponding Toffoli, Peres and Fredkin gates, the minimum extinction ratios are 24.19, 24.60 and 18.63 dB and the maximum crosstalks are -32.56, -27.81, and -20.80 dB, respectively.

Recently, reversible logic gate provides an alternative to overcome many problems in computing technologies as their zero-power dissipation under ideal condition and it is emerged as a promising computing paradigm with applications in low-power CMOS, quantum computing, optical computing and nanotechnology. Optical logic gates become potential component to work at macroscopic (light pulses carry information), or quantum (single photon carries information) levels with high efficiency. This paper proposes a low-power design of all-optical programmable Binary-to-Gray or Gray-to-Binary code converter using reversible new multiplexer in all-optical domain. By Matlab-7.0 the simulation results verify the functionality of both the new multiplexer and programmable code converter as well as reversibility.

In WDM communication based networks the processors have to deal with large number of data. It is seen that the data loss becomes significant when the conventional logic gates have been used as the building block of the processors. The reversible logic gates already have established its utility due to its low power consumption and less hardware complexity. In case of reversible logic gate, inputs are directly mapped to outputs after performing some logic functions. As the inputs of the reversible gate can be uniquely recovered from the outputs, power loss is ideally zero. Toffoli gate, invented by Tommaso Toffoli is one of the most common universal reversible logic gates. It is a three-input-three-output reversible logic gate. In this article, authors have proposed a new technique of designing optical Toffoli gate, and subsequently propose a method of developing an optical full adder with the help of Toffoli gates. For this purpose the authors have deployed the polarization switching characteristic of semiconductor optical amplifier (SOA). The authors have exploited frequency encoded data due to the inherent identity. The proposed optical frequency encoded full adder will be a key component of an optical reversible Arithmetic Logic Unit (ALU), or any other reversible optical computing. Simulation results of the Toffoli gate based on theoretical model PSW show the feasibility of the of the proposed scheme.

Reversible logic gates are capable of designing lossless digital systems, which have received a great deal of attention in photonic integrated circuits due to their advantages, such as less heat generation and low power dissipation. In this paper, all-optical reversible Feynman and Toffoli logic gates are designed for optical computing devices and low-power integrated circuits. Proposed designs of all-optical reversible logic gates are implemented with two-dimensional photonic crystal waveguides without using any nonlinear material. The finite-difference time-domain method is used to simulate and verify the proposed design, and it is operated at a wavelength of 1550 nm. The structure of all-optical reversible logic gates requires much less area, and Feynman logic gates offer a contrast ratio (CR) of 12.4 dB, transmittance of 0.96, and less insertion loss of − 0.015 d B , while Toffoli logic gates offer a CR of 32.5 dB, transmittance of 0.9, and less insertion loss of − 0.04 d B .

Compared with the idea of universal quantum computation, a direct synthesis of a multiqubit logic gate can greatly improve the efficiency of quantum information processing tasks. Here we propose an efficient scheme to implement a three-qubit controlled-not (Toffoli) gate of neutral atoms based on unconventional Rydberg pumping. By adjusting the strengths of Rabi frequencies of driving fields, the Toffoli gate can be achieved within one step, which is also insensitive to the fluctuation of the Rydberg-Rydberg interaction. Considering different atom alignments, we can obtain a high-fidelity Toffoli gate at the same operation time $\sim 7~\mu s$. In addition, our scheme can be further extended to the four-qubit case without altering the operating time., Comment: To be published in Optics Express

Demand of Very Large Scale Integration (VLSI) circuits with very high speed and low power are increased due to communication system's transmission speed increase. During computation, heat is dissipated by a traditional binary logic or logic gates. There will be one or more input and only one output in irreversible gates. Input cannot be reconstructed using those outputs. In low power VLSI, reversible logic is commonly preferred in recent days. Information is not lost in reversible gates and back computation is possible in reversible circuits with reduced power dissipation. Reversible full adder circuits are implemented in the previous work to optimize the design and speed of the circuits. Reversible logic gates like TSG, Peres, Feynman, Toffoli, Fredkin are mostly used for designing reversible circuits. However it does not produced a satisfactory result in terms of static power dissipation. In this proposed research work, reversible logic is implemented in the full adder of MOS Current-Mode Logic (MCML) to achieve high speed circuit design with reduced power consumption. In VLSI circuits, reliable performance and high speed operation is exhibited by a MCML when compared with CMOS logic family. Area and better power consumption can be produced implementing reversible logic in full adder of MCML. Minimum garbage output and constant inputs are used in reversible full adder. The experimental results shows that the proposed designed circuit achieves better performance compared with the existing reversible logic circuits such as Feynman gate based FA, Peres gate based FA, TSG based FA in terms of average power, static power dissipation, static current and area.

In this paper, improved reversible comparator designs are investigated using Multiple Control Toffoli(MCT) gates, improving Quantum Cost(QC) and also Nearest Neighbor Cost(NNC) metrics of circuits. The proposed designs are compared with recent works and found to be efficient in terms of cost by making these nearest neighbor compliant using Swap gate insertions.

Quantum-dot cellular automata (QCA) is a developing nanotechnology, which seems to be a good candidate to replace the conventional complementary metal-oxide-semiconductor (CMOS) technology. The QCA has the advantages of very low power dissipation, faster switching speed, and extremely low circuit area, which can be used in designing nanoscale reversible circuits. In this paper, the new efficient QCA implementations of the basic reversible Gates such as: CNOT, Toffoli, Feynman, Double Feynman, Fredkin, Peres, MCL, and R Gates are presented based on the straight interactions between the QCA cells. Also, the designs of 4-Bit reversible parity checker and 3-bit reversible binary to Grey converter are introduced using these optimized reversible Gates. The proposed layouts are designed and simulated using QCADesigner software. In comparison with previous QCA designs, the proposed layouts are implemented with the minimum area, minimum number of cells, and minimum delay without any wire-crossing techniques. Also, in comparison with the CMOS technology, the proposed layouts are more efficient in terms of the area and power. Therefore, our designs can be used to realize quantum computation in ultralow power computer communication.

As billions of transistors are being placed on a few square millimeters of silicon, power dissipation is becoming a more crucial factor to be tackled for high performance computing. Reversible circuit synthesis has been considered as a promising direction for low power design due to its information lossless behavior. In addition, it forms the basis for quantum computing. However, synthesis of reversible circuits cannot be achieved with the classical approaches for irreversible logic due to the additional imposed constraints, consequently, neither fan-out nor feedback are allowed. Binary Decision Diagrams (BDDs) have been proposed as a compact data structure to represent a boolean function. They have been exploited to synthesize reversible circuits through proper mapping of each BDD’s node into a cascade of reversible Toffoli gates. Nevertheless, reordering of BDD’s nodes before circuit synthesis significantly impacts the overall cost of the synthesized circuit. In this paper, we present a comparative study for BDD reordering algorithms in terms of the cost of the generated reversible circuit. The studied algorithms include greedy, dynamic programming, and heuristic based approaches. The cost metric includes the number of lines, gate count, and quantum cost. Experimental results show that meta heuristic-based BDD reordering algorithms outperform other algorithms in terms of the overall synthesized circuit cost with slightly additional runtime. Thereafter, we conclude with a proposal for a new framework for reversible logic synthesis.

A new enhanced reversible logic circuit synthesis method was developed using reversible gates that include NOT, CNOT (Feynman), Toffoli, Fredkin, Swap, and Peres gates. The synthesis method was done using newly developed genetic programming. Usually previous synthesis methods that uses genetic algorithms or other similar evolutionary algorithms suffers a problem known as blotting which is a sudden uncontrolled growth of an individual (circuit), which may render the synthesis inefficient because of memory utilization, making the algorithm difficult to continue running and eventually stack in a local minima, there for an optimized reversible circuit may not be generated. In this method the algorithm used was blot free, the blotting was carefully controlled by fixing a suitable length and size of the individuals in the population. Following this approach, the cost of generating circuits was greatly reduced giving the algorithm to reach the end of the last designated generation to give out optimal or near optimal results. The results of the circuits generated using this method were compared with some of the results already in the literature, and in many cases, our results appeared to be better in terms of gate count and quantum cost metrics.

Primary purpose behind this work is to develop a type of quantum gate C2(iZ)/C2(-iZ) derived from unitary quantum gate C2(-I) by finding its 2nd root. This newly introduced gate is nearest-neighbor compliant with a unit quantum cost. The main objective in deriving this quantum gate C2(iZ)/C2(-iZ) is to generate low cost MCT gates which eventually produces cost optimized NNC free reversible circuits. For systematic mapping and a fair comparison with prior works, we formed a quantum gate library that includes CNOT, NOT, H, CH, C2(-I) and C2(iZ)/C2(-iZ) gates. A mapping algorithm including the complete gate library is proposed alongwith necessary mathematical proofs. Using the gate library, we show significant cost savings is achievable over the state-of-the-art approaches, when mapping n-control Toffoli gates and chosen benchmark functions.

Reversible logic gates show potential roles in communication technology, and it has a wide area of applicability such as in sequential and combinational circuit of optical computing, optical signal processing, multi-valued logic operations, etc. because of its advantageous aspects of data-recovering capabilities, low power consumption, least power dissipation, faster speed of processing, less hardware complexity, etc. In a reversible logic gate not only the outputs can be determined from the inputs, but also the inputs can be uniquely recovered from the outputs. In this article an alternative approach has been made to develop three-input–output Fredkin and Toffoli gates using the frequency conversion property of semiconductor optical amplifier (SOA) and frequency-based beam routing by optical multiplexers and demultiplexers. Simulation results show the feasibility of our proposed scheme.

Reversible logic is one of the basis of future computing system that promises zero energy dissipation. It has applications in various fields such as Low power VLSI, Fault tolerant designs, quantum computing, nanotechnology, DN A computing, optical computing, cryptography and informatics. To make reversible logic circuits reliable, they must incorporate fault tolerance attribute. In this paper, we propose a new parity preserving reversible logic gate. We have proposed two optimized design of a self checking two rail checker circuit based on proposed parity preserving reversible logic gate in terms of number of gates and critical path delay. The proposed design achieves less critical delay and gates compared to the existing designs available in literature.  Index Terms—Critical delay, fault tolerant, parity- preserving reversible gates, two rail checker.