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The proposition of integrating the 2-D materials and ferroelectric negative-capacitance MOSFETs (NCFETs) was expected to have excellent steep slope I – V characteristics due to the combined advantages of both ultrathin body channel material and negative-capacitance effect. Recent experiments demonstrated the excellent steep slope features of 2-D material NCFETs. Therefore, it was important to understand the device physics of this characteristic, its performance projection, and the benchmark with NCFETs based on conventional Group IV materials. In this article, we conducted a computational study of 2-D material NCFETs based on MoS2 under the nonequilibrium Green’s function (NEGF)-Poisson self-consistent scheme with free-Gibbs energy calculation to judge the operating path in polarization–electric field (P–E) relation. Monolayer MoS2 (1L-MoS2) was chosen as channel material while various thickness of ultrathin body silicon (UTB-Si) for benchmark purpose. The results showed an excellent average subthreshold slope (SS) of ~25 mV/dec in 1L-MoS2 NCFETs compared to ~32 mV/dec of the UTB-Si counterparts. It was found that the steep-slope features in 1L-MoS2 NCFETs could be attributed to the more optimized capacitance matching in 1L-MoS2 NCFETs and tunneling currents at the subthreshold region. [ABSTRACT FROM AUTHOR]

Ferroelectric (FE) negative capacitance (NC) MOSFETs is investigated in depth with a full real-space atomic simulator. For the first time, Gibbs-free energy of the whole atomic system is employed to determine the appropriate operation region in polarization-electric-field (${P}$ – ${E}$) path of the FE layer for FE MOSFETs. With different FE thicknesses, the operation path of the FE layer in MOS structures can be hysteresis or hysteresis-free. For MOSFET structures, the operation path of FE layer will vary with different FE materials. With proper device parameters, the NC effect in FE layer can be obtained with minimum Gibbs-free energy of the MOS and MOSFET structures. The body factor, ${dV}_{G}/{d} \Psi _{S}$ , is obtained with the real-space structure to reflect the influence of the FE layer and optimize the device performance. With the FE layer of the same thickness, the NC-FET with longer channel has a larger body factor which causes the tradeoff between low tunneling current and small body factor. This tradeoff makes it difficult to improve the subthreshold swing by changing the gate length. In addition, the effect of floating metal layer between FE and SiO2 layers in NC-FETs is studied in detail with atomic level real-space analysis for different gate lengths. The metal layer has a stronger influence on the electric characteristics of NC-FETs with longer channel. [ABSTRACT FROM AUTHOR]

Integration of InxGa1–xAs n-MOSFETs and SiyGe1–y p-MOSFETs could be a key to realize future low-power and high-speed logic circuits. In this paper, monolithic integration of InAs n-MOSFETs and Ge p-MOSFETs on a Si substrate is reported. To address the challenge of integrating materials with large lattice mismatch (InAs and Ge on Si substrate), a sub-120-nm GaSb-on-GaAs buffer on a germanium-on-insulator (GeOI) starting substrate is employed. The strain resulting from the 7.78% lattice mismatch between the GaSb and GaAs layers is mainly relaxed via interfacial misfits at the GaSb/GaAs interface, enabling significant reduction in the buffer thickness. For device fabrication, a self-aligned gate last process flow with Si-CMOS-compatible modules is used. To realize raised source-drain device architecture, a combination of dry and digital etch processes is developed to etch InAs and Ge cap layers. Devices with channel thicknesses less than 5 nm and channel lengths less than 200 nm are realized for both n- and p-MOSFETs, with promising electrical characteristics. [ABSTRACT FROM PUBLISHER]

An improved simulation scheme for investigating the performance of nanoscale FETs is developed in this paper. The total current of the MOSFET consists of two main components: thermionic current above the top of barrier of the channel calculated by ballistic approach and tunneling current computed by Wentzel–Kramer–Brillouoin approximation based on a full-complex-band structure. Furthermore, to get atomic-position-based potential profile in the nanoscale device, we self-consistently solve atomic charges and potentials in the real space along and transverse in the transport direction. The device performance calculated with this model shows excellent agreement with that obtained using non-equilibrium Green’s function solver (full quantum mechanism) but by using only one-tenth of the simulation resource. Moreover, special characteristics of insulating materials integrated with advanced device structures can also be incorporated in this Poisson solver. An example based on the negative capacitance MOSFET is examined with this model, and it shows significantly improved performance than conventional MOSFET. [ABSTRACT FROM PUBLISHER]

We investigated the effect of body thickness on the electrical performance of GaSb double-gate ultrathin-body (DG-UTB) MOSFET by examining the band structure of the 12- ( $\sim 2$ nm), 24- ( $\sim 4$ nm), 36- ( $\sim 6$ nm), and 48- ( $\sim 8$ nm) atomic-layer (AL) thick GaSb. Two different surface orientations, namely, (100) and (111), were studied. sp3d5s* tight-binding model is used to calculate the band structures of GaSb MOSFET. Ballistic transport was studied using the semiclassical top-of-barrier model with applied self-consistent real-space potential across the body. First, we found that for (100) surface orientation, GaSb DG-UTB FET with body thickness of 24 ALs offered relatively larger ON-state current for various gate dielectric materials studied. However, for (111) surface orientation, 12 ALs GaSb DG-UTB FET showed the best performance due to its reasonably higher injection velocity and larger electron density. Furthermore, for the FET with a body thickness of 48 ALs and HfO2 dielectric, it was observed that the charge occupations shift toward the surface, unlike the cases of FETs with thinner body, leading to the formation of inversion charge on the surface. Finally, we compared the ON-state current of GaSb DG-UTB FET with different channel surface orientations and found that (100) surface generally outperforms (111) surface in terms of ON-state current. [ABSTRACT FROM AUTHOR]