Search

The proposition of integrating the 2-D materials and ferroelectric negative-capacitance MOSFETs (NCFETs) was expected to have excellent steep slope I – V characteristics due to the combined advantages of both ultrathin body channel material and negative-capacitance effect. Recent experiments demonstrated the excellent steep slope features of 2-D material NCFETs. Therefore, it was important to understand the device physics of this characteristic, its performance projection, and the benchmark with NCFETs based on conventional Group IV materials. In this article, we conducted a computational study of 2-D material NCFETs based on MoS2 under the nonequilibrium Green’s function (NEGF)-Poisson self-consistent scheme with free-Gibbs energy calculation to judge the operating path in polarization–electric field (P–E) relation. Monolayer MoS2 (1L-MoS2) was chosen as channel material while various thickness of ultrathin body silicon (UTB-Si) for benchmark purpose. The results showed an excellent average subthreshold slope (SS) of ~25 mV/dec in 1L-MoS2 NCFETs compared to ~32 mV/dec of the UTB-Si counterparts. It was found that the steep-slope features in 1L-MoS2 NCFETs could be attributed to the more optimized capacitance matching in 1L-MoS2 NCFETs and tunneling currents at the subthreshold region. [ABSTRACT FROM AUTHOR]

Integration of InxGa1–xAs n-MOSFETs and SiyGe1–y p-MOSFETs could be a key to realize future low-power and high-speed logic circuits. In this paper, monolithic integration of InAs n-MOSFETs and Ge p-MOSFETs on a Si substrate is reported. To address the challenge of integrating materials with large lattice mismatch (InAs and Ge on Si substrate), a sub-120-nm GaSb-on-GaAs buffer on a germanium-on-insulator (GeOI) starting substrate is employed. The strain resulting from the 7.78% lattice mismatch between the GaSb and GaAs layers is mainly relaxed via interfacial misfits at the GaSb/GaAs interface, enabling significant reduction in the buffer thickness. For device fabrication, a self-aligned gate last process flow with Si-CMOS-compatible modules is used. To realize raised source-drain device architecture, a combination of dry and digital etch processes is developed to etch InAs and Ge cap layers. Devices with channel thicknesses less than 5 nm and channel lengths less than 200 nm are realized for both n- and p-MOSFETs, with promising electrical characteristics. [ABSTRACT FROM PUBLISHER]

Black phosphorus (BP) has been proposed as the channel material in the next generation ultrascaled CMOS devices. In order to gain insight into the current characteristics in 2-D layered materials, the current distribution of a few-layer BP Schottky barrier FET is investigated via state-of-the-art quantum device simulations. Approximately 40% of the total current was found to be concentrated in the top layer when the device was switched on, with the remaining current distributed among the other layers. In comparison, ~80% of the current concentrated below the surface in a Si device with the same structure. These features are related to the strength of the intra/interlayer interaction in few-layer BP and are unique to 2-D layered materials. Moreover, the current distribution and the device performance were different for the top- and side-contacted devices, with the side-contacted devices yielding lower resistance compared with the top-contacted devices. [ABSTRACT FROM PUBLISHER]

An improved simulation scheme for investigating the performance of nanoscale FETs is developed in this paper. The total current of the MOSFET consists of two main components: thermionic current above the top of barrier of the channel calculated by ballistic approach and tunneling current computed by Wentzel–Kramer–Brillouoin approximation based on a full-complex-band structure. Furthermore, to get atomic-position-based potential profile in the nanoscale device, we self-consistently solve atomic charges and potentials in the real space along and transverse in the transport direction. The device performance calculated with this model shows excellent agreement with that obtained using non-equilibrium Green’s function solver (full quantum mechanism) but by using only one-tenth of the simulation resource. Moreover, special characteristics of insulating materials integrated with advanced device structures can also be incorporated in this Poisson solver. An example based on the negative capacitance MOSFET is examined with this model, and it shows significantly improved performance than conventional MOSFET. [ABSTRACT FROM PUBLISHER]