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Low-frequency noise is a critical characteristic of transistors, but there are only a few experimental works on the noise in printed electronics. In this work, we characterize the low-frequency noise of inkjet-printed electrolyte-gated thin-film transistors (EGTs) with indium-oxide semiconductors. We confirm that the carrier number fluctuation with correlated mobility fluctuation is the dominating noise generation mechanism. Also, we present the benchmark analysis on the noise level of various thin-film technologies. Notably, the extracted value of trap density near the insulator-channel interface is high, indicating an inferior quality of solution-processed and inkjet-printed thin-films. However, because of electrolyte-gating, the large areal gate capacitance compensates the negative effect of the high trap density, effectively reducing the flat-band voltage noise. As a result, the normalized drain current noise is considerably lower than solution-processed transistors and comparable with sputtered inorganic transistors with dielectric gating. This renders the electrolyte-gating approach useful in reducing the noise for printed/solution-based transistors, suitable for low-noise applications. [ABSTRACT FROM AUTHOR]

Unlike nanoscale silicon transistors, printed thin-film transistors usually rely on micrometer size channel lengths. The device dimensions, the morphology of the channel material, and the interface properties strongly influence important device parameters such as the threshold voltage (Vth) and the transconductance parameter (k). In this article, we analyze and model the dependence of critical electrical device properties of printed, electrolyte-gated transistors, based on crystalline indium oxide channel, for various device geometries. It is shown that the threshold voltage scales with the charge density at the electrolyte channel interface and is hence linearly dependent on the channel length (L). Furthermore, nonlinear scaling effects in the transconductance parameter and in the ON-current are studied, which turn out to be dependent on both, channel width and length. Finally, we present a scaling model capturing the width/length dependencies of the studied transistor technology which enables the correct simulation of logic gates. [ABSTRACT FROM AUTHOR]

Rectifiers are vital electronic circuits for signal and power conversion in various smart sensor applications. The ability to process low input voltage levels, for example, from vibrational energy harvesters is a major challenge with existing passive rectifiers in printed electronics, stemming mainly from the built-in potential of the diode’s p-n-junction. To address this problem, in this work, we design, fabricate, and characterize an inkjet-printed full-wave rectifier using diode-connected electrolyte-gated thin-film transistors (EGTs). Using both experimental and simulation approaches, we investigate how the rectifier can benefit from the near-zero threshold voltage of transistors, which can be enabled by proper channel geometry setting in EGT technology. The presented circuit can be operated at 1-V input voltage, featuring a remarkably small voltage loss of 140mV and a cutoff frequency of ~300 Hz. Below the cutoff frequency, more than 2.6-μW dc power is obtained over the load resistances ranging from 5 to 20 k Ω. Furthermore, experiments show that the circuit can work with an input amplitude down to 500mV. This feature makes the presented design highly suitable for a variety of energy-harvesting applications. [ABSTRACT FROM AUTHOR]

In this report, we have studied field-effect transistors (FETs) using low-density alumina for electrolytic gating. Device layers have been prepared starting from the structured ITO glasses by printing the In2O3 channels, low-temperature atomic layer deposition (ALD) of alumina (Al2O3), and printing graphene top gates. The transistor performance could be deliberately changed by alternating the ambient humidity; furthermore, ID,ON/ID,OFF-ratios of up to seven orders of magnitude and threshold voltages between 0.66 and 0.43 V, decreasing with an increasing relative humidity between 40% and 90%, could be achieved. In contrast to the common usage of Al2O3 as the dielectric in the FETs, our devices show electrolyte-type gating behavior. This is a result from the formation of protons on the Al2O3 surfaces at higher humidities. Due to the very high local capacitances of the Helmholtz double layers at the channel surfaces, the operation voltage can be as low as 1 V. At low humidities (≤30%), the solid electrolyte dries out and the performance breaks down; however, it can fully reversibly be regained upon a humidity increase. Using ALD-derived alumina as solid electrolyte gating material, thus, allows low-voltage operation and provides a chemically stable gating material while maintaining low process temperatures. However, it has proven to be highly humidity-dependent in its performance. [ABSTRACT FROM AUTHOR]

Electrolyte-gated thin-film transistors (EGTs) with indium oxide channel, and expected lifetime of three months, enable low-voltage operation (~1 V) in the field of printed electronics (PEs). The channel width of our printed EGTs is varied between 200 and 1000 μm, whereas a channel length between 10 and 100 μm is used. Due to the lack of uniform performance p-type metal oxide semiconductors, n-type EGTs and passive elements are used to design circuits. For logic gates, transistor–resistor logic has been employed so far, but depletion- and enhancement-mode EGTs in a transistor–transistor logic boost the circuit performance in terms of delay and signal swing. In this article, the threshold voltage of the EGT, which determines the operation mode, is tuned through sizing of the EGTs channel geometry. The feasibility of both transistor operation modes is demonstrated for logic gates and ring oscillators. An inverter operating at a supply voltage of 1 V shows a maximum gain of 9.6 and a propagation delay time of 0.7 ms, which represents an improvement of ~2 × for the gain and oscillation frequency, in comparison with the resistor–transistor logic design. Moreover, the power consumption is reduced by 6 ×. [ABSTRACT FROM AUTHOR]

Advances in printed electronics (PE) enables new applications, particularly in ultra-low-cost domains. However, achieving high-throughput printing processes and manufacturing yield is one of the major challenges in the large-scale integration of PE technology. In this article, we present a programmable printed circuit based on an efficient printed lookup table (pLUT) to address these challenges by combining the advantages of the high-throughput advanced printing and maskless point-of-use final configuration printing. We propose a novel pLUT design which is more efficient in PE realization compared to existing LUT designs. The proposed pLUT design is simulated, fabricated, and programmed as different logic functions with inkjet printed conductive ink to prove that it can realize digital circuit functionality with the use of programmability features. The measurements show that the fabricated LUT design is operable at 1 V. [ABSTRACT FROM AUTHOR]

Printed electronics can benefit from the deployment of electrolytes as gate insulators, which enables a high gate capacitance per unit area (1– 10 μF cm−2) due to the formation of electrical double layers (EDLs). Consequently, electrolyte-gated field-effect transistors (EGFETs) attain high-charge carrier densities already in the subvoltage regime, allowing for low-voltage operation of circuits and systems. This article presents a systematic study of lumped terminal capacitances of printed electrolyte-gated transistors under various dc bias conditions. We perform voltage-dependent impedance measurements and separate extrinsic components from the lumped terminal capacitance. The proposed Meyer-like capacitance model, which also accounts for the nonquasi-static (NQS) effect, agrees well with experimental data. Finally, to verify the model, we implement it in Verilog-A and simulate the transient response of an inverter and a ring oscillator circuit. Simulation results are in good agreement with the measurement data of fabricated devices. [ABSTRACT FROM AUTHOR]

A physical unclonable function (PUF) is a hardware circuit that produces a random sequence based on its manufacturing-induced intrinsic characteristics. In the past decade, silicon-based PUFs have been extensively studied as a security primitive for identification and authentication. The emerging field of printed electronics (PE) enables novel application fields in the scope of the Internet of Things (IoT) and smart sensors. In this paper, we design and evaluate a printed differential circuit PUF (DiffC-PUF). The simulation data are verified by Monte Carlo analysis. Our design is highly scalable while consisting of a low number of printed transistors. Furthermore, we investigate the best operating point by varying the PUF challenge configuration and analyzing the PUF security metrics in order to achieve high robustness. At the best operating point, the results show areliability of 98.37% and a uniqueness of 50.02%, respectively. This analysis also provides useful and comprehensive insights into the design of hybrid or fully printed PUF circuits. In addition, the proposed printed DiffC-PUF core has been fabricated with electrolyte-gated field-effect transistor technology to verify our design in hardware. [ABSTRACT FROM AUTHOR]

Electrolyte-gated, printed field-effect transistors exhibit high charge carrier densities in the channel and thus high on-currents at low operating voltages, allowing for the low-power operation of such devices. This behavior is due to the high area-specific capacitance of the device, in which the electrolyte takes the role of the dielectric layer of classical architectures. In this paper, we investigate intrinsic double-layer capacitances of ink-jet printed electrolyte-gated inorganic field-effect transistors in both in-plane and top-gate architectures by means of voltage-dependent impedance spectroscopy. By comparison with deembedding structures, we separate the intrinsic properties of the double-layer capacitance at the transistor channel from parasitic effects and deduce accurate estimates for the double-layer capacitance based on an equivalent circuit fitting. Based on these results, we have performed simulations of the electrolyte cutoff frequency as a function of electrolyte and gate resistances, showing that the top-gate architecture has the potential to reach the kilohertz regime with proper optimization of materials and printing process. Our findings additionally enable accurate modeling of the frequency-dependent capacitance of electrolyte/ion gel-gated devices as required in the small-signal analysis in the circuit simulation. [ABSTRACT FROM AUTHOR]

In the domain of printed electronics (PE), field-effect transistors (FETs) with an oxide semiconductor channel are very promising. In particular, the use of high gate-capacitance of the composite solid polymer electrolytes (CSPEs) as a gate-insulator ensures extremely low voltage requirements. Besides high gate capacitance, such CSPEs are proven to be easily printable, stable in air over wide temperature ranges, and possess high ion conductivity. These CSPEs can be sensitive to moisture, especially for high surface-to-volume ratio printed thin films. In this paper, we provide a comprehensive experimental study on the effect of humidity on CSPE-gated single transistors. At the circuit level, the performance of ring oscillators (ROs) has been compared for various humidity conditions. The experimental results of the electrolyte-gated FETs (EGFETs) demonstrate rather comparable currents between 30%–90% humidity levels. However, the shifted transistor parameters lead to a significant performance change of the RO frequency behavior. The study in this paper shows the need of an impermeable encapsulation for the CSPE-gated FETs to ensure identical performance at all humidity conditions. [ABSTRACT FROM AUTHOR]

Printed electronics is a fast-growing emerging technology, which is expected to play a major role in smart sensors for the Internet of Things domain. While there has been considerable progress at the device level by new materials, on circuit level results are still rare. In this letter, we report on the design, simulation, fabrication, and measurement of an inkjet-printed latch, which is an essential building block for digital circuits. Our technology approach is based on electrolyte-gated transistors, which enables low-voltage operation and yields an outstanding electrical performance due to high mobility of the semiconducting, precursor-made In2O3 channel. The fabricated latch can operate reliably down to 0.6 V, where the power consumption is only 16 \mu \textW . The area requirement is about 7 mm2, and in terms of lifetime, no performance degradation was observed during an experimental period of 12 weeks. [ABSTRACT FROM PUBLISHER]