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Negative Bias Temperature Instability (NBTI) is suspected to be linked to various other MOSFET phenomena. We report measurements of increased drain current noise, increased gate leakage current, and decreased recoverable threshold voltage shift after multiple cycles of negative bias temperature stress and relaxation for three different technologies. We also find that stress conditions have to be carefully selected, otherwise oxide breakdown will be erroneously interpreted as a correlation between NBTI, noise and gate leakage. Finally, the implications of our findings on the modelling of oxide defects are highlighted. [ABSTRACT FROM PUBLISHER]

Short term threshold instabilities may cause erratic behavior in analog circuits like comparators and analog-to-digital-converters. As conventional characterization procedures have not been appropriately sensitized to such issues, this kind of erratic behavior usually only occurs in products where it is very difficult to identify. Therefore, for example prior to the introduction of a new gate stack, it is essential to do a careful experimental characterization of short term threshold instabilities, which goes beyond standard NBTI or PBTI measurements. A reliable forecast of the effect of threshold instabilities on the performance of analog circuits will require circuit simulations taking the threshold instabilities into account. [ABSTRACT FROM PUBLISHER]

With a significantly reduced Negative Bias Temperature Instability, SiGe channel pMOSFETs promise to virtually eliminate this reliability issue for ultra-thin EOT devices. The intrinsically superior NBTI robustness is understood in terms of a favorable energy decoupling between the SiGe channel and the gate dielectric defects. Thanks to this effect, a significantly reduced time-dependent variability of nanoscaled devices is also observed. Other reliability mechanisms, such as Channel Hot Carriers, Time-Dependent Dielectric Breakdown and Low-Frequency noise are demonstrated not to be showstoppers. Finally the performance improvement promised by the SiGe technology is discussed from the perspective of VLSI logic circuits. [ABSTRACT FROM PUBLISHER]

A thorough analysis of charge-pumping extraction techniques for hot-carrier induced defect spatial distribution in MOSFETs has been carried out. We discuss the main features of the existing approaches reflecting upon their shortcomings and applicability limits. For our investigations a new simple and accurate compact model for the MOSFET local oxide capacitance has been employed. The spatial distribution extracted from experiment is in a good agreement with the findings of our physics-based model of hot-carrier degradation. [ABSTRACT FROM PUBLISHER]

We study p-type metal-oxide-semiconductor field-effect transistors (pMOSFETs) using the direct-current-current-voltage (DCIV) method before and after bias temperature stress. The stress is varied over a wide range of temperatures using our polyheater technology. The ability of the SRH model and a multistate non-radiative multiphonon (NMP) model to meaningfully reproduce the acquired DCIV data is compared. It is demonstrated that the SRH model cannot capture the detailed features of the data and a more detailed model is required. [ABSTRACT FROM PUBLISHER]

We study charge trapping in a variety of Ge-based pMOS and nMOS technologies, either with Si passivation and conventional SiO2/HfO2 gate stack, or with GeOx/high-k gate stacks. A general model for understanding this phenomenon in alternative substrate/dielectric systems is proposed. We discuss two different approaches to pursue a reduction of charge trapping in alternative material systems, which will be necessary for achieving reliable high-mobility devices. [ABSTRACT FROM PUBLISHER]

The correlation of discrete gate and drain current fluctuations is revealed in nanoscaled SiON pFETs and nFETs, demonstrating that discrete trapping and detrapping events in the same single states are responsible of both ID and IG random telegraph noise (RTN). The high and low gate current IG-RTN levels are independent of temperature but the switching rates thermally activated indicating that the trapping and detrapping events are consistent with nonradiative multiphonon theory. [ABSTRACT FROM PUBLISHER]

The turn-around effect of the threshold voltage shift during hot-carrier stress has been investigated. Such a phenomenon is explained by the interplay between interface states and oxide traps, i.e. by the compensation of the rapidly created oxide charges by the more slowly created interface states. To prove this idea, a refined extraction scheme for the defect distribution from charge-pumping measurements has been employed. The obtained results are in a good agreement with the findings of our physics-based model of hot-carrier degradation. This approach considers not only damage produced by channel electrons but also by secondary generated channel holes. Although the contribution of the holes to the total defect creation is smaller compared to that of electrons, their impact on the threshold voltage shift is comparable with the electronic contribution. The reason behind this trend is that hole-induced traps are shifted towards the source, thereby more severely affecting the device behavior. [ABSTRACT FROM PUBLISHER]

We report extensive statistical NBTI reliability measurements of nanoscaled FETs of different technologies, based on which we propose a 1/area scaling rule for the statistical impact of individual charged gate oxide defects on the electrical characteristic of deeply scaled transistors. Among the considered technologies, nanoscaled SiGe channel devices show smallest time-dependent variability. Furthermore, we report comprehensive measurements of the impact of individual trapped charges on the entire FET ID-VG characteristic. Comparing with 3D atomistic device simulations, we identify several characteristic behaviors depending on the interplay between the location of the oxide defect and the underlying random dopant distribution. [ABSTRACT FROM PUBLISHER]

In nm-sized FET devices with just a few gate oxide defects, the typically measured threshold voltage shifts are not obviously correlated with the device behavior at high gate bias. The largest shifts observed at the threshold voltage after the capture of a single carrier are reduced at higher gate biases. This degradation-mitigating effect is further shown to be amplified at lower channel doping. The understanding gained from 3D numerical simulations is captured in a simple analytic description of a single trapped-charge impact on the FET characteristics in the entire gate bias range. Potential use is illustrated in an improved lifetime projection and in circuit simulations of time-dependent variability. [ABSTRACT FROM PUBLISHER]