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This paper reports a highly-sensitive and low power photosensor based on split gate tunnel field effect transistor (TFET) structure for visible light detection in wavelength ranging from 450–750 nm. The TFET based sensing device utilizes the photogating effect in a portion of transition metal dichalcogenide (TMD) channel. The optically tunable workfunction contrast between the two gates of dual material gate (DMG) TFET achieves significant gains in the overall device characteristics. It demonstrates high photo-to-dark current ratio of the order of $10^{8}$ and variation in responsivity in the range between $10^{3}$ AmW $^{-1}$ to $10^{-5}$ AmW $^{-1}$ for ${V}_{\textit {gs}}=-0.9$ V. This paper further discusses the photodetector performance based on the position of the photogate on the tunneling or auxiliary side, the gate splitting ratio between the photosensing region and the metal, and the ${n}$ -TFET based device design. The device performance has been analyzed using the analytical model for the optically controlled workfunction. This hybrid device consisting of an ultrathin channel sensitized with absorbing semiconductors while exploiting the characteristics of TFET leads to a new generation of highly sensitive photodetectors. [ABSTRACT FROM AUTHOR]

Quantum computing (QC) provides an efficient platform to solve complex problems such as number factoring and searching. The quantum Fourier transform (QFT) is an integral part of quantum algorithms for integer number factoring, phase estimation, discrete algorithms, interchange of position and momentum states, quantum key distribution protocol, multiparty quantum telecommunication, and quantum arithmetic. The theoretical and experimental implementations of QFT on various platforms have been proposed by researchers. Spin-torque-based qubit(s) manipulation is one of the encouraging solid-state device technologies. However, to date, QFT is not realized by spin-torque-based QC architecture. In this article, the spin-torque-based architecture has been modeled with the help of optimized decomposition of quantum circuits for the QFT. Moreover, an optimal-depth Clifford + T gates set-based quantum circuit is utilized to implement the QFT. The performance analysis in terms of fidelity (>99%), magnitude, and phase difference of respective density matrices for different forms of three-qubit QFT provides a novel way of its physical realization to address the complex problems. [ABSTRACT FROM AUTHOR]

Quantum computers perform computations based on the principles of quantum mechanics, which enables faster speed and higher security than classical computers; they also have the ability to process a large amount of information via parallel processing. Some important concepts regarding quantum computers are qubits, quantum registers, quantum logic, quantum networks, quantum reversibility, quantum teleportation, quantum data compression, quantum cryptography, universal quantum computing, and quantum algorithms. Quantum computers rely on the basic quantum principles of superposition and entanglement. The time evolution of an arbitrary quantum state is computational ly more powerful than that of a digital logic state. Theoretical quantum computing based on the rotation of the qubits has proven that it is possible for quantum devices to address complex computing problems. [ABSTRACT FROM AUTHOR]

With the inception of perpendicular magnetic anisotropy-based magnetic tunnel junction (PMTJ) devices, spin-transfer torque (STT) magnetic random access memory (MRAM) is considered as a promising candidate for low power high-density embedded memory applications. However, the single-level cell STT-MRAM did not create much impact due to its energy/area inefficiency, higher cost per bit, and unoptimized read/write operations in sub-50 nm regime. In this paper, a series multilevel cell (sMLC) STT-MRAM is proposed that offers higher array density with reliable and energy efficient read–write operations with minimum error rates at the lower supply voltage. A high-k dielectric metal gate-based gate-all-around vertical silicon nanowire is used to drive the sMLC. A unified model based on Verilog-A and HSPICE is employed to imitate the PMTJ device. The results of 2 bit sMLC designs demonstrate switching error probability much below $10^{-9}$ , and average write energy <2 pJ at the pulsewidth of 20 ns with a footprint area of 2F2 per bit (F is the feature size). [ABSTRACT FROM AUTHOR]

The semiconductor industry is facing a twofold challenge at sub-nanometer level; first, the high power dissipation in irreversible computing architectures due to information loss and second, inability to handle large data due to sequential information processing. These issues create obstacles in producing the presumed low-power complex computing outcomes. The heat dissipation can be reduced by utilizing the complementary metal–oxide–semiconductor-based reversible computing architectures. However, these architectures fail to enhance the performance owing to inability to process large data. Quantum computing (QC) can circumvent these problems due to its fundamental ineffaceable characteristics of quantum mechanics-based reversible computing and parallelism. Spin-torque-based physical realization is the most suitable platform for reversible computing due to the electron spin analogous to the qubit. However, optimal quantum circuits are required to physically realize the complex Boolean logic due to spin-qubit decoherence and reduce the number of transistor switching activities for the spin generation and injection required for the spin-qubit rotation. Therefore, in this paper, optimal quantum circuit decompositions are presented with the help of developed elementary quantum library { $R_{y}^{(\theta)}$ , $R_{z}^{(\theta)}$ , $\sqrt {\text {SWAP}}$ } for the spin-torque-based QC architecture. The reversible Boolean logic performance is analyzed and compared for the conventional, reduced, and optimal decompositions on the first- and second-order transmission coefficient matrix-based spin-torque QC architecture. The results encourage to set a path toward QC-based reconfigurable complex computing systems in near future. [ABSTRACT FROM AUTHOR]

Spin-torque-based quantum computing (QC) architecture is emerging as one of the novel technologies to meet scalability challenge due to its intra architecture spin qubit state manipulation. The existing model for spin-torque-based QC does not include the ratio of reflection barrier height to exchange interaction to the transmission coefficients. Therefore, in this paper, a modified matrix is proposed to analyze the effect of ratio of reflection barrier height to exchange interaction on electron–qubit interaction, deviation of axis of rotation for single-qubit rotation, and average error probability for two-qubit rotation in a spin-torque-based ${n}$ -qubit reconfigurable architecture. In addition, the conventional and reduced quantum gates are compared for existing and modified matrices. The quantum gates performance is analyzed in terms of number of electrons required per gate for the electron–qubit interaction, gate fidelity, number of elementary quantum operations per gate, and gate execution time. Reconfigurability is accomplished through barrier height modulation to reduce the architecture hardware. Moreover, a novel nanomagnet-based spin reservoir is incorporated in the architecture for the nonlocal spin injection to facilitate only spin-based operations. High fidelity (~99%) of quantum gates is attained for the fault-tolerant QC. [ABSTRACT FROM AUTHOR]

In this paper, we propose and investigate a novel heterojunction T-shaped tunneling field-effect transistor (TTFET) using Sentaurus technology computer-aided design (TCAD) simulations. The electrical characteristics of InP/In0.53Ga0.47As heterojunction TTFET are compared with an L-shaped tunneling field-effect transistor (LTFET) and are found to be superior. The proposed T-shape of device increases the tunneling cross-sectional area of the TTFET. This results in $4.3\times $ improvement in the drive current, $4\boldsymbol \times $ improvement in the transconductance, and $2.36\times $ improvement in the cutoff frequency as compared to the LTFET. Besides this, the gate–drain overlapped structures of TTFET and LTFET reduce the ambipolarity of the device in comparison to the conventional LTFET. The distribution of source and channel of the TTFET in vertical direction enhances the scalability of the device. [ABSTRACT FROM PUBLISHER]

High- $k$ spacer materials have been extensively studied nowadays for the enhancement of electrostatic control and suppression of short-channel effects in nanoscaled devices. However, the exorbitant increase in fringe capacitance due to high- $k$ spacers deteriorates the dynamic circuit performance. Interestingly, this paper demonstrates effective reduction in circuit delay with an optimum usage of high- $k$ spacer material. An asymmetric dual- $k$ spacer trigate (ADS-TG) FinFET architecture is employed for the purpose. From extensive 3-D simulations, it is demonstrated that ADS-TG device significantly improves the overall circuit delay and robustness performance while fully capturing the fringe capacitance effects. A FinFET inverter and a three-stage ring oscillator (RO3) are adopted to investigate the performances carefully. In comparison with the conventional device, the ADS-TG device speeds up the RO3 circuit by 22.6% and 32.4% using high- $k$ spacer dielectrics HfO2 and TiO2, respectively. Contradictorily, a purely high- $k$ FinFET device deteriorates the RO3 delay per stage up to 11%. Furthermore, the effects of supply voltage and underlap length on ADS-TG-based RO3 delay over the conventional ones are also dealt in. The ADS-TG device and static RAM based on this device prove to be more variation tolerant in comparison with the conventional configurations. [ABSTRACT FROM AUTHOR]

Spin transfer torque (STT) magnetic random access memories (MRAMs) have recently emerged as one of the strongest contenders for universal memory technology. They have entire range of features, i.e., high speed, nonvolatility, high density, and low power, which make them cynosure to every memory designer's notion. Researchers are working ardently to use STT MRAMs under continuously increasing scaling challenges. To accommodate a larger amount of embedded memory, the cell size must be reduced. Therefore, the designs target to attain an optimistic figure of 4F 2 (F being the feature size) array density, which is the maximum achievable two-dimensional (2-D) density. With this objective in mind, a novel 4F2 buried-source-line (SL) STT MRAM cell structure with a vertical gate all around (GAA) cylindrical buried source NMOS transistor is proposed. The magnetic tunnel junction (MTJ) multilayer structure is stacked above the select device with both occupying the same 2-D area. The diameters of perpendicular MTJ and vertical silicon nanowire are equal (i.e., F). Device simulations have been carried out on TCAD for buried source vertical GAA device structure. Furthermore, these TCAD results are used to calibrate the BSIM CG model for cylindrical GAA transistors. The proposed STT MRAM cell is then analyzed using calibrated Verilog-A models for perpendicular anisotropy MTJ and vertical GAA NMOS transistor (BSIM CG). The performance analysis in terms of read stability, write margins, and power dissipation for the proposed cell is also presented. [ABSTRACT FROM PUBLISHER]

Underlap FinFET devices, or trigate transistors, are considered to be the most favorable substitute to the conventional bulk device below 22-nm technology node. However, their application in circuit design requires specific attention because of the fin width quantization and increased parasitic. This paper proposes a double dielectric or dual-k spacers technology to enhance the electrostatic integrity of underlap FinFETs. For the first time, we investigate the circuit performance such as that of static RAMs (SRAMs), based on the proposed dual-k spacer FinFETs. The proposed structure enhances SRAMs performance in terms of robustness, access times, and the leakage power during all possible modes of operation. The hold, read, and write-margin increases by 8.7%, 9.4%, and 10.4%, respectively, as compared with conventional FinFET SRAM. Furthermore, the read and write access times reduces by 56% and 17.1%, respectively. Moreover, the standby leakage power is also reduced by \sim73\% compared with the conventional FinFET-based SRAM while occupying same bit-cell area. [ABSTRACT FROM PUBLISHER]

In this study, electrical behaviour of dual‐gate (DG) and single‐gate (SG) organic thin film transistors (OTFTs) is investigated using Atlas two‐dimensional (2D) numerical device simulation. Compared with the SG, DG organic transistor shows improved performance because of the presence of two channels formed in DG device by charge carrier modulation. Furthermore, this study introduces all‐p organic inverter circuits with diode‐load and zero‐Vgs‐load logic configurations using SG and DG structures. Static and dynamic behaviour of all‐p organic inverter circuits is compared with addressing the effect of both the devices. A maximum voltage gain (AV) of 16 is obtained in zero‐Vgs‐load logic using DG‐OTFT, whereas SG‐OTFT configuration produces a maximum AV of about 6.27. Significant improvements in propagation delay of 66% for diode‐load and 53% for zero‐Vgs‐load logic using DG‐OTFT are obtained as compared with SG‐OTFT. [ABSTRACT FROM AUTHOR]

This paper proposes a new asymmetric underlap Fin-Field Effect Transistor (FinFET) structure using a dual-k spacer. Asymmetric dual-spacer at source shows excellent gate control over the channel due to increase in the outer fringe field at gate/source underlap. Hence, this structure exhibits a superior short-channel effect metric over the conventional/single-spacer underlap FinFET. The proposed asymmetric structure enhances static random access memories (SRAMs) performance in terms of robustness, access times as well as leakage power during the hold, read, and write operations. The hold static noise margin and write margin increases by 5.16% and 5.66%, respectively. The read stability enhances by 13.75% and 19.35% over conventional FinFET SRAM circuit. Furthermore, the leakage power reduces by 60%, and write access time improves by 23.63%. Compared with conventional FinFET-based SRAM, same bit-cell area and read delay are associated with the proposed structure. Supply voltage scalability on SRAM design metrics is also investigated. In addition to SRAM application, underlap length, lateral source/drain doping gradient, and the high-k spacer width are optimized for high-performance digital applications. [ABSTRACT FROM AUTHOR]