Search

As a transmitter power amplifier (PA), the electrical output characteristics of gallium nitride (GaN) high electron mobility transistors (HEMTs) are closely related to the drain current versus drain voltage (${I}_{d}$ – ${V}_{d}$) characteristics. Any abnormalities in the ${I}_{d}$ – ${V}_{d}$ characteristics will seriously affect device performance. Therefore, many groups have investigated the kink effect of GaN HEMTs. One of the commonly used measurement methods of the kink effect is the ${I}_{d}$ – ${V}_{d}$ forward and reverse sweep. In this study, we used the same method for Al2O3/Si3N4–AlGaN/GaN metal–insulator–semiconductor HEMT (MIS HEMT) devices. We found that not only did the kink effect occurred but ${I}_{d}$ also increased abnormally during the reverse sweep and after a series of electrical measurements. At the end of the forward sweep, impact ionization caused by a high ${V}_{d}$ generated electron–hole pairs and some holes accumulated under the gate region, which caused the negative shift of the threshold voltage (${V}_{\text{Th}}$), leading to an abnormal increase in ${I}_{d}$ during the reverse sweep. [ABSTRACT FROM AUTHOR]

In this article, a new metal-semiconductor field-effect transistor (MESFET) is introduced by amending the carrier distribution in the active regions of the device for radio frequency applications (RF). A quasi-two-dimensional material beta gallium oxide (β-Ga2O3) semiconductor is used as a fundamental material. To amend the carrier distribution, a tunnel diode (TD- β GO) is employed at the bottom of the source and the channel regions in the buried oxide (BOX) layer of MESFET. In our work, parameters such as the breakdown voltage, the self-heating effect, the kink effect, the parasitic capacitance, the power gains, the noise figure, and the carrier’s concentration are obtained and compared with the conventional structure. As a result of employing the tunnel diode, the TD-β GO MESFET has better characteristics in comparison with the C-β GO MESFET though the drain current at the saturation region in the TD- ${\beta }$ GO structure is reduced. [ABSTRACT FROM AUTHOR]

We report sub-micron channel length ($0.5~\mu \text{m}$), low-temperature polysilicon (LTPS) thin-film transistor (TFT) using blue laser annealing (BLA) for ultra-high-resolution displays. The TFTs exhibited negligible kink effect in output characteristics with excellent negative bias temperature stability. Protrusion-free BLA LTPS is evident from the transmission electron microscopy (TEM) image. Technology computer-aided design (TCAD) simulation reveals that the protruded LTPS with grain boundaries has ~1.4 times higher electric field than protrusion-free LTPS. This causes high impact generation rate of ${3.76}\times {10}^{{14}}$ cm−3s−1 ~8 times) compared to ${4.64}\times {10}^{{13}}$ cm−3s−1 for protrusion-free LTPS TFTs. It is demonstrated that protrusion-free LTPS can achieve kink-free, sub-micron short channel devices. [ABSTRACT FROM AUTHOR]

This study examines the appearance of a kink effect phenomenon in the I $_{\mathbf {D}}$ -V $_{\mathbf {D}}$ electrical characteristics of low-temperature polycrystalline Si thin-film transistors (LTPS TFTs) after high-current-induced hot-carrier stress (HCS). During HCS, electron–hole pairs were generated in the channel near the drain terminal owing to impact ionization. Next, the electrons were repelled towar the source by the drain electric field, thereby inducing the floating body effect, which lowered the source barrier. In addition, a dual-gate-structured LTPS was found to inhibit the electrical degradation caused by HCS. The COMSOL simulation indicated that in the dual-gate structure, holes at the upper and lower margins of the channel were inverted and inhibited the degradation caused by the floating body effect. Therefore, the use of dual-gate LTPS TFTs could facilitate high-current gate-on-array circuit applications in display panels. [ABSTRACT FROM AUTHOR]

The drain conductance oscillations are simultaneously observed in the trigated and double-gated poly-Si junctionless (JL) nanowire thin-film transistors (TFTs). The strongest oscillations appear at ${V} _{\text {GS}}$ of 1 V and $V_{\text {DS}}$ of 4–5 V/6–7 V in 0.35- $\mu \text{m}$ /5- $\mu \text{m}$ poly-Si JL nanowire TFTs. To explain the drain conductance oscillations, in addition to the separated sub-bands and Coulomb blockade effect, the space-charge-potential barrier/grain boundary (GB) potential barrier in the channel and the kink effect in the output characteristics should be considered. The space-charge-potential barrier is affected by the unstable trapped electrons at GB and leads to the drain conductance oscillations. Due to the kink effect, an anomalous increase of the current in the output characteristics can enhance the conductance oscillations. Moreover, the channel of the double-gated device shows higher degree of crystallinity by solid-phase crystallization. Compared with the trigated device without solid-phase crystallization, less GB potential barriers in the channel of the double-gated device lead to a higher mobility in the channel, and these electrons can easily destroy the stability of the trapped electrons at the GBs, resulting in the stronger drain conductance oscillations. Therefore, the physical mechanisms are proposed to understand the drain conductance oscillations well in poly-Si JL nanowire TFTs. [ABSTRACT FROM AUTHOR]

Results specific to power amplifiers (PAs) designed using a SOI EDNMOS transistor free of kinks in ID-VD plane and high breakdown voltage are presented. The suppression of the drain current kink and improvement in breakdown voltage are achieved by the omission of the N+ source implant step. Instead, the source junction is realized by an optimized NLDD implant step only, allowing the formation of an under-source body contact. This approach is highly suitable for integration with RF switch and low-noise amplifiers on the same thin film SOI substrate. The improved channel conductance is found to give rise to highly linear amplitude and phase characteristics under high power conditions when the optimized EDNMOS device is used standalone as a PA. [ABSTRACT FROM AUTHOR]

A new technique to control the kink effect in the high-voltage lateral double-diffused MOSFET (LDMOS) is presented in this paper. This technique produces a local minimum in the band diagram of the proposed structure, which causes the lower barrier height for the holes from the channel to the source region. So, the produced excess holes during the impact ionization process in the channel are reduced significantly. We have called the proposed structure as local minimum energy band LDMOS (LMEB-LDMOS) transistor. The LMEB-LDMOS structure contains modified source and drain regions. The modified source region creates a local minimum in the energy band diagram for absorbing the excess holes, and the modified drain region causes high breakdown voltage (462 V) and low specific on-resistance ( 5.1~\text m\Omega \cdot ~\text cm^2) . Also, the drift region with lower doping density than drain is deleted in LMEB-LDMOS transistor. The simulation with 2-D ATLAS simulator shows that the proposed structure improves the device performance. [ABSTRACT FROM PUBLISHER]

A new multiple-gate poly-Si thin-film transistor (TFT) with a bottom field plate (FP) is proposed. The FP disperses the high current density away from the top corner of the spacer channel with the highest electric field, leading to an improved kink effect. Moreover, owing to an inversion layer induced by the FP at the bottom region of spacer poly-Si channel, a higher on-state current is achieved. In addition, the electric field near drain area is reduced, leading to a lower off-state current. Overall, the new multiple-gate poly-Si TFT shows improved characteristics as compared with the counterpart without a bottom FP. [ABSTRACT FROM PUBLISHER]

In this letter, a high-current kink effect free Z-gate polycrystalline silicon (poly-Si) thin-film transistor (ZG-TFT) is proposed and demonstrated. The ZG-TFT, which is formed by a raised source/drain (RSD) region and a split channel (SC) structure, reveals better device performance. Our experimental results show that the ON-current of ZG-TFT is about two times higher than that of a conventional single top gate TFT, and the leakage current is greatly reduced simultaneously. In addition, the high drain electric field is considerably reduced by the RSD structure, and the SC design can further effectively suppress the kink effect. Therefore, a better ON/OFF current ratio and a higher drain breakdown voltage can be achieved. [ABSTRACT FROM PUBLISHER]

This paper investigates the impact of ionizing radiation on floating body effects for the 130 nm PDSOI NMOSFETs. It is shown that the floating body effects are restrained by the irradiation both for the core device and the input/output (I/O) device. For the core device, the second peak of the front gate transconductance which is known as the gate-induced floating body effect degrades with the incremental total dose. The decline of the second g_m peak is ascribed to the impact of the radiation-induced leakage current, but not to the radiation-induced interface traps assisted recombination or the suppression of the electron valence band (EVB) tunneling. For the I/O device, the kink effect and the hysteresis effect in the output characteristic which are observed before irradiation become insignificant after irradiation. These phenomena are due to the fully depleted of the silicon film in the I/O device which is caused by the buried oxide charge trapping. In addition, a radiation-induced latch, which is result from the leakage current-induced impact ionization, is also observed in the I/O device. [ABSTRACT FROM PUBLISHER]

Via a simple selective-etching technique, a poly Si nanowire (NW) thin-film transistor (TFT), accompanied with the offset region, embedded vacuum gaps, and subgate structure, has been fabricated and characterized. The embedded vacuum gaps serves as an effective thicker insulator above the offset region, thus effectively reduces OFF-state leakage current and kink effect. This is because, under gate/drain biases, the electric field at channel surface near the drain can be reduced by the vacuum gap design compared with that in the conventional NW TFT. The extension of TiN layer above vacuum gap serves as a subgate and induces an inversion layer at the offset region to maintain a high on-current. The local electrical field located at the channel spacer surface and sharp corner near the drain is much lower in proposed vacuum gap structure compared with that in conventional NW TFT. Therefore, the device reliability, such as the degradation of threshold voltage, subthreshold swing, and transconductance under dc hot-carrier stress, is obviously improved by the proposed vacuum gap structure. Therefore, this proposed NW TFT is suitable for applications in advanced system-on-panel and 3-D circuit. [ABSTRACT FROM AUTHOR]

In this paper, the electrical characteristics of sequential-lateral-solidification (SLS) single-crystal-like nanowire (NW) poly-Si thin-film transistors (TFTs) with various gate structures are compared and comprehensively studied. The self-heating and kink effects of all SLS TFT devices with various gate structures are analyzed. Owing to the nanoscale nitride hard mask, each NW is easily transformed within one crystalline grain of the SLS poly-Si film with the regularly arranged grains; thus, each NW performs with a single-crystal-like device channel. Therefore, NW-type SLS TFTs with gate-all-around (GAA) and trigated (TRI) structures exhibit better electrical characteristics as compared with the conventional planar SLS TFTs. At moderate VGS and VDS biases, GAA devices exhibit better electrical characteristics. However, the self-heating effect and the local electric fields located at three sharp corners result in the severe degradation of electrical characteristics for GAA-SLS TFTs operated or stressed at high VGS and VDS biases. [ABSTRACT FROM PUBLISHER]

A tunnel diode body contact (TDBC) silicon-oninsulator (SOI) MOSFET structure without floating-body effects (FBEs) is proposed and successfully demonstrated. The key idea of the proposed structure is that a tunnel diode is embedded in the source region, so that the accumulated carriers can be released through tunneling. In an n-MOSFET, a heavily doped \p^+ layer is introduced beneath the \n^+ source region. The simulated and measured results show the suppressed FBE, as expected. Other phenomena that originate from the FBEs, such as the kink, linear kink effect, abnormal subthreshold swing, and small drain-tosource breakdown voltage in the properties, were also sufficiently suppressed. In addition, it should be noted that the proposed SOI MOSFETs are fully laid out and process compatible with SOI CMOS. Hysteresis effects disappear in TDBC SOI MOSFETs, which makes them attractive for digital applications. On the other hand, in analog applications, TDBC SOI MOSFETs are shown to hold the advantage over floating-body SOI MOSFETs due to their higher Gm/ID ratio. TDBC SOI MOSFETs can be considered as one of the promising candidates for digital and analog devices. [ABSTRACT FROM PUBLISHER]

SiN passivation layers were found to yield better performance, suppress the kink effect, and improve the gate leakage current and gate-induced drain leakage (GIDL) of polysilicon thin-film transistors (TFTs). The SiN passivation layers deposited under different deposition conditions possess different characteristics due to their varying passivation effect. A physical mechanism is proposed to explain the double-hump phenomenon induced by incomplete trap passivation. Based on the analysis of width dependence, the better performance of the samples with SiN passivation layers was attributed not only to radical passivation of the defect states but also to radical passivation of preexisting defects in the gate oxide. Furthermore, using SiN passivation layers improves immunity to positive gate bias stress, negative gate bias stress, and hot-carrier stressing. Moreover, the manufacturing processes are simple (without the long processing time plasma treatment requires) and compatible with TFT processes. [ABSTRACT FROM PUBLISHER]

In this paper, a scalable compact model for partially depleted silicon-on-insulator drain-extended MOSFETs (PD SOI DEMOSFETs) is developed using a subcircuit approach. The proposed compact model captures the special direct-current behavior of a PD SOI DEMOSFET transistor. Our model accounts for high-voltage effects such as quasi-saturation and impact ionization in the drift region, along with a floating-body effect such as the kink effect in the output characteristics of the floating-body PD SOI DEMOSFET transistor. In the subcircuit approach used, the channel region is modeled using the BSIM4SOI model, and the drift region is modeled using a bias-dependent resistance model, along with a current-controlled current source. The model is validated for a set of channel and drift lengths to demonstrate the scalability of the model. The accuracy of the proposed compact model is verified using 2-D numerical simulations. [ABSTRACT FROM AUTHOR]

In this paper, we propose a high-performance kink-effect-free bottom-gated polycrystalline (poly-Si) thin-film transistor with a drain-extended field plate (FP) structure. The extended-drain FP can distribute the electric field to the channel near the drain area and, particularly, can change the electron current path. The altered current path leads to a high current density and high electric field split structure that reduces the impact ionization at the drain area. Our experimental results show that the on-current of the proposed device is higher than that of the conventional structure, and the kink effect as well as the leakage current is simultaneously improved. Moreover, the device stability, such as threshold voltage shift and transconductance degradation under a high gate bias, is enhanced by the proposed drain-extended FP design. The current and electric field split structure is also beneficial in scaling down the device size for a better performance. [ABSTRACT FROM PUBLISHER]

This letter provides a clear understanding of the kink effect in S22 for active solid-state electronic devices. The origin of the kink effect is ascribed to the intrinsic section of the transistor, whereas the extrinsic elements determine its shape at the extrinsic ports. Therefore, to fairly compare the kink effect for GaN and GaAs HEMTs, the present analysis is not only focused on the whole devices but also on their intrinsic sections. The experimental evidence shows that, independently of the specific semiconductor technology, the size and the frequency band of the kink effect are mainly due to the values of the intrinsic transconductance and capacitances, respectively. [ABSTRACT FROM PUBLISHER]

This letter provides a valuable technique for evaluating the size and the shape of the kink effect in S 22 for microwave transistors. Since this phenomenon can be detected as the appearance of a concave shape in Im(S 22) versus Re(S 22), the second derivative of such a function is exploited for defining a set of parameters to fully and systematically characterize it. The effectiveness of the developed technique is demonstrated by its application to quantify the increase of the kink effect with the gate periphery for 0.15 \mum GaAs HEMTs. [ABSTRACT FROM PUBLISHER]

A novel SOI MOSFET structure to suppress the floating-body effect (FBE) and the short-channel effects is proposed and successfully demonstrated. In the new structure, a tunnel diode body contact is embedded in the source region, which can effectively release the accumulated body carriers. In an nMOSFET, a heavily doped \p^+ layer is introduced beneath the \n^+ source region so that the body and the source are effectively connected through tunneling. The fabricated device shows the suppressed FBE and lower DIBL. The new structure does not enlarge the device size and is fully compatible with SOI CMOS technology. [ABSTRACT FROM AUTHOR]

Kink effects are studied in conventional AlGaN/GaN high-electron-mobility transistors by measuring their current-voltage characteristics with various bias sweeping conditions at drain and gate terminals. It is found that the kink effect is induced by drain and gate pumping. The magnitude of kink is directly related to the maximum drain voltage and current levels during on-state operation. The hot electrons in the 2-D electron gas channel generated under high drain bias could be injected into the adjacent epitaxial buffer layer where they can be captured by donor-like traps. Hot electron trapping and the subsequent field-assisted de-trapping is suggested to be the dominant mechanism of kink generation in the studied device. The extracted activation energy of the traps accounting for the kink effect is 589 \pm 67 meV from temperature-dependent transient measurement, and is close to the energy of the E2 trap widely reported in GaN layers. [ABSTRACT FROM AUTHOR]