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Threshold logic has been attracting great attention from researchers due to the rapid development in nanotechnology-based devices. In the state-of-the-art approach to the threshold logic network (TLN) synthesis using don’t cares, we observed that not all the computed don’t cares contribute to the cost minimization of threshold logic gate (TLG). Therefore, in this work, we focus on computing the don’t cares that effectively provide the opportunities for cost minimization. Furthermore, De Morgan’s law for TLGs is applied such that global TLN optimization considering the cost and the number of inverters can be achieved. The experimental results show that the proposed approach is capable of obtaining efficiently a smaller cost and fewer inverters for a set of TLN benchmarks. [ABSTRACT FROM AUTHOR]

Quantum-dot cellular automata (QCA) is considered as a promising emerging technology due to its low power dissipation and high device density. Since the majority function is the main operation in QCA circuits, minimizing the number of majority gates in QCA circuits is crucial to the corresponding QCA circuit minimization. A previous work used the node-merging technique to replace one target node with an existing substitute node in majority circuits for optimization. However, this technique may fail when no substitute nodes exist for a target node. In this article, we propose an enhanced optimization technique for majority circuits by adding a new node into the circuits and removing the target node and its fanin nodes. The experimental results show that this technique improves the results of the node-merging technique on a set of EPFL logic synthesis benchmarks. Additionally, this enhanced technique can work together with other optimization techniques. The circuit size reduction in the integrated approach reaches 1.26 times as compared to the results using the node-merging technique. [ABSTRACT FROM AUTHOR]

LOOPLock is the state-of-the-art cyclic logic locking method in hardware security. LOOPLock is able to invalidate SAT Attack, Removal Attack, and CycSAT simultaneously by introducing two types of cycle pairs in a circuit. In this work, we analyze LOOPLock’s locking mechanism and propose an attacking approach based on locking structure analysis. Furthermore, to defend the new attack, we propose LOOPLock 2.0, which strengthens the original cyclic logic locking method—LOOPLock. Experimental results show the efficiency and effectiveness of the proposed attacking approach to LOOPLock and the high defense capability of LOOPLock 2.0. [ABSTRACT FROM AUTHOR]

This article proposes a new necessary condition and the corresponding speedup strategies to the threshold function (TF) identification problem. The state-of-the-art to this identification problem could be very time-consuming when the function-under-identification is a non-TF with the unateness property. The proposed new necessary condition can be seamlessly integrated into this identification algorithm. As compared with the state-of-the-art, the improved identification algorithm with the proposed necessary condition can more effectively and efficiently detect non-TFs. Furthermore, according to the experimental results, the ratio of CPU time overhead in the process of checking the proposed necessary condition for identifying all the 8-input TF is only 0.1%. [ABSTRACT FROM AUTHOR]

SAT Attack, CycSAT, and Removal Attack have demonstrated their abilities to break most existing logic locking methods. In this article, we propose a new cyclic logic locking method to invalidate these attacks simultaneously. Our main intention is to create noncombinational cycles to lock a circuit. Specifically, the noncombinational behavior in the noncombinational cycles that is unobservable at the primary outputs (POs) needs to be preserved when the correct key-vector is fed to resist CycSAT, and the noncombinational behavior in the noncombinational cycles affecting POs needs to be preserved when the incorrect key-vector is fed to invalidate SAT Attack. Furthermore, some nodes will be removed when applying our locking method, which is able to defend Removal Attack. The experimental results show the effectiveness and low area overhead of the proposed method. [ABSTRACT FROM AUTHOR]

The identification of threshold function (TF), which determines whether a Boolean function can be represented by an linear threshold logic gate (LTG) or not, is a fundamental but important task in the theories of threshold logic. In this paper, we propose a more efficient and effective algorithm of TF identification by constructing the system of irredundant inequalities and adjusting the weight assignment comprehensively. This is the first non-ILP-based approach that is able to identify all the eight-input TFs. The experimental results demonstrated that the proposed approach is more effective than all the existing non-ILP-based approaches and the LTGs obtained by the proposed approach are optimal for near 100% cases. For TFs with 9–15 inputs, the proposed approach can identify 100 000 randomly generated TFs as well in a reasonable CPU time. [ABSTRACT FROM AUTHOR]

Memristor, which is a two-terminal nanodevice, widely used in various fields, e.g., machine learning and neuromorphic systems, has attracted much attention these years. Memristor can also be used to realize an implication logic gate and thus logic circuits. However, the fanouts in a memristor-based logic circuit have some constraints and need to be processed with special care. On the other hand, in addition to the number of memristors, the number of operational pulses is another metric to measure the quality of a memristor-based logic circuit. Hence, in this paper, we propose a synthesis algorithm to deal with the fanout problems in memristor-based logic circuits using implication logic gates for having a minimal number of operational pulses. We conducted experiments on a set of MCNC benchmarks. The experimental results show that the proposed algorithm can reduce 29% operational pulses and 36% memristor count on average compared with the state-of-the-art. [ABSTRACT FROM AUTHOR]

Quantum circuits consist of a cascade of quantum gates. In a physical design-unaware quantum logic circuit, a gate is assumed to operate on an arbitrary set of quantum bits (qubits), without considering the physical location of the qubits. However, in reality, physical qubits have to be placed on a grid. Each node of the grid represents a qubit. The grid implements the architecture of the quantum computer. A physical constraint often imposed is that quantum gates can only operate on adjacent qubits on the grid. Hence, a communication channel needs to be built if the qubits in the logical circuit are not adjacent. In this paper, we introduce a tool called the physical design-aware fault-tolerant quantum circuit synthesis (PAQCS). It contains two algorithms: one for physical qubit placement and another for routing of communications. With the help of these two algorithms, the overhead of converting a logical to a physical circuit is reduced by 30.1%, on an average, relative to previous work. The optimization algorithms in PAQCS are evaluated on circuits implemented using quantum operations supported by two different quantum physical machine descriptions and three quantum error-correcting codes. They reduce the number of primitive operations by 11.5%–68.6%, and the number of execution cycles by 16.9%–59.4%. [ABSTRACT FROM AUTHOR]

Quantum computation can solve certain problems much faster than classical computation. However, quantum computations are more susceptible to errors than conventional digital computations. Thus, a fault-tolerant (FT) quantum circuit design is required for a practical implementation. Quantum circuits consist of a cascade of quantum gates. These gates are themselves realized using primitive quantum operations that are supported by the quantum physical machine description (PMD). As different quantum systems are associated with different Hamiltonians, they have different PMDs. In addition, the quantum cost for implementing a quantum operation may differ from one PMD to another. Thus, a quantum logic circuit needs to be realized with and optimized for the set of primitive quantum operations supported by the given PMD. In this paper, an FT quantum logic synthesis (FTQLS) methodology and tool is described for six different PMDs. A methodology, such as this, which can be targeted at multiple PMDs, has not been attempted before, to the best of our knowledge. The input to FTQLS is an unoptimized quantum circuit realized using a set of commonly used gates and its output is an optimized FT quantum circuit that only comprises of primitive quantum operations supported by the given PMD. FTQLS does technology mapping for different PMDs and then converts non-FT circuits to FT circuits. For technology mapping, it utilizes an optimized quantum gate library targeted at various PMDs that decomposes gates into primitive operations. Efficient conversion to FT circuits is done by integrating two quantum compilers and an FT cache table into FTQLS. For improving the synthesis results, an FT set of gates that is directly supported by each PMD is proposed. Quantum circuit optimization is done by utilizing quantum identity rules. The performance of FTQLS is evaluated using two cost metrics: number of primitive operations (#ops) and execution cycles on the critical path (#cycles). Experiment results show that the decrease in #ops varies between 58.1% and 87.0% and in #cycles between 42.8% and 76.4%, on an average, depending on the PMD. [ABSTRACT FROM AUTHOR]

An amorphous Yb2O3 passivation layer integrated with a crystalline ZrTiO4 film was explored as the advanced gate stack for Ge MOS devices. The ZrTiO 4/Yb2O 3 gate stack demonstrates Dit of 2.4 × 10^11 cm ^-2\cdot\, eV^-1 and EOT down to 0.76 nm which are, respectively, due to the formation of an interfacial YbGeO x layer that well passivates the dangling bonds at Ge surface and the adoption of a crystalline ZrTiO4 film with a κ value of 45.6. The gate stack also shows low leakage current, tight distribution of device parameters, and desirable reliability performance, paving an alternative avenue to develop high-performance Ge MOS devices. [ABSTRACT FROM PUBLISHER]

Quantum logic circuits consist of a cascade of quantum gates. These gates are realized using primitive quantum operations that are supported by a quantum physical machine description (PMD). Since different quantum systems are associated with different Hamiltonians, a specific quantum operation may be more easily realizable in one quantum system than another. Thus, different quantum systems have different PMDs. Also, the quantum cost for implementing a quantum operation may differ from one PMD to another. Thus, a quantum logic circuit needs to be realized with and optimized for only the set of primitive quantum operations supported by the given PMD. Quantum logic design that can be targeted at multiple PMDs has not been attempted before, to the best of our knowledge. In this paper, we target quantum logic design with respect to the set of primitive quantum operations that are supported by six different PMDs: quantum dot, superconducting, ion trap, neutral atom, and two photonics systems. Our aim is to build a quantum gate library that targets these PMDs. This is akin to a cell library in traditional logic design that enables logic gates to be mapped to cells realizable in an underlying technology. To make our quantum gate library efficient in terms of the number of primitive quantum operations involved and the associated delay, we explore one- and two-qubit quantum identity rules that can help remove redundancies in the quantum gate implementation. We show that, using these identities, each gate in the library can be efficiently mapped to just the set of primitive operations supported by each of the six PMDs. Each mapping results in a different circuit structure and quantum cost, which is measured in terms of the number of primitive quantum operations and the number of execution cycles required. Thus, such a library provides the foundation for quantum logic synthesis, just like a cell library provides the foundation for technology-dependent logic synthesis (i.e., technology mapping) in traditional synthesis. [ABSTRACT FROM AUTHOR]

An amorphous (ZrO_2) _x(La _2O_3) 1-x alloy formed by depositing a ZrO _2/La_2O _3/ZrO_2 laminate and a subsequent annealing was employed as the gate dielectric for metal-oxide-semiconductor (MOS) devices. The (ZrO_2) _x(La_2O_3)1-x alloy is found to have a high permittivity κ of 26.2 with negligible amount of bulk traps, both of which are very desirable for advanced gate dielectrics. By integrating the (ZrO_2)_x(La _2O_3) 1-x alloy with an SiON interfacial layer as the gate stack, it displays good frequency dispersion in capacitance–voltage (C –V) characteristics and low interfacial trap density of 1.52 × 10^11 cm^-2 eV^-1. In addition, the current conduction mechanism of the gate stack is observed to be Fowler–Nordheim tunneling and the leakage current of 3.6 × 10^-6 A/cm^2 at the gate voltage of −1 V for equivalent oxide thickness of 1.1 nm can be achieved, which is superior to other high-κ dielectrics. Furthermore, satisfactory reliability is verified by bias temperature instability measurement. Most importantly, this gate stack not only exhibits a promising perspective for advanced CMOS technology but introduces a more reliable process to form an alloy-based high-κ gate dielectric. [ABSTRACT FROM PUBLISHER]

Ge MOS devices passivated by SmGeOx with equivalent oxide thickness of 0.61 nm were employed as the platform to evaluate the eligibility of SmGeOx as Ge surface passivation layer. The SmGeOx layer was formed by deposition of Sm2O3 on Ge substrate with a subsequent O2 annealing and the formation of SmGeOx was confirmed by X-ray photoelectron spectroscopy. The tiny frequency dispersion in capacitance measurement and a low interface trap density of 5.1\times 10^11~cm^-2eV^-1 near midgap attest to desirable passivation effect and it can be ascribed to Sm-Ge-O bonding, which is favorable in mitigating dangling bonds at Ge surface. In addition, the small hysteresis in capacitance also suggests good quality of bulk dielectric. Due to the small amount of bulk traps and large conduction band offset with respect to Ge, it enjoys low leakage current of 0.36 A/cm^2 at gate bias of Vfb (flatband voltage)-1 V. Through the test of bias temperature instability, the passivation layer demonstrates reasonable reliability performance in terms of 65-mV flatband voltage shift at 85^\circC after stressing with -16~MV/cm for 1000 s. With these characteristics, SmGeOx is promising as a passivation layer for aggressively scaled Ge MOS devices. [ABSTRACT FROM AUTHOR]

Because of a higher permittivity than \Al2\O3, a large conduction band offset and high thermal stability, a thin amorphous \Yb2\O3 layer was integrated with a \ZrTiO4 film as the gate stack for advanced Si MOS devices. With 800 ^\circ\C annealing, the \ZrTiO4 film can be crystallized in orthorhombic phase with permittivity of 45.9 and a gate stack with equivalent oxide thickness of 0.86 nm can be achieved. This crystalline \ZrTiO4/\Yb2\O3 gate stack demonstrates negligible frequency dispersion in capacitance, low interface trap density of \1.86 \times \10^11\ \cm^-2\eV^-1 , leakage current of \6.7 \times \10^-6\ \A/cm^2 at gate bias of flatband voltage (VFB)-1\ \V, and high extrapolated 10-year lifetime operating voltage of -2.9 V. These promising electrical characteristics suggest that the crystalline \ZrTiO4/\Yb2\O3 gate stack holds great potential to be applied to aggressively scaled CMOS technology. [ABSTRACT FROM AUTHOR]

\SnGeOx films formed by thermal oxidation of Sn/Ge and \SnGex/\Ge structures were confirmed by X-ray photoelectron spectroscopy and explored to investigate the capability of passivation for Ge MOS devices. It is found that Sn incorporation into germanium oxide is effective in suppressing the formation of volatile GeO. For \SnGeOx films formed by oxidation of \SnGex/\Ge structures, due to fewer dislocations between \SnGex and Ge, it enjoys an interface trap density of \2.1 \times \10^11\ \cm^-2 \cdot \eV^-1, which is lower than those oxidized from Sn/Ge structures. Furthermore, the films also demonstrate desirable electrical characteristics in terms of tiny frequency dispersion and small hysteresis in capacitance measurement, a low leakage current of \9.3 \times \10^-10\ \A/cm^2 at a gate voltage of -1 V with an effective oxide thickness of 3.6 nm, and a good bias temperature instability of 15-mV flatband voltage shift at 85 ^\circ\C after 12.5 MV/cm stress for 1000 s. [ABSTRACT FROM AUTHOR]