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In this article, we separately investigate the role of electric field and device self-heating (SHE) in enhancing the charge emission process from Fe-related buffer traps (0.52 eV from Ec) in AlGaN/GaN high electron mobility transistors (HEMTs). The experimental analysis was performed by means of drain current transient (DCT) measurements for either: 1) different dissipated power (PD,steady) at constant drain-to-source bias (VDS,steady) or 2) constant PD,steady at different VDS,steady’s. We found that: 1) an increase in PD,steady yields an acceleration in the thermally activated emission process, consistently with the temperature rise induced by SHE and 2) on the other hand, the field-effect turned out to be negligible within the investigated voltage range, indicating the absence of the Poole–Frenkel effect (PFE). A qualitative analysis based on the electric field values obtained by numerical simulations is then presented to support the interpretation and conclusions. [ABSTRACT FROM AUTHOR]

In this article, pulsed measurements of thermal resistance in GaN-based high-electron mobility transistors (HEMTs) on silicon, with different gate geometries and gate-to-drain extensions, are analyzed and modeled. Simple expressions for the thermal resistance of silicon-on-insulator (SOI) MOSFETs, which take into account the gate width and channel length, can be adapted to model the thermal resistance of these GaN-based HEMTs. Narrow width effects and the increase in the heat flow through the gate as the channel length increases were correctly reproduced. In addition, numerical simulations were performed to explain the reduction obtained in thermal resistance as the gate-to-drain extension increases. Our approach can also be applied easily to other well-established models using circuit simulators. [ABSTRACT FROM AUTHOR]

This article reports the first comprehensive analysis of the reliability of hydrogen-terminated diamond metal semiconductor field-effect transistors (MESFETs) submitted to OFF-state stress. We demonstrate that stress induces an increase in ON-resistance and a shift in the threshold voltage, along with a decrease in the transconductance peak value. These effects are ascribed to the generation of defects at the diamond surface and/or in the upper semiconductor layers. The defects are generated both in the access regions and under the gate, and their activation energy is 0.30 eV. [ABSTRACT FROM AUTHOR]

We present a detailed investigation of the trapping and detrapping mechanisms that take place in the gate region of β-Ga2O3 vertical finFETs and describe the related processes. This analysis is based on combined pulsed characterization, transient measurements, and tests carried out under monochromatic light, with photon energies between 1.5 and 5 eV. The original results presented in this article demonstrate that: (i) when submitted to positive gate stress with VGS > 3 V, the devices show a significant threshold voltage variation; (ii) this effect is not recoverable in 10 000 s in rest condition (zero bias, dark condition). (iii) VTH can quickly recover its initial value when the device is illuminated with UV-C light at 280 nm. (iv) Stress-recovery experiments carried out at different photon energies allowed us to estimate the threshold energy for the release of carriers from the Al2O3/Ga2O3 interface, and for the injection of electrons from metal to the Al2O3 insulator (conduction band discontinuity at the metal/Al2O3 interface). [ABSTRACT FROM AUTHOR]

In this article, we present the results of on-wafer short-term (24 h) stress tests carried out on 0.25-μm AlGaN/GaN HEMTs. Devices on-wafer were submitted to 24-h dc tests, at various gate and drain voltage values corresponding to dissipated power densities PD up to 40 W/mm, with estimated channel temperature ≅ 375 °C. GEN1 devices adopted a Ni/Pt/Au gate metallization and conventional plasma-enhanced chemical vapor deposition (PE-CVD) SiN passivation; in GEN2 devices, a modified gate metallization and a two-layer SiN passivation were adopted. When tested at Pd > 25 W/mm, a substantial decrease of drain current ID and transconductance gm was measured in GEN1 HEMTs, without any significant shift of threshold voltage. Failure analysis revealed that Au and O interdiffusion took place from the sidewalls; Au gradually substituted Ni as a Schottky contact, while O, in the presence of high electric field, high temperature, and high current, promoted (Al)GaN oxidation and pitting. On the contrary, negligible degradation was found after high temperature storage of GEN1 devices without applied bias, up to 450 °C. In GEN2, process modification was effective in reducing the impact of this failure mechanism, resulting in only 5% gm decrease after 24 h at a junction temperature of 375 °C with PD = 38 W/mm. Results demonstrate the effectiveness of the adopted on-wafer screening methodology in identifying potentially dangerous failure mechanisms. [ABSTRACT FROM AUTHOR]

This paper investigates the degradation of vertically aligned gallium nitride (GaN) nanowire (NW) arrays submitted to gate bias stress and UV light. Based on electrical tests and simulations, we demonstrate the existence of trapping processes that depend on the applied stress voltage ${V}_{\textsf {Gstress}}$ and on the applied light during stress (wavelength, $\lambda $). We demonstrate the following original results: 1) for positive and negative ${V}_{\textsf {Gstress}}$ conditions, no significant variation in dc characteristics is observed when the samples are stressed in dark and 2) when the devices are submitted to negative ${V}_{\textsf {Gstress}}$ and to UV light, a positive variation in threshold voltage (${V}_{\textsf {th}}$) is observed. The positive ${V}_{\textsf {th}}$ shift is ascribed to the transfer and trapping of electrons from the gate metal to the oxide, promoted by UV light. We also evaluated the temperature dependence of the threshold voltage shift under UV light. We demonstrated an increased trapping at higher temperatures, indicating a role of thermionic processes in electron trapping. On the other hand, detrapping from oxide states proceeds through defect-mediated conduction, i.e., is limited by the number of available states. [ABSTRACT FROM AUTHOR]

The gate reliability of p-GaN gate AlGaN/GaN high electron mobility transistors with a ring-gate structure is investigated by step-stress experiments under a gate bias, combined with electroluminescence imaging and pulsed measurements. For gate stress (${V} _{\text {Gstress}}$) from 0 to 13 V, the drain current is found to be stable and decreases at 13 V at OFF-state and increases at ON-state. For ${V} _{\text {Gstress}}$ from 13 to 31 V, the drain current increases at OFF-state and decreases at ON-state, whereas ${V} _{\text {TH}}$ is stable and increases slightly. The changes in drain current characteristic and ${V} _{\text {TH}}$ values of the device after applying various ${V} _{\text {Gstress}}$ are associated with the injection and trapping of holes from the p-GaN layer to the AlGaN layer, supported by the results of pulsed measurements and by the simulation of energy band diagrams. When ${V} _{\text {Gstress}}$ is further increased to a high voltage of 31 V, ${V} _{\text {TH}}$ becomes noisy and a strong luminescence signal occurs with a sudden reduction in the drain current, and finally, a catastrophic failure happens in the gate-channel region. [ABSTRACT FROM AUTHOR]

This paper investigates the trapping mechanisms in gate-injection transistors (GITs) without and with a pdrain electrode, referred to as GITs and Hybrid-Drain-embedded GITs (HD-GITs), respectively, used to inject holes and reduce charge trapping effects. We compare the two sets of devices under both the OFF-state and semi- ON state, to investigate the role of hot electrons in favoring the charge trapping. The analysis is based on combined pulsed characterization, transient measurements, and electroluminescence (EL) characterization. We demonstrate the following relevant results: 1) GITs and HD-GITs have comparable and negligible dynamic ${R}_{ \mathrm{\scriptscriptstyle ON}}$ when trapping is induced in the OFF-state; under semi- ON state conditions, GITs suffer from significant dynamic ${R}_{ \mathrm{\scriptscriptstyle ON}}$ , while HD-GITs show no additional trapping with respect to OFF-state; 2) EL characterization carried out until ${V}_{\mathsf {DS}}= 500$ V in semi- ON conditions shows comparable features, suggesting that the electric field and hot-carrier density are similar in GITs and HD-GITs. This result indicates that the hot-electron trapping rate is identical for the two sets of samples, so the difference observed in dynamic ${R}_{ \mathrm{\scriptscriptstyle ON}}$ must be ascribed to a different detrapping rate; 3) transient ${R}_{ \mathrm{\scriptscriptstyle ON}}$ measurements indicate that the traps filled in the OFF-state conditions are the same as those filled by hot electrons in semi- ON, with ${E}_{a}= 0.8$ eV (possibly ${C}_{N}$); and 4) EL analysis under constant bias indicates that in GITs there is a time-dependent increase in the luminescence signal at the drain terminal, when the devices are biased with ${V}_{\mathsf {DS}}= 300$ V. Such effect, indicative of hot-electron trapping, is not observed in HD-GITs. Based on the experimental evidence collected within this paper, we conclude that—in the semi- ON state—the main difference between GITs and HD-GITs consists in a faster detrapping rate of hot electrons, achieved through hole injection from the pdrain terminal. [ABSTRACT FROM AUTHOR]

The gate conduction mechanisms in p-gallium nitride (GaN)/AlGaN/GaN enhancement mode transistors are investigated using temperature-dependent dc gate current measurements. In each of the different gate voltage regions, a physical model is proposed and compared to experiment. At negative gate bias, Poole–Frenkel emission (PFE) occurs within the passivation dielectric from gate to source. At positive gate bias, the p-GaN/AlGaN/GaN “p-i-n” diode is in forward operation mode, and the gate current is limited by hole supply at the Schottky contact. At low gate voltages, the current is governed by thermionic emission with Schottky barrier lowering in dislocation lines. Increasing the gate voltage and temperature results in thermally assisted tunneling (TAT) across the same barrier. An improved gate process reduces the gate current in the positive gate bias region and eliminates the onset of TAT. However, at high positive gate bias, a sharp increase in current is observed originating from PFE at the metal/ p-GaN interface. Using the extracted conduction mechanisms for both devices, accurate lifetime models are constructed. The device fabricated with the novel gate process exhibits a maximum gate voltage of 7.2 V at ${t}_{\textsf {1}\%}=\textsf {10}$ years. [ABSTRACT FROM AUTHOR]

This letter reports on the observation of hot-electron and impact-ionization mechanisms in N-polar GaN-based MIS-HEMTs designed for high frequency (RF) operation. Thanks to the extremely low gate leakage of such devices, we were able to demonstrate—for the first time—a correlation between electroluminescence (EL) and gate current in the semi-on state. In the semi-on state, the devices show a non-monotonic, bell-shaped behavior of the EL-versus- ${\text {V}}_{\text {GS}}$ and of the ${I}_{\text {G}}$ -versus- ${V}_{\text {GS}}$ characteristics, and the intensity of the EL signal is proportional to the ${I}_{G}\times {I}_{D}$ product. The results are experimental evidence for impact ionization: the related mechanisms are described in detail in the letter. [ABSTRACT FROM AUTHOR]

This paper demonstrates and investigates the time-dependent vertical breakdown of GaN-on-Si power transistors. The study is based on electrical characterization, dc stress tests and electroluminescence measurements. We demonstrate the following original results: 1) when submitted to two-terminal (drain-to-substrate) stress, the AlGaN/GaN transistors show a time-dependent degradation process, which leads to the catastrophic failure of the devices; 2) time-to-failure follows a Weibull distribution and is exponentially dependent on stress voltage; 3) the degradation mechanism is strongly field dependent and weakly thermally activated, with an activation energy of 0.25 eV; and 4) emission microscopy suggests that vertical current flows under the whole drain area, possibly through extended defects. The catastrophic failure occurs at random positions under the drain contact. The time-dependent failure is ascribed to a percolation process activated by the high-electric field that leads to the generation of localized shunt paths between drain and substrate. [ABSTRACT FROM PUBLISHER]

This paper presents a new nonlinear microwave-based characterization methodology for the study of the deep levels proprieties in gallium nitride (GaN)-based high electron mobility transistors (HEMTs). Currently, it is unique measurement method allowing the extraction of time constants of HEMTs operating under large signal RF conditions. This method improves the conventional dc techniques, since it employs RF excitation during the filling condition to investigate the impact of “real-life” RF excitation on the trapping mechanisms. The experimental results demonstrate that, beyond the presence of Poole–Frenkel effect, the slow detrapping time constant is accelerated by the power dissipation of the trapping bias point. Moreover, it is possible to distinguish the impact of dc and RF conditions on the trapping phenomena. The temperature measurements allow identifying the 0.75-eV deep level, attributed to extended defects in GaN, when ionized under dc excitation. This deep level trap is probably located in the buffer layer and contributes to the RF trapping phenomenon. [ABSTRACT FROM PUBLISHER]

This paper demonstrates that—for high-electric fields and drain current levels—the electroluminescence (EL) versus VGS curves of GaN-on-Si radio frequency HEMTs significantly deviate from the well-known bell-shape, due to the turn-on of a secondary EL process that has not been described so far in the literature. Based on the combined EL measurements, electrical characterization, and thermal analysis, we demonstrate that: 1) for moderate gate and drain voltages, the EL versus VGS curve has the characteristic bell shape, and light emission originates from hot electrons injected from the source; EL signal is stronger at the edges of the gate, due to the higher electric field; 2) at high drain/gate bias and temperature, a second process induces a monotonic increase in the EL versus VGS curve; in this case, the EL signal is stronger at the center of the gate, and the EL intensity is directly correlated with the gate leakage current. Based on the experimental evidence collected within this paper, the secondary luminescence process is ascribed to: 1) the injection of carriers from the gate metal to the channel; 2) the acceleration of these electrons by the high gate–drain field; and c) the subsequent radiative emission. [ABSTRACT FROM AUTHOR]

This paper reports an experimental demonstration of the time-dependent failure of GaN-on-Si power high-electron-mobility transistors with p-GaN gate, submitted to a forward gate stress. By means of combined dc, optical analysis, and 2-D simulations, we demonstrate the following original results: 1) when submitted to a positive voltage stress (in the range of 7–9 V), the transistors show a time-dependent failure, which leads to a sudden increase in the gate current; 2) the time-to-failure (TTF) is exponentially dependent on the stress voltage and Weibull-distributed; 3) the TTF depends on the initial gate leakage current, i.e., on the initial defectiveness of the devices; 4) during/after stress, the devices show a localized luminescence signal (hot spots); the spectral investigation mainly reveals a peak corresponding to yellow luminescence and a broadband related to bremsstrahlung radiation; and 5) 2-D simulations were carried out to clarify the origin of the degradation process. The results support the hypothesis that the electric field in the AlGaN has a negligible impact on the device failure; on the contrary, the electric field in the SiN and in the p-GaN gate can play an important role in favoring the failure, which is possibly due to a defect generation/percolation process. [ABSTRACT FROM PUBLISHER]

In this brief, traps-related dispersion phenomena are investigated on GaN/AlGaN MOS-high-electron mobility transistors. Pulsed $I$ – $V$ characteristics and low-frequency-noise measurements are the characterization vehicles used to get a direct insight of the device trap-states. By considering a set of ten samples, device-to-device fluctuation parameters extracted from trap-related measurements (1/ $f$ noise and gate bias instability) are systematically compared with conventional electrical parameters (threshold voltage and ON-current). Two separate trends are identified and ascribed to two different trap families. [ABSTRACT FROM AUTHOR]

This letter reports an in-depth study of the negative threshold voltage instability in GaN-on-Si metal-insulator–semiconductor high electron mobility transistors with partially recessed AlGaN. Based on a set of stress/recovery experiments carried out at several temperatures, we demonstrate that: 1) operation at high temperatures and negative gate bias (−10 V) may induce a significant negative threshold voltage shift, that is well correlated to a decrease in on-resistance; 2) this process has time constants in the range between 10–100 s, and is accelerated by temperature, with activation energy equal to 0.37 eV; and 3) the shift in threshold voltage is recoverable, with logarithmic kinetics. The negative shift in threshold voltage is ascribed to the depletion of trap states located at the SiN/AlGaN interface and/or in the gate insulator. [ABSTRACT FROM PUBLISHER]

In this paper, a new characterization method, which allows the determination of the time constants of traps in AlGaN/GaN high electron-mobility transistors is proposed. The approach is based on the current transient method for assessing the time constants that are involved in real working conditions. To do that the dc filling pulses, which are classically used in this method, are replaced by RF filling pulses, which reproduce the real large-signal conditions. To investigate the impact of large-signal working conditions on the trapping phenomena, on-wafer single-pulse load–pull characterizations are carried out at different temperatures and for two different output load impedances: maximum of power-added efficiency and mismatched impedance. The results obtained show the deep impact of the load-line excursion on the current collapse of the detrapping drain current. A comparison between the single-pulse RF load–pull characterization and single-pulse dc measurement is finally presented. [ABSTRACT FROM PUBLISHER]

We performed pulsed measurements on organic transistors presenting four different active materials. All the devices show a strong correlation between the drain–source current and the pulse width. We attributed this phenomenon to the long time needed for channel formation and depletion. These transient effects may have a severe impact on device characterization and application development. [ABSTRACT FROM AUTHOR]

This paper reports the experimental demonstration of time-dependent dielectric breakdown in GaN-based high-electron mobility transistors (HEMTs) submitted to OFF-state stress. Based on combined breakdown measurements, constant voltage stress tests, and 2-D simulations, we demonstrate the following relevant results. First, GaN-based HEMTs with a breakdown voltage higher than 1000 V (evaluated by dc measurements) may show time-dependent failure when exposed to OFF-state stress with V\mathrm {DS} in the range 600–700 V. Second, time-to-failure (TTF) is Weibull-distributed, and has an exponential dependence on the stress voltage level. Third, time-dependent breakdown is ascribed to the failure of the SiN dielectric at the edge of the gate overhang, on the drain side. Fourth, 2-D simulations confirm that—in this region—the electric field exceeds 6 MV/cm, i.e., the dielectric strength of SiN. Finally, we demonstrate that by limiting the electric field in the nitride through epitaxy and process improvements, it is possible to increase the TTF by three orders of magnitude. [ABSTRACT FROM AUTHOR]

This paper reports an investigation of the trapping mechanisms responsible for the temperature-dependent dynamic- R\mathrm {\mathrm{{\scriptstyle ON}}} of GaN-based metal–insulator–semiconductor (MIS) high electron mobility transistors (HEMTs). More specifically, we perform the following. First, we propose a novel testing approach, based on combined OFF-state bias, backgating investigation, and positive substrate operation, to separately investigate the buffer- and the surface-related trapping processes. Then, we demonstrate that the dynamic R\mathrm {\mathrm{{\scriptstyle ON}}} of GaN-based MIS-HEMTs significantly increases when the devices are operated at high temperature levels. We explain this effect by demonstrating that it is due to the increased injection of electrons from the substrate to the buffer (under backgating conditions) and from the gate to the surface (under positive substrate operation). Finally, we demonstrate that by optimizing the buffer and by reducing the vertical leakage, substrate-related trapping effects can be completely suppressed. The results described within this paper provide general guidelines for the evaluation of the origin of dynamic R\mathrm {\mathrm{{\scriptstyle ON}}} in GaN power HEMTs and point out the important role of the buffer leakage in favouring the trapping processes. [ABSTRACT FROM AUTHOR]

This paper presents an extensive investigation of the properties of the trap with activation energy equal to 0.6 eV, which has been demonstrated to be responsible for current collapse (CC) in AlGaN/GaN HEMTs. The study was carried out on AlGaN/GaN HEMTs with increasing concentration of iron doping in the buffer. Based on pulsed characterization and drain current transient measurements, we demonstrate that for the samples under investigation: 1) increasing concentrations of Fe-doping in the buffer may induce a strong CC, which is related to the existence of a trap level located 0.63 eV below the conduction band energy and 2) this trap is physically located in the buffer layer, and is not related to the iron atoms but—more likely—to an intrinsic defect whose concentration depends on buffer doping. Moreover, we demonstrate that this level can be filled both under OFF-state conditions (by gate-leakage current) and under ON-state operation (when hot electrons can be injected to the buffer): for these reasons, it can significantly affect the switching properties of AlGaN/GaN HEMTs. [ABSTRACT FROM AUTHOR]

This letter demonstrates that GaN-based MIS-HEMTs submitted to stress with high-temperature, high drain bias, and constant source current (HTSC stress) may show degradation modes that are not detectable during standard high temperature reverse bias (HTRB) stress. Based on a number of stress/recovery experiments, we demonstrate the following novel results: 1) the combined presence of high drain bias and constant drain–source current (HTSC stress) can lead to a significant increase in ON-resistance ( R\mathrm{\scriptscriptstyle ON} ) that is not detected under conventional HTRB stress; 2) R\mathrm{\scriptscriptstyle ON} increases without changes in the threshold voltage, indicating that charge trapping takes place in the access regions, and not under the gate; 3) the R\mathrm{\scriptscriptstyle ON} increase has a monotonic dependence on the source current flowing during stress; and 4) for the same stress current level, the R\mathrm{\scriptscriptstyle ON} increase has a negative dependence on temperature. The strong correlation between R\mathrm{\scriptscriptstyle ON} increase and source current and the negative temperature coefficient strongly support the hypothesis that trapping originates from the injection of hot electrons toward the gate–drain access region. [ABSTRACT FROM PUBLISHER]

This paper reports the experimental demonstration of a novel degradation mechanism of high-power AlGaN/GaN high electron mobility transistors (HEMTs), that is, time-dependent drain-source breakdown. With current-controlled breakdown measurements and constant voltage stress experiments we demonstrate that: 1) when submitted to constant voltage stress, in the OFF-state, the HEMTs can show a significant degradation; 2) the degradation process is time-dependent, and consists of a measurable increase in subthreshold drain-source leakage; this effect is ascribed to the accumulation of positive charge in proximity of the gate, consistently with previous theoretical calculations; and 3) a catastrophic (and permanent) failure is observed for long stress times, possibly due to thermal runaway or to the increase in the electric field in proximity of the localized drain-source leakage paths. [ABSTRACT FROM AUTHOR]

This paper reports on an extensive analysis of the trapping processes and of the reliability of experimental AlGaN/GaN MIS-HEMTs, grown on silicon substrate. The study is based on combined pulsed characterization, transient investigation, breakdown, and reverse-bias stress tests, and provides the following, relevant, information: 1) the exposure to high gate-drain reverse-bias may result in a recoverable increase in the on-resistance (RON), and in a slight shift in threshold voltage; 2) devices with a longer gate-drain distance show a stronger increase in RON, compared to smaller devices; 3)current transient measurements indicate the existence of one trap level, with activation energy of 1.03 ± 0.09 eV; and 4) we demonstrate that through the improvement of the fabrication process, it is possible to design devices with negligible trapping. Furthermore, the degradation of the samples was studied by means of step-stress experiments in off-state. Results indicate that exposure to moderate-high reverse bias (<; 250 V for LGD = 2 μm) does not induce any measurable degradation, thus confirming the high reliability of the analyzed samples. A permanent degradation is detected only for very high reverse voltages (typically, VDS = 260-265 V, on a device with LGD = 2 μm stressed with VGS = - 8 V) and consists of a rapid increase in gate leakage current, followed by a catastrophic failure. EL measurements and microscopy investigation revealed that degradation occurs close to the gate, in proximity of the sharp edges of the drain contacts, i.e., in a region where the electric field is maximum. [ABSTRACT FROM AUTHOR]

In this paper, an emerging double-heterostructure high-electron mobility transistor based on AlN/GaN/AlGaN grown on silicon substrate is presented, which enables a unique simultaneous achievement of high breakdown voltage and high frequency performance. This configuration system allowed state-of-the-art GaN-on-silicon dc, RF output power, and noise performances at 40 GHz, paving the way for high-performance millimeter-wave (mmW) cost-effective amplifiers. Preliminary reliability assessment has been performed on this new class of RF devices, showing promising mmW GaN-on-Si device stability for the first time. [ABSTRACT FROM PUBLISHER]

In this paper, we review and add additional data and understandings on our findings on the two most common failure modes of GaN-based HEMTs: 1) permanent gate leakage current increase and 2) output current drop. We suggested that they have different origins and one is not necessarily correlated to the other. Yet, they can both concur to the device degradation. First, we demonstrate that the phenomenon of gate leakage current increase has a voltage-accelerated degradation kinetic. Therefore, the identification of the critical voltage for leakage increase is meaningless. We demonstrate that the time-to-breakdown tBD data are Weibull distributed and we prove that they represent intrinsic failures. According to our data, this phenomenon is not related to the inverse piezoelectric effect. Finally, a new degradation model for the gate leakage current increase based on the percolation path theory is proposed. Second, we show that the permanent output current drop is a consequence of the relaxation of AlGaN layer. This occurs by means of formation of crystallographic defects as described by the inverse piezoelectric degradation model. Finally, we show an excellent stability of devices with reduced Al content in the AlGaN barrier, proving the crucial role of strain in the reliability of AlGaN/GaN HEMTs. [ABSTRACT FROM AUTHOR]

In this paper, the effects of device self-heating on the extraction of traps activation energy are investigated through experimental measurements and numerical simulations. Neglecting the device temperature increase during the experimental measurements can lead to an underestimation of traps activation energies as well as nonoverlapping Arrhenius plots. It will be shown that said artifacts can be removed once device thermal resistance is known and used to correct the temperatures data points at which trap time constants are extracted. The correctness of the proposed method is also supported through numerical simulations carried out both by neglecting and considering thermal effects during the drain current transient measurements. Finally, the experimental results obtained are also suggesting a novel method for the extraction of device thermal resistance, which yielded comparable results with respect to those obtained with other experimental techniques. [ABSTRACT FROM AUTHOR]

This paper critically investigates the advantages and limitations of the current-transient methods used for the study of the deep levels in GaN-based high-electron mobility transistors (HEMTs), by evaluating how the procedures adopted for measurement and data analysis can influence the results of the investigation. The article is divided in two parts within Part I. 1) We analyze how the choice of the measurement and analysis parameters (such as the voltage levels used to induce the trapping phenomena and monitor the current transients, the duration of the filling pulses, and the method used for the extrapolation of the time constants of the capture/emission processes) can influence the results of the drain current transient investigation and can provide information on the location of the trap levels responsible for current collapse. 2) We present a database of defects described in more than 60 papers on GaN technology, which can be used to extract information on the nature and origin of the trap levels responsible for current collapse in AlGaN/GaN HEMTs. Within Part II, we investigate how self-heating can modify the results of drain current transient measurements on the basis of combined experimental activity and device simulation. [ABSTRACT FROM AUTHOR]

This paper presents a comprehensive review of AlGaN/GaN high electron mobility transistor failure physics and reliability, focusing on mechanisms affecting the gate-drain edge, where maximum electric field and peak temperatures are reached. Physical effects at the origin of device degradation (inverse piezoelectric effect, time-dependent trap formation and percolative conductive paths formation, and electrochemical AlGaN and GaN degradation) are discussed on the basis of literature data and unpublished results. Thermally activated mechanisms involving metal-metal and metal-semiconductor interdiffusion at the gate Schottky junction are also discussed. [ABSTRACT FROM AUTHOR]

Reverse-bias stress testing has been applied to a large set of more than 50 AlGaN/GaN high electron mobility transistors, which were fabricated using the same process but with different values of the AlN mole fraction and the AlGaN barrier-layer thickness, as well as different substrates (SiC and sapphire). Two sets of devices having different defect types and densities, related to the different growth conditions and the choice of nucleation layer, were also compared. When subjected to gate–drain (or gate-to-drain and source short-circuited) reverse-bias testing, all devices presented the same time-dependent failure mode, consisting of a significant increase in the gate leakage current. This failure mechanism occurred abruptly during step-stress experiments when a certain negative gate voltage, or “critical voltage,” was exceeded or, during constant voltage tests, at a certain time, defined as “time to breakdown.” Electroluminescence (EL) microscopy was systematically used to identify localized damaged areas that induced an increase of gate reverse current. This current increase was correlated with the increase of EL intensity, and significant EL emission during tests occurred only when the critical voltage was exceeded. Focused-ion-beam milling produced cross-sectional samples suitable for electron microscopy observation at the sites of failure points previously identified by EL microscopy. In high-defectivity devices, V-defects were identified that were associated with initially high gate leakage current and corresponding to EL spots already present in untreated devices. Conversely, identification of defects induced by reverse-bias testing proved to be extremely difficult, and only nanometer-size cracks or defect chains, extending vertically from the gate edges through the AlGaN/GaN heterojunction, were found. No signs of metal/semiconductor interdiffusion or extended defective areas were visible. The weak dependence on AlGaN properties, the strong process dependence, the time dependence, and the features of the localized damage identified by EL and electron microscopy suggest a multistep failure mechanism initiated by a process-induced weakness of the gate Schottky junction, which enhances current injection into pre-existing defects. As a result, further defects are generated or activated, eventually resulting in a percolation conductive path and permanent damage. A low-impedance path between the device gate and the channel is formed, increasing gate leakage current and possibly resulting in device burnout. [ABSTRACT FROM PUBLISHER]

An analysis of the reliability of GaN high-electron-mobility transistors during dc and RF stress tests is presented. Competing degradation mechanisms have been observed during RF operation, demonstrating the dependence of device reliability on device RF driving conditions. DC tests revealed only one degradation pattern related to defect formation at the high-electric-field region of the gate contact. RF signals, however, allow for other physical phenomena to take place before the said defect formation. Electron injection on the gate–drain region decreases the electric field value, thus counteracting the electric-field-induced defect formation at the gate edge. [ABSTRACT FROM PUBLISHER]

In this paper, an extensive description of the main characteristics and possible applications of a double-halo metal–oxide–semiconductor (MOS) device is presented. In particular, the details concerning the prototype fabrication through a standard complementary MOS (CMOS) process and the obtained experimental results are reported. Extensive numerical device simulation has been carried out in order to deeply understand the new structure. Furthermore, to gain insight on the device behavior, an electrical model to be used in SPICE-like circuit simulation tools has been developed and verified. As shown by our analysis, digital integrated circuits employing the new technology introduce, with respect to standard CMOS ones, a drastic reduction of both the device number and the parasitic capacitances, leading to a significant improvement of the circuit performance. [ABSTRACT FROM AUTHOR]

This paper presents a fast methodology for the investigation of trapping and hot-electron effects in GaN-based high-electron mobility transistors (HEMTs). The presented method is based on pulsed ID–VG measurements and electroluminescence characterization and provides a rapid and effective evaluation of the following: 1) the presence of traps in the region under the gate; 2) trapping phenomena occurring in the gate–drain access region; 3) the role of traps in limiting the maximum gate–drain electric field and the equivalent electron temperature. The method is validated by means of a split-wafer experiment carried out on GaN-based HEMTs with different gate materials with and without passivation. [ABSTRACT FROM PUBLISHER]

A novel field-effect device for high-density integrated circuits has been developed and manufactured. Numerical device simulations have also been carried out in order to deeply investigate the new structure. Such field-effect device is able to perform simultaneously the functions of two traditional field-effect transistors (e.g. a nMOS and a pMOS), working as one or as the other according to the voltage applied to the gate terminal. Combinational and sequential circuits employing the new technology introduce, with respect to the standard CMOS ones, a drastic reduction of both required devices number and associated parasitic capacitances. This leads to a significant increase of the circuit speed. Furthermore, the IC circuits obtained with these novel devices are fully compatible with standard CMOS technology and fabrication processes. [ABSTRACT FROM AUTHOR]

This letter describes an extensive analysis of the time- and field-dependent trapping processes that occur in GaN-based gate injection transistors exposed to high drain voltage levels. Results indicate that—even if the devices do not suffer from current collapse—continuous exposure to high drain voltages can induce a remarkable increase in the on-resistance (Ron). The increase in Ron can be recovered by leaving the device in rest conditions: Temperature-dependent analysis indicates that the activation energy of the detrapping process is equal to 0.47 eV. By time-resolved electroluminescence characterization, we show that this effect is related to the capture of electrons in the gate–drain access region. Finally, we show that charge emission can be significantly accelerated through the injection of holes from the gate. [ABSTRACT FROM AUTHOR]

A multifunctional field-effect transistor (FET) for the manufacturing of high-density integrated circuits (ICs) has been developed and fabricated. Furthermore, an extensive numerical device simulation campaign has been carried out in order to characterize the new structure. Such device is a metal–oxide–semiconductor (MOS) FET that simultaneously performs the functions of two traditional FETs (an n-channel MOS and a p-channel MOS), working as one or as the other according to the voltage applied to the gate's terminal. Combinational and sequential circuits employing the new technology introduce, with respect to the standard complementary MOS (CMOS) ones, a drastic reduction of both the required device number and the parasitic capacitances. This leads to a significant increase in the circuit's speed. Furthermore, the ICs obtained with these transistors are fully compatible with the standard CMOS technology and fabrication process. [ABSTRACT FROM PUBLISHER]