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Recent developments in medium-voltage (MV) silicon and silicon carbide (SiC) power semiconductor devices are challenging state-of-the-art converter and auxiliary power supply (APS) designs. The APS is an important converter component, which energizes the gate-drive units and, therefore, has an influence on the overall reliability and efficiency of the converter system. There has, however, been comparably little research on how the APS of high-power converter submodules can be realized, in particular, for high-voltage applications. New, or improved, solutions may build on state-of-the-art topologies in the near future, but utilize MV SiC technology in the APS circuit itself to enable improved efficiency, reliability, simplicity, and compactness. Externally-fed APS concepts could provide several further advantages. Their various benefits on converter and system level may enable them to be a competitive solution for future APS concepts. Especially, light-based power supply systems are considered most useful since they offer extreme voltage isolation capability and immunity to electromagnetic interference. This article presents a review of the wide range of solutions for APSs, possible implementation options, and the most important design considerations. The different solutions are evaluated in a qualitative fashion, providing an overview of available APS concepts with regard to the requirements for high-power converter applications. [ABSTRACT FROM AUTHOR]

In this paper, a new low-loss turn-on concept for the silicon insulated-gate bipolar transistor (Si-IGBT) in combination with silicon p-i-n diode is presented. The concept is tailored for two-level motor converters in the 100 kW to 1 MW range under the constraint that the output voltages slopes are limited in order to protect the motor windings. Moreover, analyses of the IGBT turn-on and diode reverse recovery voltage slopes are presented concluding that the diode reverse recovery is the worst case. The concept includes a low-cost measurement of the free-wheeling diode current and temperature by the gate driver without necessity of acquiring this information from the converter control board. By using this concept, the output dv/dt at the diode turn-off can be kept approximately constant regardless of the commutated current and junction temperature. Hence, the switching losses could be decreased for the currents and temperatures where the voltage slopes are lower when using a conventional gate driver optimized for the worst case. Moreover, results are shown for one such power semiconductor, showing a total switching loss reduction of up to 28% in comparison with a gate driver without current and temperature measurement. Finally, this concept is particularly suitable for high power semiconductor modules in half-bridge configuration which are recently proposed by several suppliers. [ABSTRACT FROM AUTHOR]

An experimental analysis of the behavior under short-circuit conditions of three different silicon-carbide (SiC) 1200-V power devices is presented. It is found that all devices take up a substantial voltage, which is favorable for detection of short circuits. A transient thermal device simulation was performed to determine the temperature stress on the die during a short-circuit event, for the SiC MOSFET. It was found that, for reliability reasons, the short-circuit time should be limited to values well below Si IGBT tolerances. Guidelines toward a rugged design for short-circuit protection (SCP) are presented with an emphasis on improving the reliability and availability of the overall system. A SiC device driver with an integrated SCP is presented for each device-type, respectively, where a short-circuit detection is added to a conventional driver design in a simple way. The SCP driver was experimentally evaluated with a detection time of 180 ns. For all devices, short-circuit times well below 1 \upmu\texts were achieved. [ABSTRACT FROM AUTHOR]

This paper presents the design process of a 312-kVA three-phase silicon carbide inverter using ten parallel-connected metal–oxide–semiconductor field-effect-transistor power modules in each phase leg. The design processes of the gate-drive circuits with short-circuit protection and power circuit layout are also presented. Measurements in order to evaluate the performance of the gate-drive circuits have been performed using a double-pulse setup. Moreover, electrical and thermal measurements in order to evaluate the transient performance and steady-state operation of the parallel-connected power modules are shown. Experimental results showing proper steady-state operation of the power converter are also presented. Taking into account measured data, an efficiency of approximately 99.3% at the rated power has been measured for the inverter. [ABSTRACT FROM PUBLISHER]

A high-voltage tapped-inductor buck converter utilizing a novel autonomous high-voltage valve is presented in this paper. Its application as auxiliary power supply for high-power cascaded-converter submodules is discussed, followed by a presentation of the most challenging problems in designing a low-power high-voltage step-down converter. The TI-buck converter topology is analyzed, which together with the novel autonomous high-voltage valve overcomes most of the problems. Analytical expressions describing the operation as well as circuit simulations are presented. Finally, an experimental evaluation of a 3-kV 70-W prototype converter utilizing the proposed autonomous high-voltage valve with series-connected super-junction MOSFETs is presented. [ABSTRACT FROM PUBLISHER]

A circuit solution to the normally-ON property of the normally-ON silicon carbide junction field-effect transistor, namely the self-powered gate driver, has been recently proposed. This letter sheds some light on the design process of the self-powered gate driver concept as well as limitations from the system perspective. It is experimentally shown that the parameters of the self-powered gate driver must be chosen taking into account a tradeoff between a fast response and stable operation of the driver. Moreover, the influence of the shoot-through current in the fast activation of the self-powered gate driver is also presented. [ABSTRACT FROM AUTHOR]

Operation of parallel-connected 4H-SiC vertical junction field effect transistors (VJFETs) from SemiSouth is modeled using numerical simulations and experimentally verified. The unbalanced current waveforms of parallel-connected VJFETs are investigated with respect to the spread in the critical parameters of the device structure and to the influence of the parasitic inductances in the measurement circuit. The device structures are reconstructed based on scanning electron microscopy (SEM) analysis, electrical characterization, and device simulations. The doping concentration and profile depth of a p-grid formed by angular implantation are studied as main contributors that influence the variation of the on-state characteristics, and the threshold voltage of the experimental devices. It has been shown elsewhere that similar differences in p-grid also lead to differences in gate-source breakdown voltage. The switching performance of the parallel-connected JFETs is measured using single and double gate drivers in a double-pulse test and compared with simulations. The switched current and voltage waveforms from measurements are reproduced in simulation by introducing the parasitics. From the analysis, it is found that reasonable differences in doping levels and profiles of the p-grid give rise to significant differences in device parameters. However, even with these parameter differences and circuit asymmetries, it is possible to successfully operate parallel-connected VJFETs of this type. [ABSTRACT FROM AUTHOR]

Silicon Carbide high-power modules populated with several parallel-connected junction field-effect transistors must be driven properly. Parasitic elements could act as drawbacks in order to achieve fast and oscillation-free switching performance, which are the main goals. These two requirements are related closely to the design of the gate-drive unit, and they must be kept under certain limits when high efficiencies are targeted. This paper deeply investigates several versions of gate-drive units and proposes a dual-function gate-drive unit which is able to switch the module with an acceptable speed without letting the current suffer from significant oscillations. It is experimentally shown that turn-on and turn-off switching times of approximately 130 and 185 ns respectively can be reached, while the magnitude of the current oscillations is kept at an adequate level. Moreover, using the proposed gate driver an efficiency of approximately 99.7% is expected for a three-phase converter rated at 125 kVA and having a switching frequency of 2 kHz. [ABSTRACT FROM AUTHOR]

The very low on-state resistance, the voltage-controlled gate, and the relative simplicity of fabrication of the normally ON silicon carbide junction field-effect transistor (JFET) make this device the most important player among all state-of-the-art silicon carbide transistors. However, the normally ON nature counts as the main factor which keeps this device far from being considered as an alternative to the silicon insulated-gate bipolar transistor. A self-powered gate driver without external power supply for normally ON silicon carbide JFETs is presented in this paper. The proposed circuit is able to handle the short-circuit currents when the devices are subjected to the dc-link voltage by utilizing the energy associated with this current. On the other hand, it supplies the necessary negative gate-source voltage during the steady-state operation. A detailed description of the operating states in conjunction with a theoretical analysis of the proposed self-powered gate driver is presented. The first part of the experimental investigation has been performed when the proposed circuit is connected to a device which is directly subjected to the dc-link voltage. The second set of measurements were recorded when the self-powered gate-driver was employed as the driver of normally ON components in a half-bridge converter. From the experimental results, it is shown that the short-circuit current is cleared within approximately 20 μs after the dc-link voltage is applied, while the power consumption when all devices are kept in the OFF state equals 0.37 W. Moreover, it is experimentally shown that the proposed gate driver can properly switch when it is employed in a half-bridge converter. Finally, limitations regarding the range of the applications where the self-powered gate drive can efficiently operate are also discussed. [ABSTRACT FROM AUTHOR]

State-of-the-art silicon carbide switches have current ratings that are not sufficiently high to be used in high-power converters. It is, therefore, necessary to connect several switches in parallel in order to reach sufficient current capabilities. An investigation of parallel-connected normally ON silicon carbide JFETs is presented in this paper. The device parameters that play the most important role for the parallel connection are the pinch-off voltage, the gate–source reverse breakdown voltage, the spread in the on-state resistances, and the variations in static transfer characteristics of the devices. Moreover, it is experimentally shown that a fifth factor affecting the parallel connection of the devices is the parasitic inductances of the circuit layout. The temperature dependence of the gate–source reverse breakdown voltages is analyzed for two different designs of silicon carbide JFETs. If the spread in the pinch-off and gate–source reverse breakdown voltages is sufficiently large, there might be no possibility for a stable off-state operation of a pair of transistors without forcing one of the gate voltages to exceed the breakdown voltage. A solution to this problem using individual gate circuits for the JFETs is given. The switching performance of two pairs of parallel-connected devices with different combinations of parameters is compared employing two different gate-driver configurations. Three different circuit layouts are considered and the effect of the parasitic inductances is experimentally investigated. It is found that using a single gate circuit for the two mismatched JFETs may improve the switching performance and therefore the distribution of the switching losses significantly. Based on the measured switching losses, it is also clear that regardless of the design of the gate drivers, the lowest total switching losses for the devices are obtained when they are symmetrically placed. [ABSTRACT FROM AUTHOR]