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Your search keyword '"Pan, Li-Hong"' showing total 2 results
Start Over Author "Pan, Li-Hong" Topic logic gates
2 results on '"Pan, Li-Hong"'

1. Transistor Mismatch Properties in Deep-Submicrometer CMOS Technologies.

Author

Yuan, Xiaobin, Shimizu, Takashi, Mahalingam, Umashankar, Brown, Jeffrey S., Habib, Kazi Z., Tekleab, Daniel G., Su, Tai-Chi, Satadru, Sarkar, Olsen, C. Michael, Lee, Hyunwoo, Pan, Li-Hong, Hook, Terence B., Han, Jin-Ping, Park, Jae-Eun, Na, Myung-Hee, and Rim, Ken

Subjects
FIELD-effect transistors, COMPLEMENTARY metal oxide semiconductors, MICROMETERS, DATA analysis, ELECTRIC potential, SILICON oxide
Abstract

Transistor mismatch data and analysis from poly/SiON and high-k/metal-gate (HKMG) bulk CMOS technologies are presented. It is found that the traditional mismatch figure of merit from the Pelgrom plot (AVT) continuously scales down as technology advances. Furthermore, the AVT values for both nFET and pFET in the HKMG technology are significantly reduced from poly/SiON technologies. By normalizing the mismatch data against electrical oxide thickness (TINV), threshold voltage (VTH), and effective work function, a direct comparison of the mismatch data from various technologies is made. The differences in nFET and pFET mismatch behaviors in both poly/SiON and HKMG technologies are discussed in detail. Correlation between transistor VTH mismatch and flicker noise variation is observed in both poly/SiON and HKMG technologies. Finally, it is quantitatively demonstrated that effective work function variation does not generate significant VTH variability in the present HKMG technology. [ABSTRACT FROM AUTHOR]

Published
2011
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2. Gate Stack Resistance and Limits to CMOS Logic Performance.

Author

Wachnik, Richard A., Lee, Sungjae, Pan, Li-Hong, Li, Hongmei, Lu, Ning, Wang, Jing, Bernicot, Christophe, Bingert, Raphael, Randall, Mai, Springer, Scott K., and Putnam, Christopher S.

Subjects
LOGIC circuits, COMPLEMENTARY metal oxide semiconductor performance, SILICON oxynitride, ELECTRIC resistance measurement, NOISE measurement
Abstract

The input resistance of CMOS circuits is a measurable limit on the performance of typical static CMOS logic gates. A survey of measured data from five generations of CMOS technology including polysilicon oxynitride gate first stacks (P-SiON), high K metal gate first stacks (GF), and high K replacement metal gate stacks (RMG) shows a trend of increasing gate resistance. We show DC and RF measurements may be analyzed to determine horizontal and vertical components of gate resistance in terms of scalable parameters and the sum of these components may be represented by a compact scalable equation representing total gate resistance. Measured noise data supports this decomposition. Gate resistance increases at advanced nodes and affects typical logic performance of a 20 nm replacement gate technology. [ABSTRACT FROM AUTHOR]

Published
2014
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