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This letter proposes a memory cell, denoted by 1F-1 T, consisting of a ferroelectric field-effect transistor (FeFET) cascaded with another current-limiting transistor (T). The transistor reduces the impact of drain current ($I_{d}$) variations by limiting the on-state current in FeFET. The experimental data from our 28 nm high-k-metal-gate (HKMG) based FeFET calibrates and simulates the memory arrays. The simulation indicates a significant improvement in bit-line (BL) current ($I_{BL}$) variation and the accuracy of vector-matrix multiplication of the 1F-1 T memory array. The system-level in-memory computing simulation with 1F-1T synapses shows an inference accuracy of 97.6% for the MNIST hand-written digits with multi-layer perceptron (MLP) neural networks. [ABSTRACT FROM AUTHOR]

In this work, we report that the VTH stability in p-GaN power HEMTs under a high dVg/dt event is highly correlated with the capacitance for the first time. The different dVg/dt event is performed by using fast sweep characterization with sweeping time (tsweep) varied from 10ms to $25~\mu \text{s}$. As the tsweep is decreased, i.e., high dVg/dt, p-GaN HEMTs show a negative VTH shift and a high measured gate current. The higher measured gate current is mainly due to the displacement current with respect to a high dVg/dt. To further understand the impacts of capacitance on VTH stability, p-GaN power HEMTs are connected with different additional capacitance (Cadditional) between gate-to-source terminals. The results indicate that the negative VTH shift and the gate current are highly correlated with the Cadditional, i.e., a large negative VTH shift and a high measured gate current in the device with a large Cadditional, suggesting that the charging capacitance caused by the displacement current during a high dVg/dt event can influence the VTHstability. Therefore, the optimization of the capacitance is crucial to improve the VTH stability during a high-speed gate operation. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate enhancement-mode regrown p-GaN gate devices with high threshold voltage as well as a robust forward time-dependent gate breakdown (TDGB) stability. The regrown p-GaN gate HEMTs are fabricated with two different AlGaN barriers. Devices with 16nm Al0.235 Ga0.765 N yield a $\text{V}_{\text {TH}}$ of 1.5V and a high threshold voltage ($\text{V}_{\text {TH}}$) of 2.7V is observed for 7nm AlGaN along with a gate breakdown voltage of more than 10V. Lastly, the regrown p-GaN gate HEMTs with 7nm AlGaN barrier demonstrate an operating $\text{V}_{\text {G}}$ of 7.46V and 7V for 1% failure rate of 10-year lifetime at 150°C and 25°C, which is amongst the highest values compared to the reported literature for regrown p-GaN gate HEMTs. [ABSTRACT FROM AUTHOR]

This work demonstrates a trench isolated lateral double-implanted MOSFET (LDMOS) on Si-face in 4H-silicon carbide (SiC). A device $\vphantom {_{\int _{}}}$ where ${L}_{\textit {ch}} = 0.8\,\,\mu \text{m}$ and ${L}_{d} = 12\,\,\mu \text{m}$ shows an ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ of 22.9 $\text{m}\Omega $ cm2 at a ${V}_{\text {GS}}$ of 20 V and a breakdown voltage (BV) of 1100 V, corresponding to a high BV2/ ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ of 55.5 MW/cm2. Devices that have different ${L}_{\text {ch}}$ , ${L}_{\text {JFET}}$ , ${L}_{d}$ , and P-top dose values are measured in order to investigate the effects of geometry on the static performance. Operations at 150 °C are measured to evaluate the temperature performance. Gate charge waveforms are also measured in order to include the switching performance in the evaluation. The ${R}_{ \mathrm{\scriptscriptstyle ON}} \times {Q}_{G}$ and ${R}_{ \mathrm{\scriptscriptstyle ON}} \times {Q}_{\text {GD}}$ values are calculated as 17.7 and $9.0~\Omega $ nC, respectively, which are promising for power-integrated circuit applications. [ABSTRACT FROM AUTHOR]

In this article, a physics-based analytical model which considers the channel charge (Qch) for enhancement-mode p-GaN power high-electron-mobility transistors (HEMTs) is developed. First, by considering the same dynamic channel charge (dQch) for the Schottky/p-GaN junction capacitance (Cj,Sch) and the p-i-n-junction capacitance (Cp-i-n), due to the p-GaN/AlGaN junction and two-dimensional electron gas (2DEG) charge, the analytical formula to calculate the voltage drop in the p-GaN layer (VpGaN) is presented. Second, by implementing the analytical formulae in the advanced SPICE model (ASM) GaN model, the proposed physics-based model reliably fits the measured C – V and I – D – V – G characteristics of the samples under different processing conditions. This provides significant insight regarding the Mg concentration, the voltage drop at the Schottky metal/p-GaN junction (Vj,Sch), and the voltage drop at the p-GaN/AlGaN junction (Vp-i-n). Finally, the I – D – V – G and I – D – V – D characteristics of enhancement-mode p-GaN power HEMTs are modeled, displaying good agreement with the experimental data. [ABSTRACT FROM AUTHOR]

In this letter, a fully transparent AlGaN/GaN HEMT (FT-HEMT) using indium-tin-oxide (ITO) as a transparent electrode is fabricated. The n-ohmic contacts are formed based on a Si-implant process using a deposited ITO rather than the conventional alloyed metal stacks. Following a post-annealing process at 600°C, the field-effect mobility and the maximum current density for an FT-HEMT were 1004 cm2/ $\text{V}{\cdot }\text{s}$ and 179 mA/mm, respectively. Furthermore, the measured transmittance for a fabricated chip in the visible range of 400 - 700 nm was greater than 70%, which is almost the same as an as-grown GaN-on-sapphire substrate. These results show that, by using this approach, an FT-HEMT that has superior electronic properties, such as high mobility and high output current, can be realized, and show great promise for applications in transparent and/or flexible electronics, as well as other optoelectronic devices. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate the use of a machine learning (ML)-based statistical approach to model and analyze the impact of the fabrication processes on the threshold voltage in recessed gate AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors. First, we employ a ML-based Tikhonov regularization approach using the input of 19 different processing splits to generate a multivariable analytical equation that considers four critical processing parameters, such as the remaining AlGaN depth, ex-situ wet clean, in-situ plasma, and gate dielectric. Furthermore, the artificial neural network-based approach, which cannot be used to further analyze the impact of the process, is implemented for the comparison. Second, the results from this analytical equation show a nice agreement with the measured threshold voltage, indicating a successful correlation between the processing parameters and the threshold voltage. Finally, the impact of each process on the threshold voltage can be analyzed through the coefficient value related to each process, which can be a useful guidance for the device optimization toward the targeted performance. [ABSTRACT FROM AUTHOR]

This article reports that the enhanced forward gate bias time-dependent dielectric breakdown (TDDB) reliability and interface quality are achieved in 5-nm ferroelectric Hf0.5Zr0.5O2 (HZO) technologies by using the NH3 plasma interfacial layer (IL) treatment and microwave annealing (MWA). An orthorhombic crystalline phase is observed in the annealed HZO film with NH3 plasma IL treatment and MWA, and NH3 plasma IL treatment can suppress Hf/Zr interdiffusion. Metal-oxide-semiconductor capacitors (MOSCAPs) subjected to NH3 plasma IL treatment and 2100-W MWA also have a higher extrapolated operating voltage for a ten-year lifetime at 0.01% failure and lower interface state density (Dit) compared to the devices subjected to only rapid thermal annealing (RTA) at 600 °C. Therefore, NH3 plasma treatment and MWA are effective for improving the TDDB reliability and interface quality of the ultrathin ferroelectric HZO. [ABSTRACT FROM AUTHOR]

In this letter, we analyzed the gate capacitance characteristics in p-GaN gate/AlGaN/GaN heterostructures by using a two-junction capacitor model. First, we have observed that the C – V behavior depends on the different processing conditions of the p-GaN gate. Second, a two-junction capacitor model considering a series connection of the Schottky metal/p-GaN junction capacitor and the AlGaN barrier capacitor is proposed to explain this C – V behavior. Based on this model, the junction capacitance has an influence on the total capacitance value under a high gate bias due to the Schottky metal/p-GaN junction. Furthermore, the Mg-concentration and hole density can be extracted. The extracted hole density is consistent with the results obtained by Hall measurements. [ABSTRACT FROM AUTHOR]

In this paper, fully recessed-gate GaN MISFETs with two different gate dielectrics, i.e., plasma-enhanced atomic layer deposition (PEALD) SiN and ALD Al2O3 gate dielectric, are used to study the origin of positive bias temperature instability (PBTI). By employing a set of dedicated stress-recovery tests, we study PBTI during the stress and relaxation. Hence, a defect band model with different distributions of defect levels inside the gate dielectric is proposed, which can excellently reproduce the experimental data and provide insightful information about the origin of PBTI in GaN MISFETs. The results indicate that the serious PBTI in the device with PEALD SiN is mainly due to a wide distribution of defect levels ( \sigma \sim 0.67 eV), centered below the conduction band of GaN ( E_{C} -0.05 eV), and can be easily accessed by the channel carriers already at a low-gate voltage. On the other hand, ALD Al2O3 gate dielectric shows a narrower distribution of defects ( \sigma \sim 0.42$ eV), which are far from the conduction band of GaN ( E_{C} +1.15 eV). This observations explain the improved PBTI reliability observed in devices with ALD Al2O3. [ABSTRACT FROM AUTHOR]

This letter reports an in-depth study of the negative threshold voltage instability in GaN-on-Si metal-insulator–semiconductor high electron mobility transistors with partially recessed AlGaN. Based on a set of stress/recovery experiments carried out at several temperatures, we demonstrate that: 1) operation at high temperatures and negative gate bias (−10 V) may induce a significant negative threshold voltage shift, that is well correlated to a decrease in on-resistance; 2) this process has time constants in the range between 10–100 s, and is accelerated by temperature, with activation energy equal to 0.37 eV; and 3) the shift in threshold voltage is recoverable, with logarithmic kinetics. The negative shift in threshold voltage is ascribed to the depletion of trap states located at the SiN/AlGaN interface and/or in the gate insulator. [ABSTRACT FROM PUBLISHER]

This letter demonstrates that GaN-based MIS-HEMTs submitted to stress with high-temperature, high drain bias, and constant source current (HTSC stress) may show degradation modes that are not detectable during standard high temperature reverse bias (HTRB) stress. Based on a number of stress/recovery experiments, we demonstrate the following novel results: 1) the combined presence of high drain bias and constant drain–source current (HTSC stress) can lead to a significant increase in ON-resistance ( R\mathrm{\scriptscriptstyle ON} ) that is not detected under conventional HTRB stress; 2) R\mathrm{\scriptscriptstyle ON} increases without changes in the threshold voltage, indicating that charge trapping takes place in the access regions, and not under the gate; 3) the R\mathrm{\scriptscriptstyle ON} increase has a monotonic dependence on the source current flowing during stress; and 4) for the same stress current level, the R\mathrm{\scriptscriptstyle ON} increase has a negative dependence on temperature. The strong correlation between R\mathrm{\scriptscriptstyle ON} increase and source current and the negative temperature coefficient strongly support the hypothesis that trapping originates from the injection of hot electrons toward the gate–drain access region. [ABSTRACT FROM PUBLISHER]

In this paper, we review and add additional data and understandings on our findings on the two most common failure modes of GaN-based HEMTs: 1) permanent gate leakage current increase and 2) output current drop. We suggested that they have different origins and one is not necessarily correlated to the other. Yet, they can both concur to the device degradation. First, we demonstrate that the phenomenon of gate leakage current increase has a voltage-accelerated degradation kinetic. Therefore, the identification of the critical voltage for leakage increase is meaningless. We demonstrate that the time-to-breakdown tBD data are Weibull distributed and we prove that they represent intrinsic failures. According to our data, this phenomenon is not related to the inverse piezoelectric effect. Finally, a new degradation model for the gate leakage current increase based on the percolation path theory is proposed. Second, we show that the permanent output current drop is a consequence of the relaxation of AlGaN layer. This occurs by means of formation of crystallographic defects as described by the inverse piezoelectric degradation model. Finally, we show an excellent stability of devices with reduced Al content in the AlGaN barrier, proving the crucial role of strain in the reliability of AlGaN/GaN HEMTs. [ABSTRACT FROM AUTHOR]

In this letter, we studied the forward bias gate breakdown mechanism on enhancement-mode p-GaN gate AlGaN/GaN high-electron mobility transistors. To the best of our knowledge, it is the first time that the temperature dependence of the forward gate breakdown has been characterized. We report for the first time on the observation of a positive temperature dependence, i.e., a higher temperature leads to a higher gate breakdown voltage. Such unexpected behavior is explained by avalanche breakdown mechanism: at a high positive gate bias, electron/hole pairs are generated in the depletion region at the Schottky metal/p-GaN junction. Furthermore, at a high gate bias but before the catastrophic gate breakdown, a light emission was detected by a emission microscopy measurement. This effect indicates an avalanche luminescence, which is mainly due to the recombination of the generated electron/hole pairs. [ABSTRACT FROM PUBLISHER]