Search

Silicon bandgap limits the reduction of operation voltage when downscaling device sizes. This increases the electrical field within-a-device and hot carrier aging (HCA) is becoming an important reliability issue again for some CMOS technologies. For nanodevices, there are a number of challenges for characterizing their HCA: the random charge–discharge of traps in gate dielectric causes “within-a-device-fluctuation (WDF),” making the parameter shift uncertain after a given HCA. This can introduce errors when extracting HCA time exponents and it will be shown that the lower envelope of the WDF must be used. Nanodevices also have substantial device-to-device variation (DDV) and multiple tests are needed for evaluating their standard deviation ( $\sigma )$ and mean value ( $\mu $ ). Repeating the time-consuming HCA tests is costly and a voltage-step-stress method is applied to reduce the number of tests by 80%. For a given number of devices under tests (DUTs), there is a little information on the accuracy of the extracted $\sigma $ and $\mu $ . We will develop a method to provide this information, based on the defect-centric model. For 40 DUTs with an average of ten traps per device, the extracted $\mu $ and $\sigma $ has an accuracy of ±14% and ±24%, respectively, with a 95% confidence. [ABSTRACT FROM PUBLISHER]

The access transistor of SRAM can suffer both positive bias temperature instability (PBTI) and hot carrier aging (HCA) during operation. The understanding of electron traps (ETs) is still incomplete and there is little information on their similarity and differences under these two stress modes. The key objective of this paper is to investigate ETs in terms of energy distribution, charging and discharging properties, and generation. We found that both PBTI and HCA can charge ETs which center at 1.4 eV below conduction band ( Ec ) of high-k dielectric, agreeing with theoretical calculation. For the first time, clear evidences are presented that HCA generates new ETs, which do not exist when stressed by PBTI. When charged, the generated ETs’ peak is 0.2 eV deeper than that of preexisting ETs. In contrast with the power law kinetics for charging the preexisting ETs, filling the generated ETs saturates in seconds, even under an operation bias of 0.9 V. ET generation shortens device lifetime and must be included in modeling HCA. A cyclic and antineutralization ETs model is proposed to explain PBTI and HCA degradation, which consists of preexisting cyclic ETs, generated cyclic ETs, and antineutralization ETs. [ABSTRACT FROM AUTHOR]

Defects in gate oxide cause breakdown and shorten device lifetime. Early works mainly focused on generation process that converts a precursor into a charged defect. Although it can be neutralized through “recovery,” the defect is still there and will recharge when resuming stress. Recently, we have shown that this is not always the case and some defects can be lost, but a detailed investigation is missing. The central objective of this work is to accurately define and extract the loss, separate it from slowdown, and evaluate their enhancement of device lifetime. Loss is defined as elimination of defects, while slowdown means that recharging a “hardened” precursor takes longer than charging a fresh one. Clear evidences show that losses originate from permanent components, i.e., generated interface states and antineutralization positive charges, while slowdown occurs to both permanent and recoverable components. Loss is thermally accelerated, but slowdown of recoverable component is not. This improved understanding adds slowdown and losses to the existing framework for defects. For the first time, we report that the losses and slowdown enhance device lifetime by a factor of 2.6–4.3, for an allowed threshold voltage shift of 20–45 mV. [ABSTRACT FROM AUTHOR]

Interface states play an important role in the performance of MOSFETs, and previous works only addressed the states within band gap. The implicit assumption is that the states beyond band gap (SBBs) are negligible, but there is no experimental evidence supporting it. Because of a lack of techniques for characterizing SBBs, there is hardly any information available. The central objective of this paper is to develop a technique for evaluating SBBs and to show the impact of SBBs on mobility evaluation. For the first time, the pulse capacitance–voltage has been used to extract SBBs quantitatively. It is found that SBBs can reach the order of \10^13 \ \cm^-2\cdot\eV^-1 beyond both conduction- and valence-band edges on a fresh MOSFET. The conventional split C– V technique ignores the SBBs, and this can lead to an underestimation of carrier mobility over 30%. Using the newly developed technique as a tool, the impact of nitridation of Hf-based dielectric stacks on carrier mobility is assessed. As nitrogen density increases, the apparent reduction of carrier mobility observed by early works originates from the higher SBBs. Once SBBs are taken into account, nitridation does not degrade carrier mobility. The SBBs are sensitive to process conditions, and this paper opens the way for their minimization. [ABSTRACT FROM AUTHOR]

\Al2\O3 high- \kappa stack is a strong candidate as the dielectric layer in Flash memory cells for technology generations beyond sub-20 nm. In this paper, the cause of abnormal VTH/VFB shift at low operating electric fields is investigated, i.e., VTH/VFB reduces at low positive gate biases and increases at low negative gate biases. It is found that this instability does not originate from the electrons trapping/detrapping from the gate nor from the dielectric relaxation. For the first time, extensive experimental evidences show that this shift is caused by as-grown mobile charges in \Al2\O3 layers generated by postdeposition annealing at 1000 ^\circ\C or above. Its impacts on program/erase windows and read/pass disturbance in Flash memory cells are also evaluated. [ABSTRACT FROM PUBLISHER]

Characterizing interface states is a key task, and it typically takes seconds when conventional techniques, such as charge pumping (CP), are used. The stress-induced degradation can recover substantially during this time, and there is a need to improve the measurement speed. The central task of this work is to reduce the measurement time for interface states from seconds to microseconds to minimize the recovery. A fast single pulse CP (SPCP) technique is developed. By exploring the differences in the transient currents corresponding to the two edges of the gate pulse, the net charges pumped into devices can be obtained, and their saturation level is used to evaluate interface states. Unlike the conventional CP (CCP) method, the contribution of currents during the plateaus of gate pulse is excluded for SPCP, making it less vulnerable to the interferences of gate leakage and defects within dielectrics. For the first time, the SPCP allows the recovery of interface states being monitored with a time resolution in microseconds. The results show that the recovery of stress-induced interface states is substantial within 100 \mu\s, which would be missed if the CCP were used. [ABSTRACT FROM PUBLISHER]

Continuing CMOS performance scaling requires developing MOSFETs of high-mobility semiconductors and InGaAs is a strong candidate for n-channel. InGaAs MOSFETs, however, suffer from high densities of border traps, and their origin and impact on device characteristics are poorly understood at present. In this paper, the border traps in nMOSFETs with an In0.53Ga0.47As channel and Al2O3 gate oxide are investigated using the discharging-based energy profiling technique. By analyzing the trap energy distributions after charging under different gate biases, two types of border traps together with their energy distributions are identified. Their different dependences on temperature and charging time support that they have different physical origins. The impact of channel thickness on them is also discussed. Identifying and understanding these different types of border traps can assist in the future process optimization. Moreover, border trap study can yield crucial information for long-term reliability modeling and device time-to-failure projection. [ABSTRACT FROM AUTHOR]

High density of electron trapping in high- \kappa intergate dielectric (IGD) materials remains a major concern for planar memory cells with either poly-Si or hybrid floating gates (FGs). In this paper, for the first time, using the ultrafast I{-}V measurements, it is demonstrated that a significant portion of the P/E windows are actually contributed by electrons trapped initially in the high- \kappa$ IGD stacks during program/erase, and then discharged to FG or control gate during verification. More importantly, it is demonstrated, for the first time, that this fast charge transition can be suppressed using novel multilayer high- $\kappa$ IGD structures, and the fast window instability can be eliminated. [ABSTRACT FROM PUBLISHER]

Endurance is one of the key criteria for Flash memory technologies, particularly for the generations beyond 30 nm with high-\kappa materials. It is observed in this paper that the electron trapping in high-\kappa layers causes threshold-voltage window closure under dynamic program/erase cycling operations. This closure does not originate from the generation of new traps or from further trapping of electrons injected from the gate during erasing. By utilizing a recently developed multipulse technique, it is found that the energy distribution of the electron trapping in the high-\kappa layer significantly changes after cycling. Electron trapping at the deeper energy levels continuously increases as cycling proceeds, because it does not reach saturation within one programming pulse. The trapping in deep levels cannot be discharged under typical erase conditions, and an increase in deep-level trapping also causes a reduction of trapping at shallow levels. It is concluded that the window closure observed in this paper is caused by a combination of increased deep trapping after erasing and a reduction of shallow trapping after programming. [ABSTRACT FROM PUBLISHER]

A new discharge-based multipulse technique has been developed in this paper, which overcomes the shortcomings of the existing techniques, such as the charge pumping, charge injection and sensing, and two-pulse C–V techniques. It captures the energy signature for electron traps across high- \kappa materials and can be a useful tool for material selection during technology development. Trap distributions in \HfO2, \Al2\O3, and HfAlO have been compared to identify the effects of material variation. It is observed that hafnium gives the shallow traps at about 0.45 eV above the silicon conduction band bottom (Si ECB), and the deep traps at 0.8 eV below the Si ECB are caused by aluminum. HfAlO combines the features in \HfO2 and \Al2\O3. A peak near the Si ECB has been observed in all the three materials. [ABSTRACT FROM PUBLISHER]