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Secure deletion in flash-based storage is crucial for data security. However, existing secure deletion schemes for flash memory suffer from performance degradation and reliability issues and cannot provide secure deletion guarantees. Although emerging nonvolatile memory (NVM) allows in-place updates and provides high performance, it is unable to fully replace flash memory and, thus, cannot solve the secure deletion problem. In this article, we propose NVM-assisted secure deletion scheme for flash memory (NASA), a stale-free storage system that combines NVM and flash memory to provide immediate secure deletion without significant performance degradation in SSDs. NASA uses block erasure to provide secure deletion guarantees for flash memory and exploits NVM to conceal time-consuming erasure operations. We demonstrate that unless the unique characteristics of NVM are considered, schemes that merely implement existing approaches to secure deletion will end up with stale data replicas within their storage media. Moreover, we evaluate NASA with different real-world workloads and demonstrate that NASA increases the average latency by 0.01% compared to LRU and decreases 2.1% average latency over the FIFO caching policy. NASA is a novel storage system that provides strong secure deletion guarantees with high performance. [ABSTRACT FROM AUTHOR]

Most of current processing-in-memory (PIM) architectures are application specific, that is, they can only accelerate particular functions, e.g., matrix-vector dot product for neural network acceleration. However, practical applications usually involve various functions. In order to accelerate different functions, various accelerators, and dedicated circuits have been proposed. In this work, by exploring the similarities among some commonly used dedicated circuits, we adopt ferroelectric field-effect transistors (FeFETs) to build a reconfigurable multifunctional memory architecture named Re-FeMAT. Re-FeMAT is composed of multiple processing elements (PEs). Each PE is not only a nonvolatile memory array, but also can perform logic operations (i.e., the PIM mode), convolutions (i.e., the binary convolutional neural network and the convolutional neural network (CNN) acceleration mode) and content search (i.e., the ternary content-addressable memory (TCAM) mode) without changing the circuit structure. Re-FeMAT can support applications that require multiple functions. As an example, by configuring different PEs to different working modes and using a simulated annealing algorithm or a tabu search algorithm to optimize the task-PE assignment, Re-FeMAT can completely accelerate few-shot learning applications. Our simulation results based on a calibrated FeFET model show that the proposed Re-FeMAT architecture achieves better performance and power efficiency than the previous FeMAT architecture. Compared with FeFET-based single-functional circuits, though the power dissipation of Re-FeMAT is higher in some modes, the power-delay product is still smaller. Compared with a state-of-the-art FeFET-based multifunctional accelerator named attention-in-memory, Re-FeMAT achieves lower power, latency, and energy when accelerating a complete few-shot learning task. [ABSTRACT FROM AUTHOR]

We present the interfering True-random-number-generators (TRNG) composed of 2 parallel resistive-gate non-volatile memory cells. Both cells store closer but different resistance states. 2 cells output current flows separately, which are received concurrently by a current-reference sense amplifier (SA). The SA compares difference of received flows and then continues outputting the same bits if difference of current-flows remains stable. However, if randomness happens, levels of current flows from the cells are interlaced; the SA will output a flipped bit, which can be in analogy to gene mutation. So, we emulate mutation by the interfering TRNGs and propose an algorithm to implement emulator of mutation. The TRNGs are also qualified by cryptographic tests, including the Hamming distance, Hamming weight, auto-correlation, and tests of National Institute of Standards and Technologies. [ABSTRACT FROM AUTHOR]

Developing the multi-valued logic circuits, that can handle more data than the conventional binary logic circuits, is a promising strategy to break through the well-known Moore’s law. In this letter, we demonstrate quaternary logic circuits, for the first time, based on the four-level organic thin-film transistor nonvolatile memories (OTFT-NVMs) as the core components. High-performance four-level OTFT-NVMs are achieved, with the low programming/erasing voltages of ±15 V, high mobility up to 7.4 cm2/Vs, reliable endurance, and stable retention capabilities. By connecting the four-level OTFT-NVMs with a load resistance in the reasonable ways, we build the logic circuits to reliably perform quaternary logic operations of NOT, NAND and NOR, respectively. Our works lay the foundation to develop the novel quaternary integrated circuits in hardware. [ABSTRACT FROM AUTHOR]

2D materials exhibit unique electrical and mechanical properties, and therefore have been investigated extensively. One of their important applications is logic‐in‐memory, which can perform logic operations as well as store data. This makes it possible to overcome the intrinsic obstacles of the von Neuman computing architecture that uses separate processing and storage units. Herein, a two‐terminal self‐gating random‐access memory (SGRAM) based on partially aligned graphene/MoS2/h‐BN/graphene/h‐BN/Au heterostructures is proposed. One of the two electrodes acts as the drain as well as the gate electrodes; thus, the SGRAM exhibits both diode‐like behaviors and nonvolatile memory effects, allowing the construction of a simple crossbar array without a selector. The SGRAM crossbar array consisting of 2 × 2 cells is constructed and its random accessibility is verified by addressing each cell independently. In addition, reconfigurable AND/OR logic gates are implemented using the SGRAM array. Hence, it is demonstrated that SGRAMs are promising candidates for "Beyond von Neumann" computing architectures. [ABSTRACT FROM AUTHOR]

HfO2-based FeFET is a remarkably promising candidate among emerging memory technologies. Its manifold applications range from nonvolatile memory to neuromorphic computing. However, the memory window (MW) is limited, since the ferroelectric properties of HfO2 degrade with increased ferroelectric thickness. Recent developments in asymmetric double-gate FeFET with dual port boast of a large MW when read from the back gate (BG), compared with the front gate (FG). It has been predicted that this can qualify as an excellent candidate for multi-level-cell (MLC) storage due to its high MW. However, the variability of the intermediate threshold voltage (VTH) states must be within reasonable limits to enable error-free reliable operation. In this work, we have thoroughly investigated the variability of VTH states in dual-port FeFET due to the random spatial distribution of ferroelectric domains. We have also accounted for the conventional sources of device variations, such as random dopant fluctuation (RDF), metal work-function variation (WFV), and line edge roughness (LER). We show that as MW is amplified when reading from BG compared with FG, variability is also amplified, thereby restricting its usage to accommodate a higher number of states. Nevertheless, a key benefit of BG read stems from the ability to reduce the ferroelectric thickness (tFE) from 10 nm down to merely 3 nm, still retaining an MW of 2.7 V. Notably, reducing tFE makes it possible to operate the FeFET at a lower voltage (1.8 V instead of 4 V). This creates avenues for better compatibility with the existing VLSI designs and reliability enhancements. We demonstrate that the variations in VTH are reduced for BG read on reducing tFE, which allows us to hold the same number of states even at such a scaled thickness. Finally, we predict the maximum number of states (in terms of bits) that can be stored and read reliably in dual-port FeFET for FG read and BG read at nominal and scaled tFE. We demonstrate that dual-port FeFET with BG read and scaled tFE offers MLC storage of 3 bits. [ABSTRACT FROM AUTHOR]

The ferroelectric field-effect transistor (FEFET) is an emerging nonvolatile memory technology that can offer ultra-scalability, fast operation, and reduced power consumption. However, a limited understanding of FEFET physics poses challenges for optimum device design. In this article, we provide physical insights into the operation of FinFET-based FEFETs (FEFinFETs) using a phase-field framework built on time-dependent Landau–Ginzburg (TDGL) thermodynamic theory. We exploit the source–drain fringing field to stabilize a monodomain configuration in the OFF state of short channel FEFinFETs. Based on recent experiments, we first analyze the switching dynamics of FEFinFETs with low remnant polarization (${P}_{r}$) and high coercive field (${E}_{c}$) hafnium zirconium oxide (HZO) FE. We find that the switching in these FEFinFETs occurs via domain nucleation and growth from the gate metal edges at the source–drain spacers. We also show that a non-zero drain bias can be used for dynamically modulating the memory window (MW) of FEFinFET to lower its power consumption. Furthermore, we find the spacer permittivity to be a crucial design parameter to control the MW and show that a lower spacer permittivity can significantly increase the MW. Finally, we show that the commonly held idea that a large ${P}_{r}$ leads to a large MW is not always valid. For a large ${P}_{r}$ , the formation of multiple domains in the FE layer can lead to a significant reduction in the MW. In addition, these devices can suffer from low write endurance due to exposure of the interfacial oxide layer to high electric fields. [ABSTRACT FROM AUTHOR]

We demonstrate nonvolatile and area-efficient ternary content-addressable memories (TCAMs) featuring amorphous indium–gallium–zinc–oxide (a-IGZO) ferroelectric field-effect transistors (FeFETs) with excellent electrical characteristics. An extremely large sensing margin of the TCAM array is achieved due to the large current ON/OFF ratio ($I_{ \mathrm{\scriptscriptstyle ON}}/I_{ \mathrm{\scriptscriptstyle OFF}})$ of the a-IGZO FeFETs. Our HfxZr $_{\text {1-x}}\text{O}$ 2 (HZO)-based a-IGZO FeFETs have a metal–ferroelectric–metal–insulator–semiconductor (MFMIS) structure. By engineering the area ratio of the ferroelectric layer (${A}_{Fe}$) and the metal–oxide–semiconductor layer (${A}_{MOS}$), a large memory window (MW) of 2.9 V is realized. Reliability test results, including retention, endurance, and positive bias temperature instability, show long-term retention of more than ten years and high endurance of 108 cycles. In addition, by scaling the channel length down to 40 nm, ON current of $77 ~\mu \text{A}/ \mu \text{m}$ (${V}_{\mathrm{GS}} - {V}_{\mathrm{TH}}$ = 5 V and ${V}_{\mathrm{DS}}$ = 2 V) and ${I}_{ \mathrm{\scriptscriptstyle ON}} / {I}_{ \mathrm{\scriptscriptstyle OFF}}$ of more than eight orders can be obtained for the ultrascaled a-IGZO FeFETs while maintaining an MW of 2.8 V. [ABSTRACT FROM AUTHOR]

Neuromorphic computing has gained a considerable research interest due to its potential in realizing highly efficient parallel computations. However, the existing neuromorphic architectures face various drawbacks. In this study, we present an integrate-and-fire (I&F) neuron using a Li-based electrochemical random access memory (Li-ECRAM) to achieve exceptional area efficiency and low-power neuromorphic computing. The proposed Li-ECRAM neuron employs a significantly reduced number of transistors when compared to other novel nonvolatile memory-based I&F neurons due to linear current integration characteristics and a high linear conductance response to the input current. As the integration-type Li-ECRAM is linear, it eliminates the requirement of a nonlinear compensating circuit. Therefore, a Li-ECRAM-based neuron has a simple structure comprising Li-ECRAM, reset transistor, inverter, and pulse generator. Furthermore, we also evaluate the operation speed and energy consumption of the proposed neuron, demonstrating the potential for high-speed and low-power operation. The proposed neuron can be applied in large-scale neuromorphic hardware applications due to the scalability and low energy consumption of Li-ECRAM. [ABSTRACT FROM AUTHOR]

Deep neural network (DNN) inference and training produce a large amount of intermediate data. To achieve high energy efficiency, sufficient on-chip buffer is preferred to reduce the energy and time consuming off-chip DRAM access. However, SRAM buffer suffers from large area cost and high standby power due to its large cell size and high leakage current. Although embedded DRAM (eDRAM) offers higher memory density, its energy consumption is high due to frequent refresh operation, which is induced by the short refresh interval (40∼100μs). In this paper, a dual-mode buffer memory based on the CMOS compatible HfZrO2 ferroelectric material is proposed for DNN accelerators. It can operate in both volatile eDRAM mode and non-volatile ferroelectric RAM (FeRAM) mode. The functionality of the proposed dual-mode memory bit-cell design is verified using SPICE simulation with the multi-domain Preisach physical model. A data-lifetime-aware memory mode configuration protocol is proposed to optimize the buffer access energy for both DNN inference and training. Detailed circuitry and architectural support for the dual-mode memory are presented. For DNN training with ferroelectric-field-effect-transistor (FeFET) and SRAM-based compute-in-memory (CIM) accelerator, the proposed dual-mode buffer design improves the overall energy efficiency by 92.2%∼98.7%, 44.1%∼47.6%, 12.6%∼13.0% compared to baseline designs using SRAM buffer with the same buffer area, eDRAM and FeRAM with the same buffer capacity, respectively. For DNN inference with tensor-processing-unit (TPU)-like systolic array, the energy efficiency during computing is improved by 40.7%∼45.6%, 18.4%∼29.6% compared to the designs with eDRAM and FeRAM buffer, respectively. By storing the persistent data using the non-volatile mode, the energy efficiency of systolic array is improved by 2.3×∼5.5× over SRAM-based design when standby is frequent. The chip area overhead of the dual-mode buffer design is 5.2%, 4.1% and 7.2% for FeFET-based-CIM, SRAM-based-CIM and systolic-array-based accelerators using eDRAM buffer, respectively. [ABSTRACT FROM AUTHOR]

An overturned charge injection synaptic transistor (OCIST) is experimentally demonstrated for neuromorphic hardware computing. The structure of the OCIST is similar to that of a conventional floating gate memory except for the directionality of charge injection. The charge valve layer (CVL) of the OCIST is analogous to a blocking oxide of a floating gate memory device. The OCIST employs the CVL to control charge flow to the floating gate, while the floating gate memory utilizes a tunneling oxide as a gate oxide for this. Because the CVL and the gate oxide are decoupled in the OCIST, the CVL is independently engineerable without any sacrifice of the gate oxide quality and scalability. Moreover, the selection spectrum for the CVL material is wide. Linearity and symmetry of synaptic potentiation and depression were improved. In addition, a classification accuracy of 92.4% for handwritten digits in the MNIST dataset was achieved. [ABSTRACT FROM AUTHOR]

We report one sort of weak physical unclonable functions (PUFs) composed of 14-nm nFinFETs with entropy of the random-trap-fluctuation (RTF). After the positive-bias-temperature-instability (PBTI) stress at high temperatures (85 °C ~ 150 °C), the generation of abundant random traps at the interface of gate-dielectric layers and channel efficiently improves cryptographic parameters of nFinFET-PUFs. Results show that bit-error-rates of the MOSAIC plots reduce to 1.4%; average values/standard-deviation of the inter- and intra- Hamming-distance reach 50.28%/1.7% and 0.38%/0.42%, respectively. This work provides an implacable technique to boost characteristics of weak PUFs through combinations of device-reliability and cryptography. [ABSTRACT FROM AUTHOR]

This study demonstrates a pentacene-based nonvolatile memory using a ferroelectric poly (vinylidene fluoride-trifluoroethylene) $/$ Barium Zirconate Titanate (P(VDF-TrFE) $/$ BZT) as a hybrid gate dielectric for thin film transistors (TFTs). The experiment results show that the solution-processed BZT is amorphous and has no obvious ferroelectricity. However, stacking the BZT and the P(VDF-TrFE) can effectively reduce the leakage current due to the improvement of the thin film interface quality. To further understand the memory properties, endurance and retention reliability tests were conducted. The devices exhibit good memory characteristics at a low operating voltage of ±10 V and a large storage window of 7 V. [ABSTRACT FROM AUTHOR]

In-memory computing (IMC) can eliminate data movement between processor and memory, which is a barrier to the energy efficiency and performance in von Neumann computing. Due to low power consumption, fast operation, and tiny footprint in crossbar architecture, resistive RAM (RRAM) is one of the most promising devices for IMC applications. We present FPCAS, a pipelined floating point (FP) arithmetic (addition/ subtraction) solver based on RRAM crossbars. Although promis- ing, RRAM-based computing may experience random failures, such as the stuck-at fault where RRAM cells are stuck at either a high-resistance state (HRS), i.e., stuck-at-0 (SA0), or a low-resistance state (LRS), i.e., stuck-at-1 (SA1). We propose techniques to prevent SA1 failures, namely, shifting-at-the-output (SATO), force to $V_{\mathrm{ DD}}$ (FTV), and force to ground (FTG) since 96% of the RRAMs employed in our architecture are in HRS. Using an extra clock cycle, both strategies employ the memory array’s fault-free RRAMs to conduct the computation. When the failure rate is less than 2%, SATO can manage more than 70% of faults, whereas FTV can handle more than 90% of faults at low power and low area overhead. Simulation results reveal that, for $\mathrm{\scriptstyle NAND}$ – $\mathrm{\scriptstyle NAND}$ - and $\mathrm{\scriptstyle NOR}$ – $\mathrm{\scriptstyle NOR}$ -based implementations, FPCAS consumes 335 and 322 pJ, respectively. Both implementations incur a performance overhead of 50% at the array level and 4% for pipelined FP implementation. [ABSTRACT FROM AUTHOR]

A tunable and reconfigurable logic gates based on an electrolyte-gated transistor (EGT) array are co-integrated with neuromorphic synapses. The tunable and reconfigurable operations of the various logic gates are controlled by analog conductance modulation with nonvolatility of the fabricated EGT. The EGT array was uniformly fabricated on an entire 4-in wafer with the aid of CMOS compatible processes. Initiated-chemical vapor deposition (i-CVD) method was adopted for the deposition of the ultrathin polyethylene glycol dimethacrylate (pEGDMA) electrolyte layer. Therefore, the logic gates could be co-integrated with synaptic devices on the same in-plane substrate for integrability. Basic inverter operation with switching threshold tunability ranging from −1 to +1 V was demonstrated with good operational stability. In addition, NAND and NOR gate operations were realized by modulating the conductance level of a specified cell in the array configuration. [ABSTRACT FROM AUTHOR]

We demonstrate that a non-volatile majority function logic is formed by a 1T-nC $_{storage}$ -1C $_{read}$ cell in which a hafnia ferroelectric capacitor is used for computing in memory (CiM) and nonvolatile logic-in-memory (NV- LiM). We show a write operation of low voltage ($< 3\text{V}$) and high speed (< 20ns), with improved $\vphantom {_{\int }}$ endurance characteristics over 1011 cycles by adopting a novel write and read method. We performed a circuit-level analysis of an NV 1bit full adder. This adder achieves a power-delay-area product that is 4.8 and 53.5 times higher than the previous FeFET-based 1bit full adder when approximate computing is excluded and applied, respectively. [ABSTRACT FROM AUTHOR]

Nonvolatile memories (NVMs) have been widely studied in the post-Moore era. However, noise/defect in NVMs has brought a challenging reliability problem in write/read access operations. A linear error correction code (ECC) has been widely used in memories to correct errors. In general, a codec hardware is required to encode or decode the information, resulting in area and energy overhead. In this article, we propose a new approach to implement the ECC codec by exploiting the existing write and read peripheral circuitry of NVMs based on an in-memory computing (IMC) architecture. In our approach, the desired code words can be generated through using write-like logic operations, given the original information and generation matrix during the encoding (write) process, while syndrome vectors (or error correction) can also be achieved through using read-like logic operations, given the parity-check matrix during the decoding (read) process, respectively. Therefore, we do not need a specific codec hardware but exploit the write-like and read-like logic operations. With an emerging toggle spin torque magnetic random access memory (TST-MRAM) and Hamming code as an example, we validated the feasibility of our approach and evaluated the performance of the design in the 40-nm technology node. The results show that our approach can significantly reduce energy consumption compared with state-of-the-art designs. [ABSTRACT FROM AUTHOR]

An ultralow program/erase voltage ($\vert {V}_{\textit {P/E}}\vert = 4$ V) is demonstrated by using an antiferroelectric-ferroelectric field-effect transistor (AFE-FE-FET) through a multipeak coercive ${E}$ -field (${E}_{C}$) concept for a four-level stable state with outstanding endurance (>105 cycles) and data retention (>104 s at 65 °C). The mixture of ferroelectric (FE) and AFE domains can provide stable multistate and data storage with zero bias for multilevel cell (MLC) applications. HfZrO2 (HZO) with AFE-FE assembles an orthorhombic/tetragonal (o/t) phase composition and is achieved by [Zr] modulation in an HZO system. MLC characteristics not only improve high-density nonvolatile memory (NVM) but are also beneficial to neuromorphic device applications. [ABSTRACT FROM AUTHOR]

In this work, we explore the material potential of yttrium-content GeOx (YGO) in the design of a charge-trapping gate stack for embedded non-volatile memory (eNVM), which can share common gate stack materials with Ge logic CMOS. Based on a deep understanding of YGO, we propose a Ge eNVM with an oxidation-induced self-assembled YGO layer as the charge trapping layer. An eNVM fabricated on Ge offers a fast program/erase (P/E) speed (50 $\mu \text{s}$ and 2 ms for program and erase operations, respectively), low-voltage operation, a data retention lifetime of >10 years, and an endurance of > 105 P/E cycles. [ABSTRACT FROM AUTHOR]

A tunnel-oxide-free GaN-based non-volatile memory (NVM) device is proposed to untangle the trilemma among speed, retention, and endurance in the implementation of conventional NVM. The program and erase (P/E) are based on bipolar charge injection controlled by individual junction barriers, whereas the data retention relies on bipolar charge trapping in an interfacial charge storage layer. The wide bandgap energy of GaN allows the formation of deep-level traps at a dielectric/GaN interface and high junction barriers in GaN, both of which benefit long-term retention. As such, the GaN-based NVM device could get rid of the tunnel oxide, thereby enabling faster P/E processes and facilitating to decouple the enhancement of endurance from that of speed and retention. The proposed device demonstrates a P/E time of 100 ns, endurance over 106 cycles, and long retention time. [ABSTRACT FROM AUTHOR]

Diverse areas such as the Internet of Things (IoT), aerospace and industrial electronics increasingly require non-volatile memory to work under high-temperature, radiation-hard conditions, with zero standby power. Nanoelectromechanical (NEM) relays uniquely have the potential to work at 300 °C and absorb high levels of radiation, with zero leakage current across the entire operational range. While NEM relays that utilise stiction for non-volatile operation have been demonstrated, it is not clear how to design a relay to reliably achieve given programming and reprogramming voltages, an essential requirement in producing a memory. Here, we develop an analytical, first-principle physics-based model of rotational NEM relays to provide detailed understanding of how the programming and reprogramming voltages vary based on the device dimensions and surface adhesion force. We then carry out an experimental parametric study of relays with a critical dimension of $\approx ~\mathrm {80~~\, \text {n} \text {m} }$ to characterise the surface adhesion force, and derive guidelines for how a NEM relay should be dimensioned for a given contact surface force, feature size constraints and operating requirements. We carry out a scaling study to show that voltages of $\approx ~\mathrm {1~~\, \text {V}}$ and a footprint under $\approx ~\mathrm {2~~\, \mu \text {m} ^{2}}$ can be achieved with a critical dimension of $\approx ~\mathrm {10~~\, \text {n} \text {m} }$ , with this device architecture. [2021-0138] [ABSTRACT FROM AUTHOR]

In this study, we demonstrate a novel recessed channel ferroelectric field-effect transistor (FeFET) with gate metal/ferroelectric (FE) layer/inter-metal (IM)/interlayer (IL)/Si stacks, which can be called as dual metal gates recessed channel FeFET (DM-RFeFET), for nonvolatile memory applications with high performance and robust reliability. Through technology computer-aided design (TCAD) simulations with calibrated FE and device model parameters, it is revealed that the DM-RFeFET can have the wide memory window (MW) and the possibility of endurance improvement by maximizing the area ratio of FE and IL without sacrificing the footprint. Furthermore, the guidelines for the DM-RFeFET design are provided in terms of recess depth and additional high- ${k}$ blocking layer between IM and IL to maximize the MW and to minimize IM charging by the gate leakage current. [ABSTRACT FROM AUTHOR]

Ferroelectric field-effect transistors (FEFETs) are an important candidate for emerging nonvolatile memory applications but suffer from a lack of physical understanding of the device operation. Previous FEFET models utilized the Preisach model of ferroelectrics and do not accurately capture the physics of the FEFET that the majority of the polarization charge is screened by trapped charge at the interfaces. We propose an empirical model for FEFETs, which also considers screening of ferroelectric polarization. The screening charge is modeled as a dissipative (leakage) current across the baseline MOS gate-stack. The proposed model is calibrated using the experimental data of p-type ZrO2 FEFETs and unravels the weak electrostatic coupling between the ferroelectric polarization and semiconductor channel charge. In addition, the model captures the memory window discrepancy between the charge–voltage characteristics and current–voltage characteristics observed in the experimental data, provides new insight into the ferroelectric device, and is well-suited for use as a compact model implementation of FEFETs. [ABSTRACT FROM AUTHOR]

In this article, we provide an analytical model for the total ionizing dose (TID) effects on the bit error statistics of commercial flash memory chips. We have validated the model with experimental data collected by irradiating several commercial NAND flash memory chips from different technology nodes. We find that our analytical model can project bit errors at higher TID values [~20 krad (Si)] from measured data at lower TID values [<1 krad (Si)]. Based on our model and the measured data, we have formulated basic design rules for using a commercial flash memory chip as a dosimeter. We discuss the impact of NAND chip-to-chip variability, noise margin, and the intrinsic errors on the dosimeter design using detailed experimentation. [ABSTRACT FROM AUTHOR]

We investigate the sensitivity of silicon–oxide–nitride–silicon–oxide (SONOS) charge trapping memory technology to heavy-ion induced single-event effects. Threshold voltage ($V_{T}$) statistics were collected across multiple test chips that contained in total 18 Mb of 40-nm SONOS memory arrays. The arrays were irradiated with Kr and Ar ion beams, and the changes in their $V_{T}$ distributions were analyzed as a function of linear energy transfer (LET), beam fluence, and operating temperature. We observe that heavy ion irradiation induces a tail of disturbed devices in the “program” state distribution, which has also been seen in the response of floating-gate (FG) flash cells. However, the $V_{T}$ distribution of SONOS cells lacks a distinct secondary peak, which is generally attributed to direct ion strikes to the gate-stack of FG cells. This property, combined with the observed change in the $V_{T}$ distribution with LET, suggests that SONOS cells are not particularly sensitive to direct ion strikes but cells in the proximity of an ion’s absorption can still experience a $V_{T}$ shift. These results shed new light on the physical mechanisms underlying the $V_{T}$ shift induced by a single heavy ion in scaled charge trap memory. [ABSTRACT FROM AUTHOR]

Silicon channel ferroelectric field-effect transistors (FeFETs) with low-k interfacial layer (IL) between ferroelectric and silicon channel suffers from high write voltage, limited write endurance and long read-after-write latency. This is due to early IL breakdown and mobile charge injection at the ferroelectric-IL interface. Here, we demonstrate low voltage, high speed memory operation with high write endurance using an IL-free back-end-of-line (BEOL) compatible FeFET. We fabricated IL-free FeFETs with 28nm channel length (Lg) and 126nm width under a thermal budget < 4000 C by integrating 5nm Hf0.5Zr0.5O2 (HZO) gate stack with amorphous Indium Tungsten Oxide (IWO) semiconductor channel. We report a voltage memory window of 1.6V with a read current window ${I}_{\textit {LVT}}{/}{I}_{\textit {HVT}}$ of 105, write voltage of ±1.6V with 20ns pulses, instantaneous read-after-write latency < 300ns and a record high write endurance exceeding 1011 cycles. This establishes the IL-free BEOL FeFET as a promising candidate for logic-compatible high-performance last-level cache memory. [ABSTRACT FROM AUTHOR]

HfZrOx-based p- and n-FeFETs with high-k AlON interfacial layer (IL) were employed as the platform to evaluate how $\gamma $ -rays radiation affects the memory performance and reliability characteristics. Even with radiation dose of 1 Mrad, the memory window (MW) and retention in terms of current ratio are hardly changed for both types of FeFETs due to the improved interfacial quality by the AlON IL. Although showing a smaller MW than n-FeFETs, p-FeFETs are considered with higher competitive advantages in terms of more robust endurance against radiation up to $10^{{5}}$ cycles by long-pulse ($10^{\text {-4}}$ s) cycling due to mitigated hot-electrons induced hole generation. Furthermore, the much-improved read latency for p-FeFETs also maintains after being subjected to 1 Mrad radiation doses. These promising results suggest that p-FeFETs possess a great potential for high-speed, high-reliability applications in the radiation environment. [ABSTRACT FROM AUTHOR]

Endurance to cyclic program/erase (P/E) in a gate-all-around (GAA)-based SONOS flash memory device is improved by Joule heat, which was driven by gate-induced drain leakage (GIDL) current (${I}_{\text {GIDL}}$) with a current level of microamperes. By use of COMSOL simulation, induced temperature (${T}$) by the ${I}_{\text {GIDL}}$ is higher at the GAA with the ONO gate dielectrics than at a GAA with a thermal gate oxide due to the confined heat inside a silicon nanowire channel wrapped by a relatively thick ONO. Furthermore, ${T}$ is high enough to cure the damage from the iterative P/E operations. For a quantitative evaluation of the damage level before and after cyclic P/E, border trap density (${N}_{\text {bt}}$) in a tunneling oxide was analyzed with the aid of low-frequency noise (LFN) measurements. The damage was almost fully cured by ${I}_{\text {GIDL}}$ without an external Joule heater or structural modifications because it is always around a MOSFET. [ABSTRACT FROM AUTHOR]

In this study, we present programming speed enhancement in amorphous oxide semiconductor memory thin-film transistor (TFT). We developed a nonvolatile memory transistor based on InZnSnO back-channel-etch TFT with InGaZnO charge storage layer inserted between gate insulators. We proposed double-gate (DG) and body-contacted (BC) memory structure to improve memory erase speed, which is the most important issue in oxide memory TFTs. DG memory did not show sufficient improvement due to large voltage drop in second gate insulator. BC memory, which can control back-channel potential directly, showed significant improvement on memory program/erase speed. [ABSTRACT FROM AUTHOR]

An organic field-effect transistor nonvolatile memory with multibit storage capability and selective UV response was demonstrated, which showed good retention for all the memory states. The programming/erasing of the device operating at a low voltage was enabled by solar-blind UV light of 254 nm, and it had no response to 365 nm UV light and visible light. The stepwise switching between the memory states was controlled only by the number of the programming/erasing pulses, rather than by programming/erasing voltage or duration. The multibit memory feature is ascribed to the cumulative and reversible charge trapping in the employed polymer electret layer, and this architecture may offer a promising approach to multibit organic-based memories. [ABSTRACT FROM AUTHOR]

Ferroelectric vertical gate-all-around field-effect-transistor (Fe-VGAAFET) suits a memory cell with a 5 nm technology node and beyond since it is less constrained by gate length, thereby providing sufficient space for the ferroelectric film compared with ferroelectric FinFET (Fe-FinFET) and ferroelectric lateral gate-all-around field-effect-transistors (Fe-LGAAFET). Also, Fe-VGAAFET achieves multilayer vertical stacking, which further increases the integrated density of devices. Here, we develop ferroelectric vertical sandwich gate-all-around field-effect-transistors (Fe-VSAFETs) with large memory windows (the maximum 2.3 V), high program/erase speeds (100 ns), and excellent retention properties using a self-aligned high- $\kappa $ metal gate process. Furthermore, vertical nanosheet devices with two channel thicknesses of approximately 16 and 42 nm and nanowire devices with a channel diameter of 30 nm were successfully fabricated, and excellent device characteristics were obtained. [ABSTRACT FROM AUTHOR]

Logic-in-memory (LIM) technology is an important technology that overcomes the bottleneck, a limitation of the von Neumann architecture. As described in previous reports, the LIM technology was fabricated with a resistive load inverter structure. However, there are some limitations due to the high-power consumption issue and low noise margin. As a result, the need for a LIM device with a complementary structure has emerged. Here, we propose a LIM architecture-based organic-inorganic complementary inverter circuit with a stable noise margin using a p-type floating-gate transistor memory (FGTM) and an n-type zinc-tin oxide (ZTO) thin-film transistor (TFT). We demonstrate that the output of the proposed complementary inverter circuit is determined according to the state of the FGTM memory. [ABSTRACT FROM AUTHOR]

The exploration of memtransistors as a combination of a memristor and a transistor has recently attracted intensive attention because it offers a promising candidate for next‐generation multilevel nonvolatile memories and synaptic devices. However, the present state‐of‐the‐art memtransistors, which are based on a single material, such as MoS2 or perovskite, exhibit a relatively low switching ratio, require extremely high electric fields to modulate bistable resistance states and do not perform multifunctional operations. Here, the realization of an electrically and optically controllable p–n junction memtransistor using an Al2O3 encapsulated 2D Te/ReS2 van der Waals heterostructure is reported. The hybrid memtransistor shows a reversible bipolar resistance switching behavior between a low resistance state and a high resistance state with a high switching ratio up to 106 at a low operating voltage (<10 V), high cycling endurance, and long retention time. Moreover, multiple resistance states are achieved by applying different bias voltages, gate voltages, or light powers. In addition, logical operations, including the inverter and AND/OR gates, and synaptic activities are performed by controlling the optical and electrical inputs. The work offers a novel strategy for the reliable fabrication of p–n junction memtransistors for multifunctional devices and neuromorphic applications. [ABSTRACT FROM AUTHOR]

An advanced gate-stack design of ferroelectric (FE) transistors has been proposed and investigated for logic compatible program/erase voltage, better scalability, and suppressed depolarization field. The ferroelectric-metal (FeM) FinFET (FeM-FinFET) and stacked nanosheets transistor (FeM-Nanosheet), which have an FE layer on top of the transistor’s gate, could adjust the area ratio (AR) between the FE capacitor (${A}_{\text{FE}}$) and the MOS capacitor (${A}_{\text{MOS}}$) (AR = ${A}_{\text{FE}} / {A}_{\text{MOS}}$) using the floating gate between them, thereby enhancing the electric field on the FE layer. In particular, the proposed FeM-Nanosheet could have the flexibility to lower the operating voltage and depolarization field by increasing the number of nanosheets to reduce the AR. [ABSTRACT FROM AUTHOR]

Ternary content addressable memory (TCAM) is one type of associative memory and has been widely used in caches, routers, and many other mapping-aware applications. While the conventional SRAM-based TCAM is high speed and bulky, there have been denser but slower and less reliable nonvolatile TCAMs using nonvolatile memory (NVM) devices. Meanwhile, some CMOS TCAMs using dynamic memories have been also proposed. Although dynamic TCAM could be denser than the 16T SRAM TCAM and more reliable than the nonvolatile TCAMs, CMOS dynamic TCAMs still suffer from the row-by-row refresh energy and time overheads. In this article, we propose dynamic TCAM using nanoelectromechanical (NEM) relays (DyTAN), and utilize one-shot refresh (OSR) to solve the memory refresh problem. By exploiting the unique NEM relay characteristics, DyTAN outperforms the existing works in the balance between density, speed, and power efficiency. Compared with the 16T SRAM-based TCAM, the 5T CMOS dynamic TCAM, the 2T2R TCAM, and the 2FeFET TCAM, evaluations show that the proposed DyTAN reduces the write energy by up to $2.3\times $ , $1.3\times $ , $131\times $ , and $13.5\times $ , and improves the search energy-delay-product (EDP) by up to $12.7\times $ , $1.7\times $ , $1.3\times $ , and $2.8\times $ , respectively. [ABSTRACT FROM AUTHOR]

Reconfigurable ferroelectric transistor (R-FEFET) is a variant of a ferroelectric transistor (FEFET), which utilizes two asymmetrically sized gate stacks to achieve voltage-controlled modulation in hysteresis and dynamic reconfigurability between volatile and non-volatile modes. However, due to a floating internal metal layer (IML), gate leakage (GL) can lead to a polarization-dependent shift in device characteristics over time. This degrades read disturb margins (RDM) and the non-volatile memory (NVM) robustness. In this work, we propose an R-FEFET with symmetric gate stacks to diminish the adverse effects of GL on NVM operation. Utilizing our new R-FEFET, we propose a two-transistor NVM (2T-R), which exhibits up to 12% higher energy efficiency, $3\times $ increase in the RDM, and 14% lower area compared to an existing R-FEFET NVM. We also perform variation analysis showing a robust operation of the symmetric R-FEFET NVM. [ABSTRACT FROM AUTHOR]

One of the most attractive types of novel nonvolatile memory concepts is resistive random access memory (ReRAM) based on a reversible (“soft”) dielectric breakdown effect. The interest is caused by combining simple architecture with promising performance: excellent scalability, nanosecond speed, long data retention, and low power consumption. However, the commercialization of this type of memory is retarded mainly due to serious drawbacks: high cell-to-cell variability of switching parameters and limited endurance related to the ionic origin of resistive switching effect coupled with the problem of voltage overshooting. In particular, these issues complicate the examination of test samples because during the lifespan of memory cells, and the permanent reselection of test switching parameters is required. This challenge can be overcome by developing a measurement technique that combines careful testing of every single structure and the ability to test a large number of test structures. As such a technique, we propose an automated testing algorithm that automatically avoids voltage overshooting and provides an effective way of characterization of cell-to-cell and cycle-to-cycle variability. It includes all stages of ReRAM cell operation, specifically electroforming, dc switching, and endurance testing in the pulsed mode. The developed technique allows on-the-fly restoring of the memory window in case of its degradation, making it possible to better understand the potential of the material stacks of the memory cell. [ABSTRACT FROM AUTHOR]

We present a nonvolatile memory of two transistors and one ferroelectric-capacitance with the three-bit-per-cell capability. With a control transistor, the memory can be turned-off correctly when the ferroelectric capacitance is programmed such that the threshold-voltage of the unit cell shifts to a deep negative value. This unit cell can be programmed in 80 ns and erased in 20 ns. The conductance can be tuned gradually in $2.5\times 10^{{4}}$ folds of the on-off ratio with 30 cycles by pulse operations. The eight conductance values can be cycled more than $10^{{7}}$ times. Data stored in distinguished eight conductance values can be retained in 80 Celsius degrees for ten years. This work offers an applicable solution for embedded non-volatile memories with ferroelectric mechanisms. [ABSTRACT FROM AUTHOR]

A Ferroelectric Field-Effect Transistor (FEFET) is a promising candidate for next-generation memory devices because it offers numerous advantages, such as its high speed, low energy profile, and nondestructive readout process. FEFETs merge logic and memory functionality in a single device, allowing efficient data transfer and a high packing density, which could make them vital for use in future in-memory computing architectures. Although issues related to the integration of perovskite materials in the state-of-the art semiconductor industry limited their commercial success, the discovery of ferroelectricity in CMOS-compatible doped hafnium oxides led to a re-emergence of FEFETs in advanced microelectronics. The demonstration of ferroelectricity in doped hafnia at extremely thin film thicknesses plus its low permittivity, high coercive field (Ec), environment-friendly composition, and excellent CMOS compatibility are expected to unleash the promise of FEFETs, and significant progress has been made in this regard. [ABSTRACT FROM AUTHOR]

Doping of HfO2 thin films is a powerful means for stabilizing ferroelectricity in this material. Yet, the amount of doping is critical to achieving the best ferroelectric response. This article investigates the impact of the Si doping content on the key performance metrics of ferroelectric field-effect transistors (FeFETs). We report on its considerable effect on the memory window, switching uniformity and steepness, number of intermediate conductance states, and data retention. Based on the experimental results, we introduce simple figures of merit for a rapid assessment of the FeFET performance. Finally, we identify an important tradeoff between the abovementioned properties as a function of the dopant content and discuss possibilities for specialized device design for nonvolatile memory applications and potential neuromorphic devices based on FeFETs. [ABSTRACT FROM AUTHOR]

Hf0.5Zr0.5O2 (HZO)-based ferroelectric field-effect transistors (FeFETs) with HfO2 seed layer were investigated for radiation-hard nonvolatile memory applications. First, it was found that the HZO thin films grown on HfO2 seed layer showed improved crystallinity and ferroelectricity compared with those directly grown on SiO2 thin film, leading to a larger memory window (MW), better endurance, and retention properties of the HZO-based FeFETs with HfO2 seed layers. Moreover, after 1 Mrad(Si) 60Co $\gamma $ -ray irradiation, the memory properties of the HZO-based FeFETs with HfO2 seed layer were also better than those without the HfO2 seed layer. Especially, the HZO-based FeFETs with an HfO2 seed layer have a larger remaining MW (0.66 V) than that (0.29 V) of the FeFETs without an HfO2 seed layer after $1\times 10^{4}$ program/erase cycle. This work represents a first attempt to realize the high performances of radiation-hard HfO2-based FeFETs. [ABSTRACT FROM AUTHOR]

In this article, we report high-performance one-transistor-one-resistor (1T1R) FETs for nonvolatile memory application based on nanometer-thick indium oxide (In2O3) as channel material deposited by atomic layer deposition (ALD). ALD grown hafnium oxide (HfO2) and aluminum oxide (Al2O3) are used as gate dielectrics as well as insulator in resistive part. Two nonvolatile states with different threshold voltages are realized. High ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}} > 10^{10}$ at ${V}_{\mathrm {GS}} =0$ V, large memory window (MW) exceeding 10 V, and deep sub-60-mV/dec subthreshold slope (SS) are achieved on ALD In2O3 1T1R FETs. Channel length (${L}_{\mathrm {ch}}$) and channel thickness (${T}_{\mathrm {ch}}$) dependence of device properties are systematically investigated. Optimized In2O3 thickness is determined to 1.2 nm, balancing ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ , MW, device variation, and stability. The fabrication process has a low thermal budget below 225 °C. Thus, these 1T1R FETs are back-end-of-line (BEOL) compatible and promising for monolithic 3-D integration to realize near-/in-memory computing. [ABSTRACT FROM AUTHOR]

We investigated the reduction of equivalent oxide thickness (EOT) of the in-situ formed Hf-based metal/oxide/nitride/oxide/silicon (MONOS) structure nonvolatile memory (NVM) device utilizing the HfON tunneling layer (TL). In case of the HfO2 TL, the SiO2 interfacial layer (IL) was formed which incrased EOT. The HfON device shows on/off current of 3.2 × 106 at drain voltage (VD ) of 0.05 V, subthreshold swing (SS) of 113 mV/dec., and memory window (MW) of 3.9 V at the program voltage/time (VPGM/tPGM) and erase voltage/time (VERS/tERS) of ±8 V/100 ms. Although, it shows low retention characteristics with 50% after 10 years, low-voltage and short-pulse operation were achieved, such as MW of 1 V at VPGM/tPGM and ERS/tERS of ±8 V/1 μs. Furthermore, it showed larger drain source voltage (VDS) dependence than HfO2 TL by utilizing charge injection from electrode side, which would reduce the operation voltage and increase the operation speed. [ABSTRACT FROM AUTHOR]

A plasma-based undoped-HfO2 FeFET (ferroelectric FET) with non-volatile memory characteristics is demonstrated. Modifying the O2 plasma period in plasma-enhanced atomic layer deposition (PE-ALD) is an effective approach to enhance the remnant polarization ($\text{P}_{\text {r}}$) up to 2P $_{\text {r}} = 25\,\,\mu \text{C}$ /cm2 for the MFM (metal/ferroelectric/metal) structure with ferroelectric undoped-HfO2 thin films, and successful integration is implemented for the FeFET. The appropriate O2 vacancies ($\text{V}_{\text {o}}^{{2}+}$) benefit the formation of the ferroelectric phase since they play the role of dopants and help orthorhombic phase (o-phase) formation during post-metal annealing (PMA). The $\text{V}_{\text {o}}^{{2}+}$ -rich undoped-HfO2 FeFET exhibits a memory window (MW) of 0.5 V, ${5} \times {10}^{{4}}$ switching endurance cycles, and higher than $10^{{4}}$ sec of data retention with $\text{V}_{\text {P/E}} = \pm 5$ V. [ABSTRACT FROM AUTHOR]

In this letter, we demonstrate a reconfigurable logic-memory hybrid device (R-LMHD), which can be dynamically and reversibly switched between the logic- and memory- mode. The logic-mode device exhibits a $2.5\times 10^{6}$ ON/ OFF current ratio and nearly zero hysteresis, which indicates the weak influence of defects trapping and de-trapping. The memory-mode device shows a large memory window up to 2.19 V and the window maintains up to 1.44 V after 106 program/erase cycles. The excellent performance can be attributed to the high crystalline quality of ferroelectric Hf0.5Zr0.5O2 (HZO) and the insertion of internal metal gate (IMG) between HZO and dielectric layer. Such R-LMHD features run-time tuning of threshold voltage and hysteresis, electrically reconfigurable. Furthermore, the subthreshold swing (SS) is electrically tunable with a minimum SS ($SS_{min}$) of 35 mV/decade and a maintainability of sub-60 mV/decade about 3 orders. The R-LMHD provides a promising way to realize future in-memory computing and low power consumption applications. [ABSTRACT FROM AUTHOR]

We report a heterojunction, nonvolatile memory (NVM) device with amorphous indium-gallium-zinc oxide (a – IGZO) and low-temperature polysilicon (LTPS) stack. The LTPS layer was achieved by blue laser annealing of amorphous silicon. The a – IGZO/LTPS heterojunction NVM exhibits a large threshold voltage $(\Delta {\mathsf {V}}_{\mathsf {Th}}({\mathsf {V}}))$ memory window of 19.2 V with prolonged operational stability. An increase in channel length (L) (from 2 to $20~\mu \text{m}$) exhibits a stable memory window. The neutral oxygen vacancy states in a – IGZO trap the carriers at a – IGZO/LTPS interface and then transforms into a metastable state, (${\mathsf {D}}^{\mathsf {O}}+ {\mathsf {h}}^{+}(2 {\mathsf {h}}^{+})\to {\mathsf {D}}^{+}/ {\mathsf {D}}^{++}$ or ${\mathsf {D}}^{\mathsf {O}}+ {\mathsf {e}}^{-}(2 {\mathsf {e}}^{-})\to {\mathsf {D}}^{-}/ {\mathsf {D}}^{--}$), which is the key to the operation of a – IGZO/LTPS heterojunction NVM. [ABSTRACT FROM AUTHOR]

Low mobility and high operating voltages are bottlenecks in the practical application of ferroelectric organic field-effect transistor (Fe-OFET) nonvolatile memory (NVM). In this article, we demonstrate a high-mobility polymer semiconductor-based Fe-OFET NVM that can well operate at low programming/erasing voltages (VP/VE). The issue that hinders the reduction of the VP/VE in Fe-OFET NVMs is discussed. We develop a route to resolve the issue by building a thin bilayer gate insulator consisted of an ultrathin poly(methyl methacrylate) (PMMA) and a thin poly(vinylidenefluoride-trifluoroethylene) films. The processing compatibility, that is, the tri-layered core architecture consisting of polymer semiconductor and insulator films is prepared by a full-solution technology, is confirmed. The mechanism of the performance improvements by using the ultrathin PMMA in the Fe-OFET NVMs is investigated. As a result, the Fe-OFET NVM exhibits excellent performances at low VP/VE of ±15 V, with a high mobility up to 1.75 cm2/Vs, reliable memory endurance over 400 cycles, and stable memory retention over 65000 s. [ABSTRACT FROM AUTHOR]

This article demonstrates the total ionizing dose (TID) impact on a NAND flash memory-based physical unclonable function (PUF). We used commercial-off-the-shelf flash memory chips to generate PUF. The flash chip is irradiated with Co-60 gamma rays up to 10 krad(Si). The irradiated chip shows significant accuracy degradation (bit error ~ 12%) of the flash-PUF. We show that TID-induced trapped charges in the oxide alter the intrinsic cell properties causing accuracy degradation of flash-PUF. We propose two independent techniques to improve the PUF accuracy under radiation environment. The first technique relies on electrical annealing which compensates the trapped charges by program stressing. The second technique uses radiation compensation method by adaptive PUF generation process. Our experimental results show that the accuracy degradation can be as low as 1.5% for TID up to 10 krad(Si) with these radiation mitigation techniques. [ABSTRACT FROM AUTHOR]

In spite of the increasing use of machine learning techniques, in-memory computing and hardware have increased the interest to accelerate neural network operation. Henceforth, novel embedded nonvolatile memories (eNVMs) for highly scaled technology nodes, like ferroelectric field effect transistors (FeFETs), are heavily studied and very promising. Furthermore, inference and on-chip learning can be fostered by further eNVM technology options, such as multibit operation and linear switching. In this article, we present the advantages of hafnium oxide-based FeFETs for such purposes due to their basic three-terminal structure, which allows to selectively activate or deactivate selected devices as well as tune linearity and dynamic range for certain applications. Furthermore, we discuss the impact of the material properties of the ferroelectric layer, the interface layer thickness, and scaling on the device performance. Here, we demonstrate good device properties even for highly scaled devices (100 nm × 100 nm). [ABSTRACT FROM AUTHOR]