Search

Negative capacitance field-effect transistors (NCFETs) with optimal ferroelectric parameters provide phenomenal power reduction as discussed in Part I. In this part, we explore the impact of operating voltage on power consumption at the device, gate, and full-chip levels. We first observe that high operating voltages applied to NCFET devices lead to an abrupt increase in both the drain current and the gate capacitance. Furthermore, negative capacitance is lost when the voltage is set too high. On the other hand, the gate capacitance increase still exists, although with smaller magnitude, even at low operating voltages. This helps reduce device delay and eventually full-chip delay. Furthermore, delay improvement at the full-chip level can be traded off to gain power reduction at the full-chip level. Finally, our experiments suggest that a sufficiently low supply voltage (= 0.4 V out of [0.2 and 0.8 V] range in our study) is needed to maximize power and performance gain at full-chip level. [ABSTRACT FROM AUTHOR]

In this two-part article, we propose a framework for selecting ferroelectric oxide material for the design of a negative capacitance field-effect transistor (NCFET). The investigation is based on an exhaustive search of two important ferroelectric material parameters: remnant polarization and coercive field in the context of their negative capacitance properties. The effects of these parameters are first studied at the NCFET device level and systematically extended up to the full-chip level. Based on this search, we arrive at the notion of optimality of ferroelectric parameters for a given “isoperformance full-chip benchmark”: The power dissipation in a specific circuit/system is maximally reduced by using optimized NCFETs while meeting the target performance. In Part I, we develop the framework for identifying optimal ferroelectric parameters at a given VDD. This sets the stage for Part II, where we investigate the optimal ferroelectric parameters as VDD is scaled. [ABSTRACT FROM AUTHOR]