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With downscaling of process technology, conventional memories encounter challenges, such as soaring static power, low reliability, and charge sharing effect induced by radiation effects. Magnetic random access memory (MRAM) is considered as an outstanding candidate for addressing these challenges. In particular, emerging spin–orbit torque (SOT) MRAMs have shown ultra-fast switching and read-disturbance immunity compared with spin-transfer torque MRAMs. However, the write operation of the SOT-MRAM is more vulnerable to single-event upsets (SEUs) as its ultra-short write pulse is comparable to the radiation current pulse. In addition, its read circuit can also be disturbed by SEUs or even double-node upsets (DNUs) induced by the charge sharing effect. In this paper, we investigate radiation effects on read/write circuits of the SOT-MRAM. Then, we propose novel radiation hardening designs for SOT-MRAM. The hardening technique is first studied at the write circuit by adding six PMOS transistors as a feedback structure to charge/discharge. Afterwards, we propose a radiation hardening read circuit addressing the issue of SEUs and DNUs, which uses redundant six transistors and two feedback connections as the hardening structure. Based on a physics-based SOT magnetic tunnel junction model and a 65-nm complementary metal–oxide–semiconductor design kit, simulation results indicate that radiation-induced soft errors can be corrected at sensitive nodes. Moreover, the error rate of the proposed read circuit is $40\times $ smaller than the previous work, and restoring time is reduced by 30.6% with negligible area overhead. [ABSTRACT FROM AUTHOR]

Continued scaling of Complementary Metal Oxide Semiconductor (CMOS) integrated circuit technology is slowing down due to physical limitations, while the static power of CMOS based memory is increasing as the transistors shrink. As an alternative memory technology, the Spin Transfer Torque Magnetic RAM (STT-MRAM) remains limited to low-level, high-capacity caches because of the high write power and still unsatisfactory write access speed. Spin Orbit Torque MRAM (SOT-MRAM), which has been proposed to tackle this issue, still faces some issues including the poor read margin due to low Tunnel Magnetoresistance (TMR) and undesirable use of a magnetic field for deterministic switching. This article proposes a novel 3T2SOT (three Transistors and two SOT magnetic tunnel junctions) based field-free MRAM, which can achieve higher read speed and reliability by adopting a self-referencing scheme, and lower write power benefiting from an advanced switching mechanism. Detailed circuit-level simulation results show that the write latency of the proposed design can be reduced to $0.3~ns$ , and the write power is two orders of magnitude lower than STT-MRAM. Additionally, compared to SRAM, for 8 MB cache memory, the read speed of 3T2SOT MRAM is enhanced by 38.9%. Compared to conventional 2T1SOT MRAM, the read performance is similar and the read error rate is dropped by 96.1% at least. [ABSTRACT FROM AUTHOR]