Search

High power microwaves (HPM) coupled through the front door pose a potential threat to RF front ends, especially for low noise amplifiers (LNA). Therefore, A C-band LNA circuit model is constructed to investigate the non-linear effects and degradation characteristics of the LNA under HPM, and validate it against damaged samples analysis acquired in HPM injection experiment of LNA. The circuit model consists of a pseudocrystalline high electron mobility transistors (pHEMT) device equivalent physical model and other passive device SPICE models. The nonlinear relationship of input and output signals and the distribution of physical parameters of pHEMT device are analyzed by simulation. When the LNA injection power is less than a certain threshold, the nonlinear degradation of LNA is recoverable. However, when the LNA injection power is greater than a certain threshold, the pHEMT device in the circuit will be damaged by combustion. Under the influence of HPM, it forms a high current channel between gate and channel due to the avalanche breakdown of the Schottky junction and generates a hot spot on the side below the gate near the source, which will eventually cause burnout damage. Moreover, an empirical formula is presented to describe the relationship between the damage time of HPM and the injection power and energy. By scanning electron microscope (SEM) observation and energy dispersive spectrometer (EDS) analysis of the damaged samples, the results show that the pHEMT gate is vulnerable to HPM damage. The hot spot inside the pHEMT device in the simulation is consistent with the damage location of the LNA in HPM injection experiment.

Electronic system and device are vulnerable under intensive electromagnetic pulse (EMP) environment, where low noise amplifer (LNA) is a typical sensitive instance for electromagnetic energy. This work focuses on the EMP-induced damage effect of GaAs pseudomorphic high electron mobility transistor (PHEMT), which is the core part of LNA. Using the simulation softeware Sentaurus TCAD, an EMP-induced damage model of the GaAs PHEMT is established in this paper, and verified through the experimental result. It is shown that the damage position of the device under the injection EMP exists in the center area under gate terminal. Based on this model and aiming at EMP parameters and external resistances, the influence of the external conditions on the damage effect of the device is investigated. The results indicate that the damage time is related to EMP parameters obviously:1) the damage time is inversely proportional to EMP amplitude since higher power density is absorbed under a stronger EMP; 2) the damage time is in direct proportion to signal rising time since the breakdown time is postponed under EMP with a slower rising edge. Furthermore, it is found that a load resistor is able to weaken current channel which is effective in delaying the damage process, and this effect is more obvious, with load resistor connected with source terminal. It should be noted that the results are beneficial to and valuable in hardening method against EMP of semiconductor devices. It is feasible to design external circuit protection units, aiming at attenuating signal amplitude and increasing the rising time of injected pulse. Another effectual approach is to enlarge the source series resistance under the premise of the performance meeting the requirements.

Simulations are carried out to explore the possibility of achieving high breakdown voltage of GaN HEMT (high-electron mobility transistor). GaN cap layers with gradual increase in the doping concentration from 2 × 1016 to 5 × 1019 cm−3 of N-type and P-type cap are investigated, respectively. Simulation results show that HEMT with P-doped GaN cap layer shows more potential to achieve higher breakdown voltage than N-doped GaN cap layer under the same doping concentration. This is because the ionized net negative space charges in P-GaN cap layer could modulate the surface electric field which makes more contribution to RESURF effect. Furthermore, a novel GaN/AlGaN/GaN HEMT with P-doped GaN buried layer in GaN buffer between gate and drain electrode is proposed. It shows enhanced performance. The breakdown voltage of the proposed structure is 640 V which is increased by 12% in comparison to UID (un-intentionally doped) GaN/AlGaN/GaN HEMT. We calculated and analyzed the distribution of electrons' density. It is found that the depleted region is wider and electric field maximum value is induced at the left edge of buried layer. So the novel structure with P-doped GaN buried layer embedded in GaN buffer has the better improving characteristics of the power devices.

Electronic transport properties of a finite (7,0) carbon nanotube (CNT) coupled to Au (111) surfaces are investigated with a fully nonequilibrium Green's functions method combined with the density functional theory. The results show that the coupling effect between the CNT and Au electrode plays an important role in the transport properties, which leads to the formation of a high plateau in the transmission spectrum around Fermi energy. In addition, the current-voltage characteristic of the (7,0) CNT coupled to Au electrodes is different from an isolated (7,0) CNT.

As electromagnetic environment of semiconductor device and integrated circuit deteriorates increasingly, electromagnetic pulse (EMP) of device and damage phenomenon have received more and more attention. In this paper, the damage effect and mechanism of the GaN high electron mobility field effect transistor(HEMT) under EMP are investigated. A two-dimensional electro-thermal theoretical model of GaN HEMT under EMP is proposed, which includes GaN polarization effect, mobility degradation in large electric field, avalanche generation effect, and self-heating effect. The internal transient response of AlGaN/ GaN HEMT is analyzed under the EMP injected into the gate electrode, and the damage mechanism is studied. The results show that the temperature of device keeps increasing, and the rate is divided into three stages, which present a tendency of rapid-slow-sharp till burn-out. The first rapid increasing of temperature is caused by the avalanche breakdown, and then rate becomes smaller due to the decrease of electric field. As the temperature is more than 2000 K, a positive feedback is formed between the hot electron emission and temperature of device, which causes temperature to sharply increase till burn-out. The maximum values of electric field and current density are located at the cylinder surface beneath the gate around the source, which is damage prone because of heat accumulation. Finally, the dependences of the EMP damage power, P, and the absorbed energy, E, on pulse width are obtained in a nanosecond range by adopting the data analysis software. It is demonstrated that the damage power threshold decreases but the energy threshold increases slightly with the increasing of pulse-width. The proposed formulas P = 38-0.052 and E = 1.1 0.062 can estimate the HPM pulse-width dependent damage power threshold and energy threshold of AlGaN/GaN HEMT, which can provide a good prediction of device damage and a guiding significance for electromagnetic pulse resistance destruction.

With the thermal effects of substrate and package in mind, electrothermal simulations are performed on the transient response of transistors under the injection of electromagnetic pulses by adopting the 2-D device simulator ISE-TCAD. Simulation results show that the junction temperature inside a transistor will increase so instantly to the melting point of silicon within tens or hundreds of nanoseconds as to damage the device when the current mode second breakdown arises in the transistor for electromagnetic pulses with high power. In this case, the thermal resistance of package has little influence over the burnout time and damage energy. However, when the electromagnetic pulse has too small a power to produce the current mode second breakdown, the thermal mode second breakdown will arise in the transistor. In this case, the thermal resistance of package will have a notable effect over the burnout time and damage energy.

The influence of temperature on the breakdown in anisotropic 6H-SiC MOSFET is studied. Taken Si face as an example , the influence of temperature on the breakdown voltage, critical electrical field and specific on-state resistance is thoroughly analyzed. Considering the anisotropy of material, anisotropy of the breakdown is obtained in different face but the tendency of breakdown voltage vs. temperature is same, both has positive temperature coefficient.

The high power microwave (HPM) damage effect on the AlGaAs/InGaAs pseudomorphic high electron mobility transistor (pHEMT) is studied by simulation and experiments. Simulated results suggest that the HPM damage to pHEMT is due to device burn-out caused by the emerging current path and strong electric field beneath the gate. Besides, the results demonstrate that the damage power threshold decreases but the energy threshold slightly increases with the increase of pulse-width, indicating that HPM with longer pulse-width requires lower power density but more energy to cause the damage to pHEMT. The empirical formulas are proposed to describe the pulse-width dependence. Then the experimental data validate the pulse-width dependence and verify that the proposed formula P = 55t 0.06 is capable of quickly and accurately estimating the HPM damage susceptibility of pHEMT. Finally the interior observation of damaged samples by scanning electron microscopy (SEM) illustrates that the failure mechanism of the HPM damage to pHEMT is indeed device burn-out and the location beneath the gate near the source side is most susceptible to burn-out, which is in accordance with the simulated results.

The temperature dependence of the latch-up effects in a CMOS inverter based on 0.5 μm technology caused by high power microwave (HPM) is studied. The malfunction and power supply current characteristics are revealed and adopted as the latch-up criteria. The thermal effect is shown and analyzed in detail. CMOS inverters operating at high ambient temperature are confirmed to be more susceptible to HPM, which is verified by experimental results from previous literature. Besides the dependence of the latch-up triggering power P on the ambient temperature T follows the power-law equation P = ATβ. Meanwhile, the ever reported latch-up delay time characteristic is interpreted to be affected by the temperature distribution. In addition, it is found that the power threshold increases with the decrease in pulse width but the degree of change with a certain pulse width is constant at different ambient temperatures. Also, the energy absorbed to cause latch-up at a certain temperature is basically sustained at a constant value.

The motion of current filaments in avalanching PIN diodes has been investigated in this paper by 2D transient numerical simulations. The simulation results show that the filament can move along the length of the PIN diode back and forth when the self-heating effect is considered. The voltage waveform varies periodically due to the motion of the filament. The filament motion is driven by the temperature gradient in the filament due to the negative temperature dependence of the impact ionization rates. Contrary to the traditional understanding that current filamentation is a potential cause of thermal destruction, it is shown in this paper that the thermally-driven motion of current filaments leads to the homogenization of temperature in the diode and is expected to have a positive influence on the failure threshold of the PIN diode.

The current controlled voltage source model of substrate parasitic resistance of deep sub-micron electrostatic discharge protection device is optimized by considering the effect of conductance modulation. A compact macro-model of substrate resistance is presented according to the characteristics of lightly doped bulk substrate and heavily doped substrate with a lightly doped epitaxial layer, which is scalable with the layout dimension. The experimental model parameters of devices with various spaces between source and substrate diffusion can be extracted by device simulation. The breakdown behavior of gate grounded negative-channel metal oxide semiconductor shows the effectiveness of this method. In the meantime, the simulation time-consuming of the compact model is only 7% that of the device simulation software.

A two-dimensional electrothermal model of the bipolar transistor (BJT) is established, and the transient behaviors of the BJT originally in the forward-active region are simulated with the injection of electromagnetic pulse from the base. The results show that the damage location of the BJT shifts with the amplitude of the pulse. With a low pulse amplitude, the burnout of the BJT is caused by the avalanche breakdown of the emitter-base junction, and the damage location lies in the cylindrical region of this junction. With a high pulse amplitude, the damage first occurs at the edge of the base closer to the emitter due to the second breakdown of the p-n-n+ structure composed of the base, the epitaxial layer and the substrate. The burnout time increases with pulse amplitude increasing, while the damage energy changes in a decrease-increase-decrease order with it, thus generating both a minimum value and a maximum value of the damage energy. A comparison between simulation results and experimental ones shows that the transistor model presented in the paper can not only predict the damage location in the BJT under intense electromagnetic pulses, but also obtain the damage energy.

Sub-threshold characteristics of the dual material gate 4H-SiC MESFET (DMGFET) are investigated and the analytical models to describe the drain-induced barrier lowering (DIBL) effect are derived by solving one- and two-dimensional Poisson's equations. Using these models, we calculate the bottom potential of the channel and the threshold voltage shift, which characterize the drain-induced barrier lowering (DIBL) effect. The calculated results reveal that the dual material gate (DMG) structure alleviates the deterioration of the threshold voltage and thus suppresses the DIBL effect due to the introduced step function, which originates from the work function difference of the two gate materials when compared with the conventional single material gate metal—semiconductor field-effect transistor (SMGFET).

We conduct a theoretical study of the damage susceptibility trend of a typical bipolar transistor induced by a high-power microwave (HPM) as a function of frequency. The dependences of the burnout time and the damage power on the signal frequency are obtained. Studies of the internal damage process and the mechanism of the device are carried out from the variation analysis of the distribution of the electric field, current density, and temperature. The investigation shows that the burnout time linearly depends on the signal frequency. The current density and the electric field at the damage position decrease with increasing frequency. Meanwhile, the temperature elevation occurs in the area between the p–n junction and the n–n+ interface due to the increase of the electric field. Adopting the data analysis software, the relationship between the damage power and frequency is obtained. Moreover, the thickness of the substrate has a significant effect on the burnout time.

A lower doped layer is inserted between the gate and channel layer and its effect on the performance of a 4H-SiC Schottky barrier field-effect transistor (MESFET) is investigated. The dependences of the drain current and small signal parameters on this inserted gate-buffer layer are obtained by solving one-dimensional (1-D) and two-dimensional (2-D) Poisson's equations. The drain current and small signal parameters of the 4H-SiC MESFET with a gate-buffer layer thickness of 0.15 μm are calculated and the breakdown characteristics are simulated. The results show that the current is increased by increasing the thickness of the gate-buffer layer; the breakdown voltage is 160 V, compared with 125 V for the conventional 4H-SiC MESFET; the cutoff frequency is 27 GHz, which is higher than 20 GHz of the conventional structure due to the lower doped gate-buffer layer.

This paper presents a theoretical study of the pulse-width effects on the damage process of a typical bipolar transistor caused by high power microwaves (HPMs) through the injection approach. The dependences of the microwave damage power, P, and the absorbed energy, E, required to cause the device failure on the pulse width τ are obtained in the nanosecond region by utilizing the curve fitting method. A comparison of the microwave pulse damage data and the existing dc pulse damage data for the same transistor is carried out. By means of a two-dimensional simulator, ISE-TCAD, the internal damage processes of the device caused by microwave voltage signals and dc pulse voltage signals are analyzed comparatively. The simulation results suggest that the temperature-rising positions of the device induced by the microwaves in the negative and positive half periods are different, while only one hot spot exists under the injection of dc pulses. The results demonstrate that the microwave damage power threshold and the absorbed energy must exceed the dc pulse power threshold and the absorbed energy, respectively. The dc pulse damage data may be useful as a lower bound for microwave pulse damage data.

A novel semicircular electrode metal-semiconductor-metal (SEMSM) ultraviolet detector is modeled, investigated and characterized with a self-consistent numerical calculation method. For the purpose of model and performance verification, a comprehensive comparison of the SEMSM detector and a conventional electrode MSM detector is carried out with experimental data. The results indicate that the physical models are able to predict the enhanced device features. Moreover, the structural parameters have been adjusted appropriately to optimize the SEMSM detector. The findings show that a device with a 2 μm finger radius and 3 μm spacing exhibits outstanding characteristics in terms of a peak responsivity of 0.177 A/W at 290 nm, a maximum external quantum efficiency of over 75%, and a comparable normalized photocurrent to dark current ratio of 1.192 × 1011 W−1 at 0.3 V bias. These results demonstrate that the SEMSM detector has excellent performance for optoelectronic integrated circuit applications.

A new analytical model to describe the drain-induced barrier lowering (DIBL) effect has been obtained by solving the two-dimensional (2D) Poisson's equation for the dual-channel 4H-SiC MESFET (DCFET). Using this analytical model, we calculate the threshold voltage shift and the sub-threshold slope factor of the DCFET, which characterize the DIBL effect. The results show that they are significantly dependent on the drain bias, gate length as well as the thickness and doping concentration of the two channel layers. Based on this analytical model, the structure parameters of the DCFET have been optimized in order to suppress the DIBL effect and improve the performance.

Based on the device operation mechanism and physical model, effects of the improved hetero-material-gate (HMG) approach on deep sub-micron silicon carbide (SiC) metal-semiconductor field-effect transistor (MESFET) are analyzed. By comparing with the conventional MESFET, it is shown that the improved HMG approach induces a multi-stepped distribution of the potential in the channel, leading to an enhanced electric field at the source. Meanwhile, the position of the maximum of the channel potential is changed to the drain side compared with the dual-material-gate (DMG) device, thus the carriers in the channel are accelerated more efficiently and the variation of potential caused by drain voltage is eliminated to a certain degree, resulting in a better restraint in short-channel effect. Also, different technological parameters are designed to study the dependence of the device performance and an optimization plan is obtained, leading to a decreased sub-threshold swing. In addition, asymmetric gate structures are designed for high power application, achieving an improved distribution of the electric field at the gate edge and an enhanced breakdown voltage of the small scale device.

An improved structure of silicon carbide metal—semiconductor field-effect transistors (MESFET) is proposed for high power microwave applications. Numerical models for the physical and electrical mechanisms of the device are presented, and the static and dynamic electrical performances are analysed. By comparison with the conventional structure, the proposed structure exhibits a superior frequency response while possessing better DC characteristics. A p-type spacer layer, inserted between the oxide and the channel, is shown to suppress the surface trap effect and improve the distribution of the electric field at the gate edge. Meanwhile, a lightly doped n-type buffer layer under the gate reduces depletion in the channel, resulting in an increase in the output current and a reduction in the gate-capacitance. The structural parameter dependences of the device performance are discussed, and an optimized design is obtained. The results show that the maximum saturation current density of 325 mA/mm is yielded, compared with 182 mA/mm for conventional MESFETs under the condition that the breakdown voltage of the proposed MESFET is larger than that of the conventional MESFET, leading to an increase of 79% in the output power density. In addition, improvements of 27% cut-off frequency and 28% maximum oscillation frequency are achieved compared with a conventional MESFET, respectively.

Combining self-heating effect, mobility degradation in high electric field and avalanche generation effect, a two-dimensional electro-thermal model of the typical silicon-based n+-p-n-n+ structure bipolar transistor induced by high power microwave is established in this paper. By analyzing the variations of device internal distributions of the electric field, the current density and the temperature with time, a detailed investigation of the damage effect and the mechanism of the bipolar transistor under the injection of 1GHz equivalent voltage signals from the base and collector is performed. The results show that temperature elevation occurs in the negative half-period and the maximum temperature falls slightly in the positive half-period when the signals are injected from the collector. Compared with the former, device damage occurs easily with the signals injected from the base. Specifically, the base-emitter junction is susceptible to damage. The damage results caused by two large-amplitude signals with initial phases of 0 and respectively indicate that the injected signal with an initial phase of is liable to cause device damage. Meanwhile, the emitter series resistance can enhance the capability of the device to withstand microwave damage effectively.

A resistometric model based on microscopic analysis of electromigration failure mechanism is built. An extraction method for failure parameters of electromigration in copper interconnects is proposed from resistometric characteristics including the slope and step height. The results show that the failure time can be considered as the time to deplete grains at the cathode line end under a given stressing current. Two dominant failure modes with resuling slit and trench voids are observed in electromigration induced failures. The resistance curve for the trench-voiding failure mode consists of two characteristic regions,i.e., a step jump and an oblique line. The grain size and the extracted critical void length are lognormally distributed with close parameters. The variation in the slop of the oblique line in resistance curve with temperature obeys an exponential law. Activation energy of approximately 0.9 eV obtained from the resisometric model is consistent with that from Black equation.

A study on the influence of the external resistor and the external voltage source during the injection of the electromagnetic pulse (EMP) into the bipolar transistor (BJT) is carried out. Research shows that the increase of the external resistor Rb at base makes the burnout time of the device decrease slightly, the increase of the external voltage source Vbe at base can aid the damage of the device when the magnitude of the injecting voltage is relatively low and has little influence when the magnitude is sufficiently high causing the device appearing the PIN structure damage, and the increase of the external resistor Re can remarkably reduce the voltage drops added to the device and improve the durability of the device. In the final analysis, the effect of the external circuit component on the BJT damage is the influence on the condition which makes the device appear current-mode second breakdown.

The response of a bipolar transistor (BJT) under a square-wave electromagnetic pulse (EMP) with different injecting voltages is investigated. Adopting the curve fitting method, the relationship between the burnout time, the damage energy and the injecting voltage is obtained. Research shows that the damage energy is not a constant value, but changes with the injecting voltage level. By use of the device simulator Medici, the internal behavior of the burned device is analyzed. Simulation results indicate that the variation of the damage energy with injecting voltage is caused by the distribution change of hot spot position under different injection levels. Therefore, the traditional way to evaluate the trade-off between the burnout time and the injecting voltage is not comprehensive due to the variation of the damage energy.

A study of the internal damage process and mechanism of the typical n+-p-n-n+ structure bipolar transistor induced by the intense electromagnetic pulse (EMP) is carried out in this paper from the variation analysis of the distribution of the electric field,the current density and the temperature. Research shows that the damage position of the bipolar transistor is different with the different magnitude of the injecting voltage,when the magnitude of the injecting voltage is low the damage will appear firstly near the collector region under the center of the emitter region,and when the magnitude of the injecting voltage is sufficiently high the damage will appear firstly at the edge of the base near the emitter due to the breakdown of the PIN structure composed of the base-epitaxial layer-collector. Adopting the data analysis software,the relation equation between the device damage power P and the pulse width T under different injecting voltage is obtained. Owing to the variety of the device damage energy,it is demonstrated that the empirical formulas of the intense electromagnetic pulse P=AT-1 (A is a constant) is modified to P=AT-1.4 for the bipolar transistor.

In this paper,based on the research of the features about high voltage and high current under electrostatic discharge(ESD),the new 3D model of 0.6 μm gate-grounded NMOS(ggNMOS) ESD protection circuit with CSMC 6S06DPDM-CT02 CMOS technology have been derived from the optimization of lattice self-heating drift/diffusion model and its thermal model; systematic study about the effect of drain contact to gate spacing(DCGS)and the source contact to gate spacing(SCGS)on the relative protection circuit robustness index(turn-on voltage,breakdown voltage,self-heating peak,etc)have been done based on this model. The simulation results show that turn-on voltage and thermal balance are not influenced by the change of DCGS and SCGS,and compared to SCGS,DCGS is more sensitive to the breakdown voltage and the self-heating peak value of protection circuit. To improve the robustness of ESD protection circuit,it is not appropriate to monotonic increase the DCGS and SCGS for the reason that the breakdown voltage cannot be increased and the self-heating peak value of devices cannot be reduced by increasing DCGS and SCGS continuously. Compared to the TLP test results of 0.5 μm and 0.6 μm CMOS,a better reflection about the trend of electrical and heating features is derived from the simulation results,and the conclusions and test results are fully consistent. The reference for sub-micrometer ggNMOS ESD protection circuit layout parameter can be provided by the study.

A stressinduced voiding model based on the NabarroHerring mechanism has been proposed. The stressinduced voiding phenomena in Cu interconnects have been studied by the FIB crosssection technique and stress modeling. The driving force for the formation of stressinduced voids has been investigated. The relationship between stressinduced voiding, temperature, stress gradient and the dominant diffusion path are discussed. The results show that stress and stress gradient reach their peak values at the top surfaces of Cu M1 lines underneath the corner of the vials where voids are observed. Stress gradient shows crucial effect on the failure spot and the voiding rate. Stress migration is basically a diffusion and nucleation process of vacancies through the main diffusion path under the force of the stress gradient. The stress gradient and the diffusion terms vary oppositely with temperature and the maximum voiding rate is reached at a medium temperature.

Accelerated stress-migration testing under 200℃ of Cu (M1/M2) interconnects has been done for 700h. Finite element analysis and focused-ion beam techniques have been used to study the stress-induced voiding in the Cu interconnects with vias of 500 and 350nm in diameter. The voiding mechanism and the effect of via size on the stress migration have been studied. The results show that peak values of stress and stress gradient in M1 lines are reached underneath the edge of vias. The stress gradient shows crucial effect on the voiding process. The vacancies introduced by thermo-mechanical stress diffuse along Cu M1/SiN interfaces under the force of stress gradient and nucleate at the peak values of the stress gradient. The void grows faster along the length direction because the stress in M1 lines changes faster horizontally. The stress and stress gradient increase with increasing via diameter, leading to a faster voiding rate.