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A 650-V/84-m normally-off GaN/SiC cascode device is demonstrated with systematic static and dynamic characterizations. The cascode device features a low voltage enhancement-mode (E-mode) GaN-HEMT to enable normally-off gate control, and a 650 V normally-on SiC JFET provides the high-voltage blocking capability. The GaN/SiC cascode device exhibits many application-desired behaviors, including reverse conduction capability, avalanche breakdown capability, thermally stable threshold voltage, low input/output capacitances, no dynamic RON degradation, and negligible dynamic VTH shift. In addition, a customized double-pulse test board is built to evaluate the switching performance of this cascode device and other 650-V SiC-based power devices. This cascode device adopting low-voltage GaN HEMT has low QGRON and exhibits excellent switching performance. The switching losses (EON and EOFF) are much smaller than that of 650-V Si/SiC cascode device and comparable to that of the state-of-the-art 650-V SiC MOSFETs.

The high-speed superiority of GaN power devices with silicon-based peripheral circuits is not yet fully leveraged, mainly due to the parasitic inductance of interconnections. In this work, we demonstrate a GaN-based gate driver with an over-current (OC) protection circuit and under-voltage lockout (UVLO) circuit on a p-GaN gate power HEMT platform. The gate driver features a rail-to-rail output voltage, suppressed gate ringing, and tunable driving speed, all of which are highly desired in high-efficiency and high-speed GaN power systems. To offer timely but reliable protections, over-current protection and UVLO circuit are designed with reference to the switching speed and the threshold voltage of GaN power device. The over-current protection is implemented with a separated sensing branch and blanking time controller and the response time to an over-current event is reduced to 10 ns after the blanking time. The UVLO circuit has a fixed hysteresis of 0.5 V and its threshold voltage is specially tailored for the GaN integrated circuits.

In this work, a novel In0.52Al0.48As based top-illuminated avalanche photodiode (APD) is demonstrated. By combining the composite charge-layer design with a special p-side up etched mesa structure to zero the electric (E)-field at the periphery of this APD's multiplication (M-) layer, the edge breakdown phenomenon can be eliminated. This in turn leads to the simultaneous high-speed, high-saturation-power, high responsivity, and low-dark current performance characteristics of our APDs, which are essential for high-performance coherent receiver applications. The demonstrated device, with its simple top-illuminated structure exhibits a wide optical-to-electrical (O-E) bandwidth (21 GHz), high responsivity (5.5 A/W at 0.9 Vbr), and saturation current as high as 8 mA with a large active diameter of 24 μm for easy optical alignment. Furthermore, the nonlinear driving of a wavelength sweeping laser in the self-heterodyne beating setup can generate an optical pulse train like waveform, providing an effective optical modulation depth of up to 158%, which leads to a maximum photo-generated RF power (at 10 GHz) from our APD as high as +5.5 dBm. The excellent performance of our demonstrated APDs opens up new possibilities for the next generation of coherent receivers.

In this work, we demonstrate a novel In0.52Al0.48As based top-illuminated avalanche photodiode (APD), designed to circumvent the problem of serious bandwidth degradation under high gain (>100) and high power operation and significantly enhance the dynamic range in the established frequency modulated continuous wave (FMCW) lidar system. In our APD design, the carriers transiting through the dual multiplication (M-)layers are subjected to a stepped-up electric field profile, so they can be energized by the first step and propagate to the second step to trigger the avalanche processes. Such a cascade avalanche process leads to an ultra-high gain bandwidth product (460 GHz) with a 1 A/W responsivity at unit gain. Compared to the high-performance and commercial p-i-n PD and photo-receiver (PD + trans-impedance amplifier (TIA)) installed in the same lidar test bed, our demonstrated APD receiver (without TIA) has a larger S/N ratio under high operation gain (33 A/W) with less optical local-oscillator (LO) power required (0.25 vs. 0.5 mW), while exhibiting a wider dynamic range in each pixel. These advantages in turn lead to the construction of a better quality of 3-D lidar image by using the demonstrated APD.

We carry out an In0.53Ga0.47As/In0.52Al0.48As single photon avalanche diode which exhibits a single photon detection efficiency exceeding 60% at 1310 nm and neat temporal characteristic of 65 ps. A novel concept of dual multiplication layer is incorporated to avoid the tradeoff between dark count rate, afterpulsing and timing jitter, paving the possibility to improve the overall performance of a single photon detector. Based on this elevated device structure, we further optimize the detection efficiency and timing jitter by employing a delicate mesa structure to better confine the electric field distribution within the central multiplication region. For our detector operated under gated mode, a shorten gate width together with an increase of excess bias percentage leads to a significant improvement in the detection performance. We eventually achieve a single photon detection efficiency of 61.4% without the involvement of afterpulsing at the gating frequency of 10 kHz for 200 K.

A novel VCSEL array for high-efficiency, high-speed, and high-brightness performance is demonstrated. In contrast to the traditional VCSEL arrays, which have several independent VCSEL cavities in parallel, the novel array structure has additional passive optical waveguides connecting each cavity. In addition, Zn-diffusion and oxide-relief structures are adopted for each single element of the array to obtain the high-brightness (single-mode; SM) output and relax the RC-limited bandwidth. Comparison is made to the traditional reference array. Although the values of the oxide-relief apertures are close to each other, the novel demonstrated arrays exhibit a higher wall plug efficiency, larger maximum output power, and better eye-opening for high-speed data transmission, when both of their output optical spectra are quasi-(SM) with close narrow divergence angle values (FWHM: ∼6°). The superior performance of the demonstrated array for (quasi-) SM operation can be attributed to the dilution of the photon density in the SM output pattern from each VCSEL unit through the connections of passive waveguide. Furthermore, it also enhances the coherence between the neighboring VCSEL emitters, minimizing their interference noise which occurs under large signal modulation. This novel 940 nm VCSEL array has good potential to serve as a light source in free-space optical communication.

Novel microring based optical phase-shifters on Si-photonic platforms for microwave photonic applications are demonstrated. By using an add-drop microring structure in combination with an additional multimode interferometer (MMI), pure phase modulation with an ultrahigh modulation efficiency can be realized. Comparison is made to the reference all-pass ring design with both the same radius (5 m) and coupling coefficient (: ~0.2). The demonstrated structure minimizes the residual amplitude modulation (0.9 vs. 1.8 dB) for nearly 2 phase shifting over a wide optical window (1520 to 1570 nm) at the expense of a larger insertion loss (0.06 dB) due to the additional MMI. The demonstrated phase shifter structure is implemented in a Mach-Zehnder interferometer (MZI) for further study of its dynamic and linearity performance. Under forward bias, it exhibits a low V/I(0.4 V/12.7 mA), fast rise-time (3 ns), low insertion loss (0.2 dB), low residue-amplitude-modulations (

In this paper, a flexible multifunctional active frequency selective surface (AFSS) with miniaturized units is proposed, and it is simulated, fabricated, and measured. In our design scheme, the flexible AFSS structure adopts PIN diode for function control, realizing the arbitrary selection of electromagnetic wave transmission and reflection functions and polarization selection function in the range of 8-12 GHz. The flexible multifunctional AFSS structure consists of two FSS layers with PIN diodes on the top and bottom, a thin, flexible dielectric layer in the middle, and vias for connecting the FSS layers. The structure we design does not need additional bias feeders, which can reduce the interference to the transmission performance of AFSS. Finally, it is found that the experimental results of the AFSS structure are in good agreement with the simulation results.

A double acid corrosion and subsequent hydrothermal treatment were used to fabricate a micro–nano-structured Ti substrates (Ti–M–N). Afterward, the mesoporous polydopamine (MPDA) nanoparticles as photothermal agent were prepared and immobilized on the surface of Ti–M–N samples, in order to obtain Ti–M–N-MPDA sample. Unique micro–nanostructure properties and the photothermal effect of the modified Ti implant caused physical stress on the bacteria and the bacterial membrane damage, and eventually led to bacteria death. More importantly, based on excellent bioactivity and cytocompatibility of mussel-inspired materials, MPDA promoted adhesion, proliferation and osteogenic differentiation of mesenchymal stem cells in vitro. Furthermore, animal experiments in vivo further confirmed that the modified Ti implants could enhance osseointegration. 使用双酸腐蚀和随后的水热处理来制造微纳米结构的 Ti 衬底 (Ti-M-N)。 随后, 制备了作为光热剂的介孔聚多巴胺 (MPDA) 纳米颗粒并将其固定在 Ti-M-N 样品的表面, 以获得 Ti-M-N-MPDA 样品。 独特的微纳米结构特性和改性钛植入物的光热效应对细菌造成物理压力和细菌膜损伤, 最终导致细菌死亡。 更重要的是, 基于贻贝材料优异的生物活性和细胞相容性, MPDA在体外促进间充质干细胞的粘附、增殖和成骨分化。 此外, 体内动物实验进一步证实, 改性钛植入物可以增强骨整合

In this article, an empirical model of dynamic off -state leakage current ( I OFF) under switching operation in p -GaN gate high-electron-mobility transistors is established based on its underlying physical mechanism. The impacts of relevant switching conditions, including switching frequency, duty cycle, off -state delay time, gate drive voltage, and temperature are all considered in the modeling of dynamic I OFF. A good agreement between the modeled dynamic I OFF and experimental results is achieved. Based on this model, the off -state power consumption ( E OFF) and off/on -state power consumption ratio ( E OFF/ E ON) under dynamic switching operation can be predicted for various switching conditions. As the device worked at a high switching frequency (e.g., 1 MHz and duty cycle: 50%) with a gate drive voltage of 7 V and temperatures from 25 to 150 °C, the E OFF/ E ON ratio is calculated from 0.53% to 0.07%, which is three to two orders of magnitude higher than what is projected from static off -state current characteristics.

Short circuit (SC) capability of 650-V Schottky-type p -GaN gate high-electron-mobility transistors (HEMTs) under single and repetitive tests is characterized in this article. The investigated devices exhibit strong capability under a single SC test, but weak capability under repetitive SC tests with a bus voltage of 400 V and a gate drive voltage of 6 V. The failure mechanism under repetitive SC tests is revealed through electrothermal simulation and microscale failure spot analysis. Thermal fatigue cracks are formed due to the high temperature spike and local temperature fluctuations in the narrow GaN channel and buffer layers, leading to weak repetitive SC capability. The unique heat confinement effect in the GaN layer plays an important role in the formation of high temperature spike and fatigue cracks. The withstand time in a single SC test is several hundred microseconds due to fast drain current drop that results from high temperature and, to a lesser degree, the dynamic threshold voltage shift during the SC transient. The device failure in a single-event SC test is related to heat diffusion to a wider region. Some guidelines are proposed for handling and improving the repetitive SC capability.

A closely coupled double-channel (DC) structure realized on an 8-inch GaN-on-Si wafer is utilized to fabricate GaN high-electron-mobility-transistors (HEMTs) with enhanced RF linearity. The strong channel-to-channel coupling from this DC structure enables efficient transport of electrons between the two parallel channels to accommodate balanced carrier concentration and current density between the two channels. Consequently, the nonlinearity of source resistance under high current operations and the external bias dependence of cut-off frequencies could be substantially mitigated, leading to device linearity enhancement. Meanwhile, the DC structure enables simple top gate control that favors a high-yield planar process. Two-tone measurements at 4 GHz show that the DC GaN HEMT delivers an output 3rd-order intermodulation point (OIP3) that is improved by 5.2 dB over a single-channel GaN HEMT.

Junction termination extension (JTE) is a mature edge termination structure in Si and SiC power devices, but remains a technical challenge in GaN due to lack of mature selective area doping technique. In this work, GaN vertical p-n diodes with Hydrogen-Modulated Step Graded JTE (HMSG-JTE) are realized by gradually enlarging photolithography windows for hydrogen plasma treatment and controlled thermal diffusion of hydrogen in p-GaN. HMSG-JTE leads to a gradually decreasing hole distribution outwards from the main junction, which laterally spreads the electric field and mitigates the electric field peak under reverse bias. Consequently, the breakdown voltage of vertical GaN p-n diode is successfully boosted from 661 V (with hydrogen-plasma-based edge termination) to 1489 V with HMSG-JTE.

Owing to its energy efficiency, silicon complementary metal–oxide–semiconductor (CMOS) technology is the current driving force of the integrated circuit industry. Silicon’s narrow bandgap has led to the advancement of wide-bandgap semiconductor materials, such as gallium nitride (GaN), being favoured in power electronics, radiofrequency power amplifiers and harsh environment applications. However, the development of GaN CMOS logic circuits has proved challenging because of the lack of a suitable strategy for integrating n-channel and p-channel field-effect transistors on a single substrate. Here we report the monolithic integration of enhancement-mode n-channel and p-channel GaN field-effect transistors and the fabrication of GaN-based complementary logic integrated circuits. We construct a family of elementary logic gates—including NOT, NAND, NOR and transmission gates—and show that the inverters exhibit rail-to-rail operation, suppressed static power dissipation, high thermal stability and large noise margins. We also demonstrate latch cells and ring oscillators comprising cascading logic inverters. Through the monolithic integration of enhancement-mode n-type and p-type gallium nitride field-effect transistors, complementary integrated circuits including latch circuits and ring oscillators can be created for use in high-power and high-frequency applications.

An electrochemical study on the redox behavior of indium in the eutectic LiCl-KCl system at 450 °C was carried out with the transient techniques of cyclic voltammetry and chronopotentiometry on an inert molybdenum electrode. The reduction of In(III) was found to be a two-step process involving In(III)/In(I) and In(I)/In couples at the potentials of about −0.4 and −0.8 V versus Ag/AgCl, respectively. The redox mechanism was further confirmed by the theoretical evaluation of the number of transferred electrons based on cyclic voltammetry and characterizations of the precipitates generated by the potentiostatic electrolysis. The diffusion coefficients of indium ions in the eutectic LiCl-KCl melt at 450 °C were estimated by cyclic voltammetry and chronopotentiometry. The results obtained through the two methods are in fair agreement, delivering an average diffusion coefficient of approximately 1.8×10−5 cm2/s for In(III), and 1.4×10−4 cm2/s for In(I).

In this work, we study the gate leakage mechanisms of E-mode ${p}$ - ${n}$ junction/AlGaN/GaN (PNJ) high electron mobility transistors (HEMTs), which have been shown to deliver low gate leakage and wide safe operating gate-bias range. The intrinsic gate leakage through the PNJ-gate was found to be limited by the transport of holes through the ${p}$ -GaN layer, which occurs via Poole-Frenkel emission and phonon-assisted tunneling in low and high gate bias region, respectively. In addition, lateral leakage current and the role of variable hopping process (VRH) are also discussed. Gate leakage current models based on the revealed mechanisms can quantitatively reproduce the gate-leakage behavior in the entire relevant range of gate biases and temperatures.

The threshold voltage ( V TH) of an enhancement-mode Schottky-type p -GaN gate high-electron-mobility transistor (HEMT) is found to have a special dependence on the drain bias. The device commonly requires higher gate voltage to switch on the transistor from a high-drain-voltage off -state than what is expected from the static device characteristics. The reason behind the dynamic V TH has been proved to be the floating p -GaN layer, where charges could be stored and further influence V TH under different drain bias. In this article, a SPICE-compatible equivalent circuit model is presented according to the structure of Schottky-type p -GaN gate HEMTs. It features a floating node to imitate the charge storage process within the gate stack. Compared to conventional models, the proposed model could accurately predict the dynamic V TH characteristics and switching behaviors of power electronics circuits, where Schottky-type p -GaN gate HEMTs are deployed as power transistors. The phenomena related to the dynamic V TH, including the disappearance of Miller plateau, the overestimated false-turn- on problem, and the higher reverse conduction loss are evaluated with a half-bridge circuit and the merits of the proposed model are verified.

The crystallization behaviors of acetylated bamboo fiber (BF)/polypropylene (PP) composites were assessed using differential scanning calorimetry (DSC) through isothermal crystallization. The transcrystalline (TC) morphologies of composites were observed through polarized optical microscopy (POM), and their surface free energies were calculated based on Hoffman‒Lauritzen theory. Isothermal DSC thermograms demonstrated that acetylated BF with higher weight percentage gains (WPGs, ~ 19%) exhibited a decreased crystallization rate of the PP matrix. POM images indicated that BF as a nucleation agent induced the TC layer on fiber–PP matrix interfaces. However, when WPG reached 19%, the TC layer was not observed on the BF surface and crystal growth was principally observed in the PP matrix bulk. Based on Hoffman‒Lauritzen theory, the folding-surface free energy (σe) and the work of chain folding (q) for acetylated BF/PP composites were estimated to be higher than those for PP composites with unmodified BF. These results indicate that BFs with different WPGs could affect the crystallization behavior of the PP matrix by inducing or hindering TC on BF–PP matrix interfaces.

Avalanche photodiode (APD) is an indispensable receiver component because of its high bandwidth and low noise performance. Recently, APD reliability, under harsh environmental stresses such as high heat and humidity, has drawn great interest in the applications of passive optical network, wireless, military, and free space optics. The authors study the APD degradation under the harsh environment of high humidity and high bias. The failure morphology through cross‐sectional scanning electron microscopy is shown, and a new moisture degradation model based on electrochemical oxidation to account for the failure mechanism is developed.

A normally- off SiC-JFET/GaN-HEMT cascode device is recently proposed, featuring a cascode configuration that incorporates a high-voltage (i.e., 1200 V) SiC junction field effect transistor (JFET) and a low-voltage GaN high electron mobility transistor (HEMT). This cascode device exhibits superior thermal stability and switching performance compared to the SiC MOSFETs, but also inevitably presents challenge in dv/dt -control as the input gate does not directly control the high-voltage JFET. Since dv/dt -control is of great importance to the management and suppression of electromagnetic interference in power electronics systems, methods of controlling the dv/dt rates of SiC/GaN cascode devices need to be developed. In this article, we conduct systematic investigation on different dv/dt control schemes with theoretical analysis and experimental evaluation. A dv/dt -control method based on diode-clamped external JFET gate resistor is proposed and evaluated by comparing it with other more conventional methods. The proposed dv/dt -control method is verified to provide a balanced dv/dt -control on the device turn- on and turn- off .

Flexible pressure sensors have attracted intense attention because of their widespread applications in electronic skin, human-machine interfaces, and healthcare monitoring. Conductive porous structures are always utilized as active layers to improve the sensor sensitivities. However, flexible pressure sensors derived from traditional foaming techniques have limited structure designability. Besides, random pore distribution causes difference in structure and signal repeatability between different samples even in one batch, therefore limiting the batch production capabilities. Herein, we introduce a structure designable lattice structure pressure sensor (LPS) produced by bottom-up digital light processing (DLP) 3D printing technique, which is capable of efficiently producing 55 high fidelity lattice structure models in 30 min. The LPS shows high sensitivity (1.02 kPa

This paper aims at investigating the dynamic characteristics of a microring driven by dual arch electrodes because they are basic elements of microelectrostatic motors. The dual arch electrodes surround the periphery of the microring and are arranged symmetrically to the center of the ring. The electrodes are fixed while the microring is flexible. The electrostatic force will deform the microring, while the deflection of the microring changes the gap between the microring and the electrodes, thereby changing the electrostatic force. Therefore, this is an electromechanical coupling effect. The nonlinear partial-differential equation that governs the motion of the microring is derived based on thin shell theory. Then, based on the assumption of small deflection, the nonlinear governing equation is linearized by truncating the higher-order terms of the Taylor series expansion of the nonlinear electrostatic force. After that, the linearized governing equation is discretized into a set of ordinary differential equations using Galerkin method in which the mode shape functions of the ring are adopted. The influences of the structural damping of the microring and the span of the arch electrodes on the forced response and dynamical stabilities of the microring are investigated. The results show that the damping ratio has a great influence on the system instability during high-frequency excitation. The unstable region of the system can increase with the increase of the electrode span; the response amplitude can also be increased within a certain range.

This study investigated the effect of heat-treated veneers on the physicomechanical properties and extended creep behavior of plywood using the stepped isostress method (SSM). The results revealed that the mechanical properties of plywood composed of fully and partially heat-treated veneers were not significantly different from those of the untreated plywood. In addition, the SSM was successfully applied to constructing the plywood creep master curves. The creep resistance of the heat-treated plywood surpassed that of the untreated plywood, especially the 5T200 plywood, which also exhibited the lowest compliance values of 0.13, 0.14, and 0.15 GPa−1 at 5, 10, and 20 years, respectively.

In this work, a novel and easy-separating rare earth adsorbent (PAA/PPNWF) was successfully synthesized by generating dense polyacrylic acid (PAA) on the surface of polypropylene nonwoven fabric (PPNWF) via UV-induced photograft technology. PAA/PPNWF was characterized by optical microscope (OM), Fourier transform infrared spectroscopy (FT-IR), scanning electron microscope (SEM) and X-ray photoelectron spectroscopy (XPS). Ce3+ was used as a model for investigating the adsorption performance of PAA/PPNWF. The maximum adsorption for Ce3+ reached 364.21 mg g−1 (initial concentration = 600 mg L−1, pH 6, T = 303.15 K) and the adsorption achieved equilibrium quickly within 40 min. PAA/PPNWF could be regenerated easily and there was small loss of its adsorption capacity after regeneration (keeping 86.7% adsorption capacity after even 8 times adsorption–desorption cycle). Moreover, 96% of Ce3+ was recycled efficiently from simulated wastewater with low pH and concentration within 60 min by PAA/PPNWF, which reflects application potential of this adsorbent.

A discrete GaN power transistor’s substrate is typically connected to its source electrode. However, on the GaN-on-Si power IC platform, the high-side transistor (HS-transistor) and low-side transistor (LS-transistor) share a common substrate that cannot be simultaneously connected to both source electrodes of the two transistors. Thus, the termination of the common substrate remains an undecided issue. In this work, comprehensive TCAD simulations are exploited to reveal the influences of various substrate termination schemes. It is found the common substrate inevitably leads to severe degradation in the dynamic ${R} _{\mathrm{ ON}}$ due to back-gating effects. The mechanisms for the degradations vary with the substrate termination scheme, and will be discussed in detail. To address these issues, we propose a new GaN power IC platform on an engineered bulk silicon substrate, and study the new platform with TCAD simulations. The proposed platform provides a local electrical substrate (a p+ island) for each GaN power transistor. The source electrode of each GaN transistor is connected to its local electrical substrate, while all devices share a common mechanical substrate. The junctions between the local substrates and the underlying n-layer provide an effective isolation between GaN transistors. The back-gating effects are completely suppressed for the GaN integrated bridge circuit.

In this work, we demonstrate the high-power and high-responsivity performance of the dual multiplication (M-) layers in In0.52Al0.48As based avalanche photodiode (APD). The dual M-layer design in our APD structure effectively constrains the multiplication process to a thin high-field region rather than the whole thick M-layer. It thus minimizes the space charge effect (SCE) within and avoids increasing the tunneling dark current for the case of directly shrinking M-layer thickness in APD. Furthermore, by combining the specially designed mesa shape with this dual M-layer structure, the edge breakdown can be well suppressed. These benefits lead to an ultra-high gain-bandwidth product (450 GHz; 1 A/W at unit gain) and a high saturation current (>12 mA) can be simultaneously achieved in our device. By nonlinearly driving a wavelength sweeping laser in the self-heterodyne lidar setup, it can generate an optical pulse train-like waveform, providing an effective optical modulation depth of 200% to feed into our demonstrated APD at the receiver-end. Under such scheme, the photo-generated RF (1 GHz) power from our APD with a 6.3 A/W responsivity can be as high as +6.95 dBm at a high (7 mA) output photocurrent. Such high-power and high-responsivity characteristics of our APD can further improve the signal-to-noise (S/N) ratio and dynamic range performances in each pixel of the lidar image. A high-quality 3-dimensional (D) FMCW lidar image is constructed based on our APD, without the integration of any electrical amplifier at the receiver end.

A gallium nitride (GaN) ring oscillator based on high-performance one-chip complementary logic (CL) inverters is demonstrated on a conventional ${p}$ -GaN gate power HEMT (high-electron-mobility transistor) platform. It manifests the feasibility of the multiple-stage monolithic integration of GaN CL gates, the most energy-efficient digital circuit configuration, and consequently the potential of deploying CL circuits in the all-GaN power integration as peripheral circuits with higher energy efficiency. Thanks to the successful monolithic integration of enhancement-mode ${p}$ -channel and ${n}$ -channel field-effect transistors, the integrated CL inverters in this work present remarkable performances, including stringent rail-to-rail operations, substantially suppressed static power dissipation at both logic ‘low’ and ‘high’ states, suitable transition threshold voltages of ~2.0 V (40% of the common 5-V supply) and wide noise margins above 1.8 V (36% of 5 V).

Systematic characterizations of a cascode device with a low-voltage enhance-mode (E-mode) p -GaN gate high-electron mobility transistor as the control device and a high-voltage (HV) depletion-mode (D-mode) silicon carbide junction field effect transistor (JFET) as the voltage blocking device are presented in this article. The demonstrated device with a breakdown voltage rating of 1200 V and a static on -resistance ( R ON) of 100 mΩ features small device capacitances with fast switching speed, avalanche breakdown capability, thermally stable threshold voltage ( V TH), and no dynamic R ON degradation. To identify its safe operation in the off -state with a high drain bias, the off -state middle point voltage ( V M) between the E-mode device drain and D-mode device source is investigated. A relatively low off -state V M is achieved under both static and dynamic modes. In addition to the device-level characterization, a custom-designed double-pulse test circuit is built to evaluate the transient switching performance of the cascode device. Optimal gate drive conditions are proposed to 1) overcome the drain bias induced positive dynamic V TH shift; and 2) suppress the increased dynamic off -state leakage current ( I OFF) induced by on -state hole injection. Under 800 V/16 A testing conditions, high switching speed with the drain voltage peak slew rates of 72 V/ns during turn- on and 121 V/ns during turn- off is achieved.

This study investigated the effect of thermal management on the performance of vertical-cavity surface-emitting lasers (VCSELs). It was found that the thickness of silicon substrate, which can serve as the submount for VCSEL packages, has a strong influence on the thermal dissipation of on-chip laser sources, and eventually impacts on their output characteristics. Moreover, the improvements in optical characteristics of the on-chip VCSELs were the best heat dissipation through thinning silicon substrates to 50- $\mu \text{m}$ thickness combined with electroplated Cu with 100- $\mu \text{m}$ thickness. In addition, this study also performed COMSOL simulations. The simulation results were consistent with experimental results.

A heterojunction diode between n-type amorphous indium-gallium-zinc-oxide (a-IGZO) and p-type nickel oxide is experimentally demonstrated with self-aligned junction termination. The diode has an abrupt, non-destructive breakdown behavior, and the avalanche breakdown is confirmed by the positive temperature coefficient of the breakdown voltage. The room-temperature breakdown voltage of the device is 33 V, and the extracted critical breakdown electrical field ( ${E}_{CR}$ ) is 2.7 MV/cm. The ${E}_{CR}$ is one order of magnitude higher than that of single-crystal silicon, making a-IGZO promising for power electronics and other high-voltage applications.

The thermodynamic calculations of Al-Cu-Fe-Mg, Al-Cu-Mg-Si and Al–Fe–Mg–Si quaternary systems were carried out using CALPHAD method, based on the Al–Cu–Fe–Mg–Si thermodynamic database. The liquidus projection of Al–Cu–Fe–Mg, Al–Cu–Mg–Si and Al–Fe–Mg–Si quaternary systems at Al-rich corner were constructed, and the solidification structures of Al-12Cu-7Mg-1Fe, Al-14Cu-2Mg-4Si, Al-0.3Fe-6Mg-12Si (wt.%) alloys were analyzed by the Scheil solidification simulation. The calculated results agree well with the previous experimental data. The liquidus projections of three quaternary aluminum alloys at the Al-rich corner were accurately plotted, which could be helpful for the analysis of solidification process of multicomponent alloy systems, and provide an important theoretical basis for the material design of aluminum alloys.

The thermodynamic calculations of Al–Cu–Fe–Si quaternary system and Al–Cu–Fe–Mg–Si quinary system were carried out using CALPHAD approach based on the Al–Cu–Fe–Mg–Si thermodynamic database. The liquidus surface projection of Al–Cu–Fe–Si quaternary system at the Al-rich corner was constructed, and then the solidification structures of four Al–Cu–Fe–Si alloys were analyzed by the Gulliver-Scheil solidification simulation. The calculated results were in good agreement with the previous experimental data. The liquidus surface projections of A1–Cu–Fe–Mg–Si quinary system at the region of Al-Cu, Al-Si and Al-Mg were constructed, respectively. The liquidus projection of the multicomponent aluminum alloy system at the Al-rich side was accurately drawn, which could accurately predict the primary phase in the solidification process of the alloy. This work has an important guiding significance for the design of the aluminum alloys.

In this work, the deep-level transient spectroscopy (DLTS) is conducted to investigate the gate stack of the ${p}$ -GaN gate HEMT with Schottky gate contact. A metal/ ${p}$ -GaN/AlGaN/GaN heterojunction capacitor is prepared for the study. The DLTS characterization captures the transient capacitance change in the stack, from which the capacitance of the metal/ ${p}$ -GaN Schottky junction can be extracted. By proper selection of the rate window, the impacts of the hole insufficiency effect are avoided during trap states evaluation. Thus, the information of deep energy levels in the ${p}$ -GaN layer is revealed, which consists of an electron trap state with activation energy of 0.85 eV and a hole trap state with activation energy of 0.49 eV. The identification of these trap states in the ${p}$ -GaN layer provides a physical foundation for understanding the threshold voltage instability in Schottky-type ${p}$ -GaN gate power HEMTs.

We demonstrate a novel optical phase shifter with a bipolar junction transistor (BJT) type of device structure based on the silicon photonics foundry platform. By operating such a device in saturation mode, we obtain measured output IEC-VEC characteristics very similar to those of an ideal diode, which has a nearly zero turn-on voltage and an extremely small differential resistance. The huge amount of injected current under a small voltage swing (0.1 V) in the operation window makes it possible to obtain significant plasma induced change of the refractive index in the optical waveguide with an extremely small driving-voltage. The device has a small foot-print (500 μm in length), but exhibits small static power consumption for the π phase-shift (Pπ: 4.1 mW), reasonable propagation loss (0.02 dB/μm), small driving-voltage (Vπ: 0.12 V), fast switching time (rise/fall

In a reflective high concentration photovoltaic (RHCPV) system, density-uniformity of solar energy flux irradiates upon receiver surface can directly affect solar cell’s photoelectric conversion efficiency. Uneven high intensity irradiation will also introduce “hot spots” which cause damages to GaAs solar cells. This paper presents a two-stage reflective mirror-type concentrator to achieve the uniformity of energy flux on receiver. A computation software, TRACEPRO, is used to model and numerically simulate the two-stage reflective mirror-type concentrator. Simulation results show that a flux uniformity of greater than 99.5% and effective area ratio for the photoelectric conversion of 77.0% can be achieved. The impacts of theoretical concentration ratio to the effective area for photoelectric conversion, maximum irradiance, average irradiance, and focal length are evaluated. At constant concentration ratio, the effective area for photoelectric conversion, the maximum irradiance, and the average irradiance are not affected by the focal length of PR. When the ratio of flux (light beams collected by the receiver) and emitted flux (incident light beams) is constant, the relationships of the maximum and average irradiance and the theoretical concentration ratio are linear, and the effective area for photoelectric conversion is also not affected by the theoretical concentration ratio. Meanwhile, a microchannel radiator is designed and studied, and GaAs solar cell surface temperature decrease with the increase of flow rate in microchannel.

A 700-V normally-off ${p}$ -GaN gate power transistor with distributed built-in Schottky barrier diode (SBD) is demonstrated in this work. The transistor cell and diode cell are alternately arrayed along the device width and are locally isolated using ion implantations. The built-in SBD provides a low reverse turn-on voltage which is independent of the threshold voltage and gate bias of the transistor. Compared to the two-device scheme consisting of an anti-parallel ${p}$ -GaN gate HEMT/SBD pair, the proposed transistor exploits the common access region in both forward conduction and reverse conduction, thus a significant reduction in chip area is obtained.

HighlightsThis study designed an air-suction jujube picking and conveying device to address the problems of low transport efficiency and high damage rate.Theoretical analysis, Fluent software simulation, and prototype testing determined the diameter of the conveying pipe, the inlet and outlet diameters of the suction chamber, and the fan type and speed.A Box-Behnken center combination design in Design-Expert software was used to perform response surface orthogonal tests to optimize the device.This study provides a reference for further optimization of the air-suction jujube picking and conveying device.Abstract. To address the problems of low transport efficiency and high damage rate, an air-suction jujube picking and conveying device was designed. The main components of the device include the fan, suction chamber, and conveying pipe. Simulation of the conveying pipe and suction chamber was performed using Fluent software, and the airflow rate and pressure were analyzed for conveying pipes of five different diameters and suction chambers with different inlet and outlet diameters. In the simulation results, the diameter of the conveying pipe was 105 to 165 mm, and the outlet diameter of the suction chamber was 150 to 210 mm. The Box-Behnken center combination design method in Design-Expert software was used to perform response surface orthogonal tests with the conveying pipe diameter, suction chamber outlet diameter, and fan speed as the test factors, and the jujube conveying rate and breakage rate as the target values. The results show that the order of the test factors on the jujube conveying rate is: fan speed = conveying pipe diameter > suction chamber outlet diameter, and the order of the test factors on the jujube breakage rate is: fan speed > suction chamber outlet diameter > conveying pipe diameter. The experimental results were verified in field tests with the optimized parameters. When the conveying pipe diameter was 165 mm, the suction chamber outlet diameter was 200 mm, and the fan speed was 3254 rpm, the average jujube conveying rate in the verification test was 238.68 kg h-1. The relative error between the experimental verification value and the theoretical optimized value was 1.44%, which is less than 5%. The average value of the jujube breakage rate in the verification test was 2.18%. The relative error between the experimental verification value and the theoretical optimized value was 3.81%, which is also less than 5%. This study provides a reference for subsequent research and optimization of the air-suction jujube picking and conveying device. Keywords: Air suction, Conveying device, Conveying pipe, Jujube, Suction chamber.

Stretchable electrodes have a crucial impact on the development of flexible electronic systems. Most conventionally blended nanocomposite electrodes are incapable of achieving high stretchability, breathability, or durability. In this work, a highly conductive, breathable, and stretchable epidermal electrode (SEE) is demonstrated by designing a hierarchically interactive nano-network that is composed of elastic polymer nano-fibers and multi-level silver nano-wires (AgNWs). The elastic polymer nano-fibers act as a continuous scaffold, and multi-level AgNWs embedded in the nano-fibers form branched conductive pathways. This structure enables high conductivity of the SEE at 4800 S cm-1 (at a significantly low AgNW content of 1.59 vt%), with high stretchability and excellent durability. For example, the SEE remained conductive even at a high strain of 500%, and it also maintained its initial resistance even after 30 000 cycles of strain at 50% or being washed with water for 100 000 cycles. The SEE was prepared by a facile in situ nonequilibrium fabrication process, and can easily be produced into an elastic circuit on a large scale, which provides a foundation for integrated and multifunctional electronic skins. The SEE possesses superior mechanical conformability and permeability of gas and liquid, and therefore, it was successfully applied in measuring electrocardiogram signals and thermal therapy, and exhibited highly robust and comfortable performances even while being washed with water or undergoing complex deformations.

Enhancement-mode (E-mode) buried ${p}$ -channel GaN metal-oxide-semiconductor field-effect-transistors ( ${p}$ -GaN-MOSFET’s) with threshold voltage ( ${V}_{\text {TH}}$ ) of −1.7 V, maximum ON-state current ( ${I}_{\text {ON}}$ ) of 6.1 mA/mm and ${I}_{\text {ON}}/{I}_{\text {OFF}}$ ratio of 107 are demonstrated on a standard ${p}$ -GaN/AlGaN/GaN-on-Si power HEMT substrate. An oxygen plasma treatment (OPT) was deployed to the gated ${p}$ -GaN region where a relatively thick (i.e. 31 nm) GaN is retained without aggressive gate recess. The OPT converts the top portion of the GaN layer to be free of holes so that only the bottom portion remains ${p}$ -type while being spatially separated from the etched GaN surface and gate-oxide/GaN interface. As a result, E-mode operation is enabled while a high-quality ${p}$ -channel is retained. Multi-energy fluorine ion implantation was implemented for planar isolation of GaN ${p}$ -channel FETs with mesa edges and sidewalls eliminated. Consequently, high ${I}_{\text {ON}}/{I}_{\text {OFF}}$ ratio is obtained.

In this work, we studied the mechanisms and switching properties of AlGaN/GaN high-electron-mobility-transistors (HEMTs) passivated by amorphous-SiNx and monocrystal-like AlN. The effects of interface traps and polarization charges on current collapse are investigated by TCAD simulations and experimental characterizations. Surface/interface deep levels can be compensated by both shallow donor-like traps (SiNx passivation) and polarization charges (AlN passivation) at passivation/heterostructure interface, but with different levels of effectiveness under fast switching conditions. SiNx-passivation introduces shallow donor-like trap states with short time constant that favors a fast emission of trapped electrons in the access region and suppressed current collapse, but nevertheless exhibits more severe time-dependent recovery of dynamic on-resistance. For AlN passivation, interface traps are compensated by the fixed positive polarization charges and the off-state depletion region (in the 2DEG channel) is formed predominantly by electric-field effect, leading to an immediate accumulation of high channel electron concentration after switching the HEMT devices back to on-state and instant response of drain current to gate and drain bias. The field plate structure is necessary in SiNx-passivated devices for both current collapse suppression and electric field alleviation. With AlN passivation, the field plate can be solely designed for achieving more uniform electric field distribution for gate reliability concern without the concern of current collapse.

A three-port optical phase-shifter and Mach-Zehnder modulator (MZM) based on PNP-type bipolar junction transistor (BJT) is demonstrated. Significant plasma (injected carrier) induced changes of the refractive index for the optical waveguide become possible with an extremely small driving-voltage and a compact device size during operation of this BJT between the saturation and forward active modes. Devices with a standard MZM structure and a small foot-print (0.5 mm) exhibit a moderate optical insertion loss (2 dB), extremely small Vπ (0.18V) and Pπ (0.21mW), fast rise/fall time (~1ns), and a residue-amplitudemodulation (RAM) as small as 0.18 dB. Furthermore, thanks to the ultra-high modulation efficiency characteristic of our device, a +4.0 dB net RF-linking gain can be obtained under dynamic operation. Compared to 2-port (base-collector) forward bias operation, under three-port operation, the extra bias current from the base-emitter junction provides a lower Vπ (0.18 vs. 0.22 V), a smaller RAM (0.18 vs. 0.6 dB), and a larger RF-linking gain (+4 vs. -3.2 dB). The superior performances of the three-port to two-port operations can be attributed to the additional forward bias B-E junction being able to provide more injected carriers to induce stronger plasma effects for optical phase-shifting.

In this work, we demonstrate a novel top-illuminated avalanche photodiode (APD) with high-speed and wide dynamic range performance for coherent lidar applications, which needs simultaneous processing of weak light reflections from the object and a strong optical local-oscillator (LO) signal at the receiving end. By taking advantage of a partially depleted p-type In0.53Ga0.47As absorbing layer and a thin In0.52Al0.48As multiplication layer (88 nm), the demonstrated APDs exhibit a wide optical-to-electrical bandwidth (16 GHz) and high responsivity (2.5 A/W at 0.9 Vbr) near the saturation output current which is as high as >8 mA. Furthermore, the measured low excess noise (k = 0.14) characteristics of this device ensure its wide dynamic range performance. In addition, it should be noted that the measured nonlinear behaviors of these APDs are quite different from those of typical fast p-i-n photodiodes (PDs), which always show serious degradation in their O-E bandwidths at their saturation output. On the other hand, the measured bias dependent 3-dB O-E bandwidth of the demonstrated APDs can be pinned at 16 GHz without any degradation at around the saturation current output. Such distinct nonlinear APD behaviors can be attributed to the space-charge-screening effect induced gain reduction under high-power operation.

The development of the bionic water channel aims to replace the possible use of natural aquaporins (AQPs) for water purification, while retaining the ability of natural AQPs to carry out ultra-fast water transport and repel ions. Carbon nanotube channels (CNTCs) are a convenient membrane-based model system for studying nano-fluidic transport that replicates a number of key structural features of biological membrane channels. In this report, we describe protocols for CNTCs synthesis by ultrasound-assisted cutting of long CNTs in the presence of lipid amphiphiles. CNTCs have a similar thickness to the lipid membrane and high affinity for it. The ultra-short high-affinity CNTCs have high permeability and ion selectivity. The water permeability of the CNTCs is 1936 &plusmn, 123 &mu, m/s, which is 2.3 times that of natural AQPs, and completely rejects salt ions. In general, carbon nanotubes represent a multifunctional nanopore building module for creating high-ranking functional bionic materials. This study has reference significance for the design of new bionic water channel and the actual development of bionic membrane based on CNTs.

A new silicon carbide (SiC) planar-gate insulated-gate bipolar transistor (IGBT) is proposed and comprehensively investigated in this paper. Compared to the traditional SiC planar-gate IGBT, the new IGBT boasts a much stronger injection enhancement effect, which leads to a low on-state voltage (VON) approaching the SiC trench-gate IGBT. The strong injection enhancement effect is obtained by a heavily doped carrier storage layer (CSL), which creates a hole barrier under the p-body to hinder minority carriers from being extracted away through the p-body. A p-shield is located at the bottom of the CSL and coupled to the p-body of the IGBT by an embedded p-MOSFET (metal-oxide-semiconductor field effect transistors). In off-state, the heavily doped CSL is shielded by the p-MOSFET clamped p-shield. Thus, a high breakdown voltage is maintained. At the same time, owing to the planar-gate structure, the proposed IGBT does not suffer the high oxide field that threatens the long-term reliability of the trench-gate IGBT. The turn-off characteristics of the new IGBT are also studied, and the turn-off energy loss (EOFF) is similar to the conventional planar-gate IGBT. Therefore, the new IGBT achieves the benefits of both the conventional planar-gate IGBT and the trench-gate IGBT, i.e., a superior VON-EOFF trade-off and a low oxide field.

Novel red-emitting phosphors LiGd9(SiO4)6O2:Eu3+ (LGSO:Eu3+) and NaGd9(SiO4)6O2:Eu3+ (NGSO:Eu3+) were successfully synthesized via a high-temperature solid-state reaction. The phase formation of LGSO:Eu3+ and NGSO:Eu3+ phosphors were characterized by X-ray powder diffraction (XRD). The phosphor could be evidently excited by the near ultraviolet (NUV) light and blue light and then exhibited red light emission, which confirmed by the photoluminescence excitation (PLE) and emission (PL) spectra. According to the photoluminescence spectra, the emission peaks of LGSO:Eu3+ and NGSO:Eu3+ are mainly locate at 595 nm and 615 nm, which attribute to the 5D0 → 7F1 and 5D0 → 7F2 transitions of Eu3+. A comparative study of the optical properties of Eu3+ in the AGd9(SiO4)6O2 (A = Li, Na) red phosphor shows that the optimum concentration of LGSO:Eu3+ phosphors x = 0.20 is less than that of NGSO:Eu3+, x = 0.50, and the emission intensity of the latter is always higher than the former at the same concentration. The ultraviolet–visible spectra indicated that both of hosts tend to absorb energy in the spectral range 200–350 nm, and the band gap of host and phosphor are calculated(LGSO = 3.80 eV, NGSO = 3.99 eV), and the doping of Eu3+ helps to reduce the band gap. The internal quantum efficiency (IQE) of LGSO:0.2Eu3+ and NGSO:0.5Eu3+ were 69.6% and 77.3%, respectively. The chromaticity coordinates of LGSO:0.2Eu3+ and NGSO:0.5Eu3+ were (0.638, 0.360) and (0.643, 0.356), which exhibited high color purity. On this basis, we come to a conclusion that the prepared phosphors enjoy tremendous potentials serve as red emitting phosphor for near ultraviolet white light emitting diodes (NUV WLEDs).

The effect of Zr addition (0.005, 0.013, and 0.054 wt.%) on the microstructure and toughness of simulated coarse-grained heat-affected zone in high-strength low-alloy steels was revealed using a Gleeble 2000 thermal simulator. It was observed that elongated MnS inclusions were formed in the lowest Zr-containing steel, while only pure equiaxed ZrO2 existed in the 0.054Zr steel (Zr content of 0.054 wt.%). Complex oxide–sulfide inclusions (ZrO2 + MnS) with size of (1.40 ± 0.25) μm were formed in 0.013Zr steel (Zr content of 0.013 wt.%). The complex inclusions refined the prior austenite grain, and the nucleation of acicular ferrite was promoted compared to those of 0.005Zr steel (Zr content of 0.005 wt.%) and 0.054Zr steel. Consequently, the 0.013Zr steel possessed superior low-temperature impact toughness in relation to 0.005Zr and 0.054Zr steels. Thus, moderate Zr addition can be considered as an effective method to refine the structure and improve the mechanical properties of the coarse-grained heat-affected zone.

A planar gate U-shaped (PGU) channel silicon-on-insulator (SOI) lateral insulated gate bipolar transistor (LIGBT) featuring divided gates (G1 and G2) is proposed, which aims to suppress the gate voltage (VG) overshoot and improve the di/dt controllability. In the conventional PGU structure, the hole accumulating and the electric potential rising in the JFET region leads to a displacement current to overcharge the gate during the turn-on transient. Two gate connection modes (Mode A and B) for the proposed PGU structure are discussed. Mode A with a grounded G2 can effectively enhance the VG stability, however, degenerating the on-state voltage (VON). Mode B shields the displacement current by a pre-charged G2. G2 is driven with a separate gate resistor to the main gate G1, which results in an improved di/dt controllability without deteriorating VON. When adjusted for the same turn-on loss of 5.28mJ/cm2, the di/dt of the proposed PGU structure with mode B is 74% lower than that of the conventional PGU structure.

In this paper, we carried out a systematic investigation on gate degradation and the physical mechanism of the Schottky-type ${p}$ -GaN gate HEMTs under positive gate voltage stress. The frequency- and temperature-dependent measurements have been conducted. It is found that the time-dependent gate degradation exhibits weak relevance with frequencies ranging from 10 to 100 kHz under dynamic gate stress and is similar to that in static gate stress. Both the gate breakdown voltage (BV) and mean-time-to-failure (MTTF) show positive temperature dependence. Moreover, the current–voltage ( I–V ) characteristics and threshold voltage ( ${V}_{\text {TH}}$ ) instability of ${p}$ -GaN devices before/after gate degradation are compared and analyzed. The degraded Schottky junction exhibits an ohmic-like gate behavior. It is revealed that under a large gate bias stress, high-energy electrons accelerated in the depletion region of the ${p}$ -GaN layer would promote the formation of defect levels near the metal/ ${p}$ -GaN interface, leading to the initial ${p}$ -GaN layer degradation. The subsequent high gate leakage density could cause the final degradation of the AlGaN barrier.

A new superjunction MOSFET (SJ-MOSFET) architecture with dual built-in Schottky diodes is proposed and studied with the numerical TCAD simulations. This letter is based on silicon. One Schottky contact is formed at the top of the n-pillar, while the other is formed at the bottom of the p-pillar. During the reverse conduction period, the Schottky junctions turn on at a lower voltage than the PN junction. The current flows through n-pillar and p-pillar in parallel, so the potential difference across the PN junction is kept below its turn-on voltage. Thus, minority carrier injection through the PN junction is completely suppressed, leading to a superior reverse recovery performance. Integration of a single Schottky contact to either the n-pillar or the p-pillar cannot completely suppress the turn-on of the PN junction in the SJ-MOSFET due to the potential drop created by the current through only one type of the pillars. Furthermore, the proposed dual-Schottky SJ-MOSFET reduces the gate charge ( ${Q} _{\mathrm {G}}$ ) and the gate-to-drain charge ( ${Q} _{\mathrm {GD}}$ ), compared with the conventional SJ-MOSFET, leading to better figures of merit.