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A new leakage-prevention pixel circuit is proposed to maintain the driving capability of its driving thin-film transistors (TFTs) at a low frame rate of 15 Hz for use in active-matrix organic light-emitting diode (AMOLED) displays. The proposed leakage-prevention mechanism generates a compensating leakage current that reduces the source-to-drain voltage of the switching TFT, thereby lessening the fluctuation of the stored driving voltage when the frame rate is reduced from 60 to 15 Hz. Moreover, the proposed circuit can compensate for the threshold voltage variation in low-temperature polycrystalline silicon TFTs (LTPS TFTs) and current–resistance drops in VDD lines. To validate the performance of the compensation and leakage prevention, simulation models based on the measurement of the fabricated LTPS TFTs and an organic light-emitting diode (OLED) are established. The experimental results confirm that the leakage current of the gate node is successfully suppressed from 50.34 to 1.25 pA by the proposed leakage-prevention mechanism. Also, within the long emission period, the highly uniform OLED currents at low, medium, and high gray levels are achieved, verifying the feasibility of the proposed pixel circuit.

A new pre-bootstrapping method (PBM) using hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) for a gate driver that is used in high-frame-rate or high-resolution displays is presented in this article. The PBM utilizes the capacitive coupling effect to bootstrap the gate voltage of the driving TFT twice to improve the insufficient field-effect mobility of the a-Si:H TFT without the need to enlarge the driving TFT. To investigate the driving capability of an a-Si:H TFT varying with the gate bias, a simulation model, based on the measured transfer curves of an a-Si:H TFT, is developed. Based on the specifications of 5.9-in panel with full high-definition resolution and 60 Hz frame rate, gate drivers with different structures are fabricated and compared. The experimental results demonstrate that the rising and the falling time of the output waveform generated from the gate driver with PBM are 45.21% and 32.04% shorter than those of the conventional gate driver. Furthermore, under a doubling of loadings, a 50 kHz clock frequency, and operation at −20 °C, the proposed PBM improve the performance of a gate driver. During an accelerated lifetime test at 85 °C, the gate driver with PBM can generate stable output waveforms for 864 h, verifying its long-term reliability.

This work proposes a hydrogenated amorphous silicon (a-Si:H) thin-film transistor (TFT) gate driver with a low-leakage capacitive coupling structure to reduce the delay of the clock signal. The proposed circuit suppresses the fluctuation in the gate node of the driving TFT induced by clock-feed-through effect, reducing the leakage current that flows from the clock signal line to the power source line with a low voltage level. This reduction in the leakage current can improve the degradation in the voltage of the clock signal and thus avoid the increase in the rising time of the scan pulse. Measurements for extracting the drain current versus gate-to-source voltage ( $\text{I}_{\mathrm {D}}$ - $\text{V}_{\mathrm {GS}}$ ) curves of a fabricated a-Si:H TFT are made to establish a simulation TFT model by fitting the obtained curves. For the same parameters of the TFTs and capacitances, the leakage current and the rising time of the output waveform of the proposed circuit are 45.45% and 21.36% lower, respectively, than those of previously developed gate driver.

This work proposes a new pixel circuit for active-matrix organic light-emitting (AMOLED) smartwatch displays with a low frame rate. Within the long emission period, the leakage current of a low-temperature polycrystalline silicon thin-film transistor (LTPS TFT) is reduced to suppress the distortion of the driving voltage at the gate node of the driving TFT. Based on the measured electrical characteristics of a fabricated p-type LTPS TFT, the HSPICE model is established to verify the feasibility of the proposed circuit. The analytical results indicate that the relative OLED current error rates are all below 4.73%, as the threshold voltage of TFT varies by ±0.5 V. Notably, the OLED current varies by only 2.94% during the emission period of 66.7 ms at a medium gray level, demonstrating the effectiveness of the leakage prevention scheme.

This paper proposes a pixel circuit combining with a leakage current prevention mechanism for use in wearable AMOLED displays. The pixel circuit consists of nine TFTs and two capacitors to eliminate the variations of the driving current caused by the threshold voltage $(\mathrm{V}_{\text{TH}})$ variations of the driving TFT. The variation of the voltage at the gate node of the driving TFT is compensated for by using a capacitor to store a specific voltage to minimize the leakage current of LTPS TFTs. Moreover, the proposed circuit prevents the current from flowing through the OLED during the programming period. The simulation results indicate that the proposed pixel circuit successfully compensates for the variations of $\mathrm{V}_{\text{TH}}$ of the driving TFT and solves the leakage current problem. Therefore, the proposed pixel circuit is appropriate for low- frame-rate displays.

This paper proposes a new p-type LTPS TFT pixel circuit for use in AMOLED smartwatch applications with a frame rate of 15 Hz. By adopting the negative feedback scheme, the voltage distortion at the gate node of the driving TFT is greatly ameliorated. The HSPICE simulation demonstrates that the relative current error rates caused by ±0.5 VV TH variations of TFTs are all suppressed below 4.8%. Moreover, the distortions of OLED currents during the long emission period of 66.67 ms are only 2.58 nA at the low gray level when the pixel circuit is operated at a frame rate of 15 Hz.

This work investigates the long-term behavior of photo thin-film transistors (TFTs) that are covered with color filters and based on hydrogenated amorphous silicon (a-Si:H) technology. Based on the electrical characteristics and the optical responses of these TFTs as measured under different stress conditions, a new method for driving a photo TFT with a negative gate-source voltage is proposed to suppress the degradation of the photocurrent. The effectiveness of the newly proposed method is verified using our previously developed white-light photocurrent gating (WPCG) structure, the measurement of photocurrents, and the established models of red, green, and blue photo TFTs. An accelerated lifetime test of the fabricated circuit was carried out at 70 °C and under the illumination of ambient light for 504 hours, demonstrating that the proposed method improves the long-term reliability of optical sensors.

A new capacitive coupling method to enhance the driving performance of hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) in high-resolution applications is presented. The gate voltage can be enlarged by the entirely transmitted high voltage of a global direct current power source line ( $V_{\mathrm{ DD}}$ ). Established models that are based on the measured electrical characteristics of fabricated a-Si:H TFTs with different aspect ratios are used to evaluate the feasibility of this proposed method in the gate driver. The maximum voltage of the gate voltage can be increased from 37.3 V to 47.6 V when $V_{\mathrm{ DD}}$ is set to 20 V, improving the driving capability of the gate driver by more than 17%, based on the specifications of a 5.99 inch HD + ( $720 \times 1440$ ) panel at a frame rate of 120 Hz.

Because of oscillatory asymptotic mechanical behavior, it is difficult to properly examine the extent of the near-front singular-dominant region for interface cracks. An approach is propose...

The present work deals with the modeling of multi-defected solids under the action of large deformation. A micromechanics constitutive model, formulated in terms of the compressible anisotropic NeoHookean strain energy density function, is presented to characterize the corresponding nonlinear effective elastic behavior. By employing a scalar energy parameter, a correspondence relation between the effective hyperelastic model and this energy parameter is established. The corresponding effective material coefficients are then evaluated through combined use of the “direct difference approach” and the extended “modified compliance contribution tensor” method. The proposed material constitutive model can be further used to estimate the effective mechanical properties for engineering structures with complicated geometry and mechanics and appears to be an efficient computational homogenization tool in practice.

This letter discusses the frequency effect of polymer-stabilized blue-phase liquid crystal (BPLC) on the data voltages of a conventional pixel circuit and develops a new pixel buffer that exploits amorphous indium–gallium–zinc-oxide thin-film transistors (TFTs). During high-speed operations, BPLC seriously distorts data voltages because of the highly frequency-dependent dielectric anisotropy. To lessen the frequency-dependent effect of BPLC, a source-follower structure is integrated into the proposed pixel buffer to prolong the charging time of the BPLC cell. The experimental results show that the source-follower yields linear output characteristics. Further compensation for TFT ${{\text{V}}}_{{\mathrm{TH}}}$ shifts and suppressing the leakage current are confirmed to make the data voltages on the BPLC cell highly uniform and stable.

This paper proposes a damage parameter, Mint, for evaluation of the surface energy associated with the formation of multiple cracks terminating at a bimaterial interface. The study consider...

A numerical method is proposed for calculation of the mixed-mode stress intensity factors at a crack tip in anisotropic functionally graded materials (FGMs). The method is constructed by introducing the nonhomogenized displacement discontinuities technique. With this method, the stress intensity factors can be effectively determined by direct use of the finite-element results of the near-tip displacement discontinuities across the crack surfaces. The result from the proposed method can also be used as an effective indicator for evaluating the accuracy of the calculation. This proposed approach is applicable for problems containing curved cracks of arbitrary shape in general anisotropic FGMs.