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The degradations of electrical parameters for depletion mode GaN devices in the cascode configuration under repetitive hard-switching stress are investigated in detail. With the help of TCAD simulations and comprehensive experimental analysis, two different mechanisms behind the degradations are demonstrated. Under a relatively low Vds hard-switching condition, hot electron injection is proved to be the only influence factor, which results in the increase of Rdson under low gate bias voltage. Furthermore, under the low Vds switching condition, influence of different stages on the degradation trend of the device is verified. It is found that the turn-on procedure has a greater degradation risk due to higher energy consumption. However, when Vds is high during hard-switching, the surface trapping effect is triggered due to high electric field at the end of gate field plate, and finally results in the device degradation trend. It results in the increase of the Rdson under high gate bias condition. Therefore, considering the stability and safety of power systems which adopt cascode devices as switches, shorter turn-on time or a soft-switching operation condition should be considered in the design.

This paper makes the comparisons on the behaviors of three types of commercial GaN power switching devices, including Schottky gate p-GaN high electron mobility transistor (HEMT), ohmic gate p-GaN HEMT with hybrid drain, and Cascode GaN device, under single-pulse and repetitive unclamp-inductive -switching (UIS) conditions by experiments and simulations. It shows that all the three types of GaN devices withstand the UIS stress by storing energy in parasitic capacitances rather than by avalanche process, which is a different phenomenon compared with traditional Si/SiC devices. However, the failure phenomena under single-pulse UIS condition are different. For the two types of p-GaN gate devices, the inverse-piezoelectric induced punch-through makes the burnout under drain contact region. For the Cascode device, the breakdown of the inner Si device dominates the failure. As for the behaviors under repetitive UIS stresses, p-GaN gate device with hybrid drain performs the best, Schottky gate p-GaN HEMT shows the most serious electrical performance degradations due to the trapping effects and carrier storage phenomena, Cascode GaN device exhibits stable threshold voltage and acceptable degradations of on-state resistance due to the existence of inner Si device.

Nanomaterials with low-dimensional morphology display unique properties in catalysis and related fields, which are highly dependent on the structure and aspect ratio. Thus, accurate identification of the structure and morphology is the basis to correlate to the performance. However, the widely adopted techniques such as XRD is incapable to precise identify the aspect ratio of low-dimensional nanomaterials, not even to quantify the morphological uniformity with statistical deviation value. Herein, ZnO nanorod and nanosheet featured with one- and two-dimensional morphology were selected as model materials, which were prepared by the hydrothermal method and statistically characterized by transmission electron microscopy (TEM). The results indicate that ZnO nanorods and nanosheets display rod-like and orthohexagnal morphology, which mainly encapsulated with {100} and {001} planes, respectively. The 7.36 ± 0.20 and 0.39 ± 0.02 aspect ratio (c/a) of ZnO nanorods and nanosheets could be obtained through the integration of the (100) and (002) diffraction rings in selected area electron diffraction (SAED). TEM combining with the SAED is favorable compare with XRD, which not only provides more accurate aspect ratio results with standard deviation values but also requires very small amounts of sample. This work is supposed to provide a convenient and accurate method for the characterization of nanomaterials with low-dimensional morphology through TEM.

In this letter, we comprehensively investigate the electrical properties of the 1200 V planner-gate 4H-SiC power metal–oxide–semiconductor field-effect transistors under the mechanical strains. Three kinds of strains, including the biaxial strain, uniaxial strain parallel to the gate channel, and uniaxial strain perpendicular to the gate channel, are applied using the wafer bending system. It is found that all kinds of compressive strains improve the drain current ( Id ) under the same gate voltage ( Vg ) and shift the threshold voltage ( V th) negatively, while the tensile strains decrease Id and shift V th positively. The V th shift mainly results from the strain modulated band structure in the poly-Si gate. Under the same overdrive gate voltage ( V ov), biaxial strains merely change Id , while both the parallel and perpendicular uniaxial compressive strains enhance Id . The uniaxial compressive strain elevates the electron mobility in the inverted channel by repopulating more electrons into the valleys with a smaller conduction effective mass, which results in the current improvement.

In this letter, comprehensive static and dynamic electrical parameter degradations of p-GaN gate high electron mobility transistor (HEMT) under repetitive short-circuit (SC) stresses are presented. Meanwhile, the mechanisms behind those degradations are first distinguished. The results indicate that both the gate region and the access region are damaged by the SC stresses, dominating the shifts of electrical parameters. Moreover, a method by modeling the output capacitance is proposed to characterize damages in access region. Finally, the switching characteristics after the stresses are investigated, it is found that the switching speed benefits from the increase in the gate leakage current. Considering the aging of p-GaN HEMT under long-term operation conditions, all the damages brought by repetitive SC stresses should be eliminated to prevent the failure of p-GaN gate and the increase in conduction loss.

In this work, a high-voltage amorphous In-Ga-Zn-O (a-IGZO) thin-film-transistors (TFTs) with the stair gate-dielectric at the drain side were demonstrated. The electrical properties of the proposed TFTs were comprehensively investigated. The breakdown voltage ( ${V} _{\text {BD}}$ ) was significantly enhanced, and the ${V} _{\text {BD}}$ of over 60 V is achieved in the TFT with the stair length ( ${L} _{\text {stair}}$ ) of $3~\mu \text{m}$ . The TCAD simulation and emission microscope (EMMI) measurements are performed to reveal the working and breakdown mechanisms of the proposed stair gate-dielectric TFTs. The descending electron current density in the channel lowers the stair-gate TFTs’ ON-current. Meanwhile, the stair-gate-dielectric region endures a strong electric field and improves the ${V} _{\text {BD}}$ of the device. Finally, the exponential trade-off relationship between the ${V} _{\text {BD}}$ and the ON-state resistance ( ${R} _{\text{ON}}$ ) was established.

The 4H-SiC trench metal–oxide semiconductor field-effect transistor (MOSFET) with the grounded p+ shielding region is one of the commercial devices with superior gate oxide reliability. However, the introduced JFET region seriously increases the influence of quasisaturation (QS) on device electrical performances, resulting in the poor output and transfer characteristics. In order to investigate the mechanism of QS effect, the output characteristic is physically analyzed by monitoring the variations of the electric field, the electron concentration, the electron velocity, and the depletion layer inside the cell structure. It is demonstrated that the channel electrons are injected into the JFET current path from the channel region by a forward bias to the channel and JFET junction at QS state. Moreover, based on the Lombardi CVT model, the influence of QS effect on devices with different channel electron mobilities is first studied. An improved SiC trench MOSFET with two-level doped current spreading layers is proposed to decrease the JFET resistance and suppress the QS effect. The QS current and the peak transconductance are improved by 42% and 23%, respectively. The specific ON-state resistance is decreased by 10% and the figure of merit is improved by 7%.

Lithium–sulfur (Li–S) batteries are promising energy‐storage devices for future generations of portable electronics and electric vehicles because of the outstanding energy density, low cost, and nontoxic nature of S. In the past decades, various novel electrodes and electrolytes have been studied to improve the performance of Li–S batteries. However, the very limited lifespan and rate performance of Li–S batteries originating from the dissolution and diffusion of long‐chain polysulfides in liquid electrolytes, and the intrinsic poor conductivity of S severely hinder their practical application. Herein, an electrospinning method was developed to fabricate a thin conductive interlayer consisting of meso-/microporous N/O dual-doping carbon nanofiber (CNF). The freestanding 3D interwoven structure with conductive pathways for electrons and ions can enhance the contact between polysulfides and N/O atoms to realize the highly robust trapping of polysulfides via the extremely polar interaction. Consequently, combining the meso-microporous N/O dual-doping CNF interlayer with a monodispersed S nanoparticle cathode results in a superior electrochemical performance of 862.5 mAh/g after 200 cycles at 0.2 C and a cycle decay as low as 0.08% per cycle. An area specific capacity of 5.22 mAh/cm2 can be obtained after 100 cycles at 0.1 C with a high S loading of 7.5 mg/cm2.

Two-dimensional (2D) MXenes, including carbides, nitrides, and carbonitrides MXene, have been proved to be a possible candidate as anode materials of sodium-ion batteries. This paper focuses on the electronic properties and the electrochemical performance of nitrides MXene. First, density functional theory simulations were utilized to disclose the geometric structure and electronic properties, Na diffusion path, and storage behaviors of titanium carbonitrides Ti3CNTx, nitrides MXene Ti3N2Tx, and carbides MXene Ti3C2Tx with oxygen terminations, predicting the more excellent performance of Ti3N2O2 than Ti3C2O2. Also, then the structure characterization and electrochemical performance experiments of Ti3C2Tx and Ti3CNTx were conducted to verify the theoretical predictions and test the cycling performances. The superior performance of Ti3N2O2 originates from the stronger connection of O-Ti-N than that of O-Ti-C, resulting in the stackings of Ti3N2O2 being tighter and the interlayer spacings being larger than that of Ti3C2O2, which is advantageous to sodiation and desodiation. The capacity of Ti3CNTx increased again to 145 mAh/g after 35 cycles at a current density of 20 mA/g, which demonstrated a better rate performance than Ti3C2Tx corroborated by the diffusion barriers of the theoretical calculation results. Ti3CNTx exhibits a good cycling performance of 110 mAh/g (≈60% of the initial value) after 200 cycles, which is better than that of 87 mAh/g (≈51% of the initial value) of Ti3C2Tx. It is worth noting that all these performances ensure that nitride MXene is more suitable as the anode material of Na-ion batteries than carbide MXene. These findings are conducive to expanding the MXene family and promoting their application in energy storage applications.

Electrical parameters degradations of p-GaN high-electron-mobility transistors (HEMTs) under repetitive unclamped-inductive-switching (UIS) stresses have been investigated in this article. With the help of the TCAD simulations, the experimental frequency-dependent conductance analyses ( $G_{p}/\omega$ ), and the experimental capacitance analyses ( $C_{\mathrm {ds}}$ ), it is demonstrated that the trapping effects near the gate region and in the gate to drain access region dominate the degradations. Due to the extremely high-voltage bias during UIS stresses, the trapping of electrons happens near gate region, resulting in the positive shifts of threshold voltage ( $V_{\mathrm {th}}$ ), the degradations of ON-state resistance, the reductions of the gate leakage current, and the reductions of OFF-state leakage current ( $I_{\mathrm {dss}}$ ). Two experimental methods, the $C_{\mathrm {ds}}$ analyses and the $G_{p}/\omega $ analyses, are introduced to characterize the trapping effects in p-GaN HEMT for the first time. Nonetheless, the large current surging during UIS stresses enhances the impact ionization and leads to the increase in $I_{\mathrm {dss}}$ . The analyses above have been validated by the TCAD simulation successfully. For switching parameters, such as the voltage rises/falls time, which should be considered when designing power electronic systems, the increase in $V_{\mathrm {th}}$ induced by the UIS stresses dominates the changes.

The degradation of electrical parameters for SiC power metal–oxide–semiconductor field-effect transistors (MOSFETs) under repetitive switching stress is investigated in detail. The dominant degradation mechanism is demonstrated to be the injection of negative charges into the gate oxide interface along the channel. It results in the increase in threshold voltage ( $V_{\mathrm {th}}$ ) and the increase in ON-state resistance ( $R_{\mathrm {dson}}$ ) under low gate bias condition. Furthermore, the influences of different stages during an entire switching process on the degradation trend of the device are verified. It is found that the charges are mainly injected into the gate oxide during the conduction stage. Even though the turn-on stage rarely results in the injection directly, it increases the junction temperature ( $T_{j}$ ), contributing to the injection of charges during the conduction stage. However, the turn-off stage barely degrades the performance of the device. The research also proves the robustness of SiC power MOSFETs under repetitive out-of-safe operating area (SOA) switching conditions. Moreover, the degradation of switching behaviors of the device is analyzed. The increased $V_{\mathrm {th}}$ increases the Miller plateau voltage ( $V_{\mathrm {gp}}$ ), leading to the increase in turn-on time and the decrease in turn-off time. Hence, the turn-on dissipated energy ( $E_{\mathrm {on}}$ ) increases, while the turn-off dissipated energy ( $E_{\mathrm {off}}$ ) decreases after enduring the stress.

Sodium-ion capacitors (SICs) are extremely promising due to the combined merits of high energy-power characteristics and considerable price advantage. However, it is still difficult to achieve high energy-power outputs and cycle stability in a typical configuration of the metal-based battery-type anode and activated carbon capacitor-type cathode due to the kinetic mismatching. In this work, a carbon nanosheet (PSCS-600) with large interlayer spacing of 0.41 nm derived from the bio-waste pine cone shell was prepared. Besides, the covalent triazine framework derived carbon (OPDN-CTF-A) was obtained through ionothermal synthesis strategy, exhibiting beneficial hierarchical pores (0.5–6 nm) and high heteroatoms (5.6 at% N, 6.6 at% O). On this basis, the all-carbon SICs were fabricated by the integration of PSCS-600 anode and OPDN-CTF-A cathode. The device delivered high energy density 111 Wh kg−1, high power output of 14,200 W kg−1 and ultra-stable cycling life (∼90.7% capacitance retention after 10,000 cycles). This work provides new ideas in fabricating carbon-carbon architectural SICs with high energy storage for practical application.

The failure mechanism of double-trench silicon carbide (SiC) power metal–oxide–semiconductor field-effect transistors (MOSFETs) under single-pulse avalanche stress is verified. Instead of the widely reported burning out failure mechanism for planar-gate devices, double-trench SiC power MOSFETs suffer from a totally different failure mechanism, as they can only endure a much lower maximum single-pulse avalanche energy ( $E_{\mathrm{ as}}$ ). It is found that during the avalanche process, obvious gate leakage current ( $I_{g}$ ) appears, which is resulted from the high impact ionization rate and high electric field along the gate trench bottom oxide interface, especially the trench corners. The $I_{g}$ continuously grows along with the increase in the peak load current ( $I_{\mathrm{ peak}}$ ), eventually leading to the breakdown of the trench bottom gate oxide under avalanche status. By increasing the value of gate resistor ( $R_{g}$ ), the $I_{g}$ raises the gate–source voltage ( $V_{\mathrm{ gs}}$ ) during the avalanche process, forcing the channel region in an inversion state. Part of the avalanche current is then diverted into the forward conductive current, changing the failure mode from breakdown of the gate oxide to burning out of the entire device. Moreover, the influence of different avalanche stress conditions, including the di / dt and the ambient temperature ( $T_{a}$ ), on the single-pulse avalanche endurance capability of double-trench SiC power MOSFETs is investigated. All the samples express a similar failure phenomenon. The higher the di / dt is, the shorter the avalanche time the device can endure. This is because the higher $I_{\mathrm {peak}}$ results in a higher $I_{g}$ during the avalanche process, leading to early failure of the gate oxide. However, the $T_{a}$ rarely influences the $E_{\mathrm{ as}}$ of the device, indicating that the single-pulse avalanche-induced failure of double-trench SiC power MOSFETs has little business with the melting of the lattice or package, demonstrating the correctness of the failure mechanism proposed in this article.

The electrochemical performance of hard carbon in sodium storage is still limited by its poor cycling stability and rate capability because of the sluggish kinetics process. In this study, we use a simple and effective method to accelerate the kinetics process by engineering the structure of the electrode to promote its surface and near-surface reactions. This goal is realized by the use of slightly aggregated ultra-small carbon spheres. The large specific surface area formed by the small spheres can provide abundant active sites for electrochemical reactions. The abundant mesopores and macropores derived from the secondary particle piled structure of the carbon spheres could facilitate the transport of electrolytes, shorten the diffusion distance of Na+ and accommodate the volume expansion during cycling. Benefiting from these unique structure features, PG700-3 (carbon spheres with the diameters of 40–60 nm carbonized at 700 °C) exhibits high performance for sodium storage. A high reversible capacity of 163 mAh g−1 could be delivered at a current density of 1.0 A g−1 after 100 cycles. Interestingly, at a current density of 10.0 A g−1, the specific capacity of PG700-3 gradually increases to 140 mAh g−1 after 10 000 cycles, corresponding to a capacity retention of 112%. Given the enhanced kinetics of SIBs reactions, PG700-3 exhibits an excellent rate capability, i.e., 230 and 138 mAh g−1 at 0.1 and 5.0 A g−1, respectively. This study provides a facile method to attain high performance anode materials for SIBs. The design strategy and improvement mechanism could be extended to other materials for high rate applications.

In this brief, the contact etch stop layer (CESL) stressor is introduced to improve the performance of n-type lateral double-diffused MOSFET (nLDMOSFET) with various operating voltages. Three groups of nLDMOSFETs were studied to demonstrate the effects of the CESL stressor. The electrical properties were carefully characterized, and the tip-enhanced Raman spectroscopy measurements were carried out to examine the process-induced strain directly. It is found that nLDMOSFETs with the strained SiN CESL have larger output current, transconductance ( ${g} _{m}$ ), and higher breakdown voltage (BV). The strained SiN CESL introduces tensile strain in the device and results in the performance boosts, which are verified by negative Raman peak shift mappings and TCAD simulations. The strained SiN CESL could effectively decrease the specific ON-resistance ( ${R} _{\text {on}}$ ) and improve the BV of the nLDMOSFET, due to the mobility enhancement.

The short-circuit (SC) failure mechanism of double-trench silicon carbide (SiC) power metal–oxide–semiconductor field-effect transistors (MOSFETs) is comprehensively studied and analyzed. Unlike traditional planar-gate devices which die from thermal runaway, the double-trench ones exhibit a different SC failure phenomenon. After enduring an ultimate SC stress cycle, the gate of the double-trench device breaks down while the conducting and blocking characteristics of the body diode remain stable. During the SC process, a substantial negative gate current from the semiconductor side to the poly gate side is observed. Silvaco TCAD simulations demonstrate that ultrahigh current density and impact ionization appear at the gate trench corners simultaneously, driving the generated hot holes through the oxide, forming the negative gate current. The sustained action of this gate current component on the oxide finally results in the failure. Moreover, the influence that bias voltages have on the SC endurance capability of the device is analyzed. In general, the higher the ${V}_{\text {ds}}$ and ${V}_{\text {gs}}$ are the shorter the SC endurance time will be. It is also found that the double-trench device fails with a higher junction temperature when stressed under a lower ${V}_{\text {ds}}$ condition, implying that the temperature rarely affects the failure, proving the correctness of the proposed SC failure mechanism.

This letter firstly reveals the single pulse unclamped-inductive-switching (UIS) withstanding physics and failure mechanism for p-GaN high electron mobility transistor (HEMT) with Schottky type gate contact. Unlike silicon/silicon carbide (Si/SiC)-based devices, the p-GaN HEMT withstands the surge current from load inductor by storing the energy into the output capacitance of the device, rather than dissipating the energy by avalanche process. To describe the UIS process, physics-based models are proposed. Also, by the simulations and de-cap/de-layer experiments, the failure mechanism is presented as a different manner compared with Si/SiC-based devices. The high voltage during the UIS process introduces high electric field near the drain contact, which leads to the inverse-piezoelectric effect, then bringing the rise-up of the leakage current and high power dissipation. As a result, the region near drain contact is burned by thermal runaway. Moreover, it is demonstrated that higher bus voltage and larger load inductance will increase the UIS-induced failure risk, while the gate resistance, turn- off gate voltage and ambient temperature exhibit little influences upon the UIS withstanding capability of the device.

In this letter, a model that predicates the degradation of 4H-SiC power metal-oxide-semiconductor field-effect transistors under repetitive avalanche stress is proposed. Since positive charges are injected into the gate oxide interface of the JFET region, the gate-drain capacitance $(C_{gd})$ is chosen as the targeted parameter to quantify the avalanche induced degradation. The relationship between the increment of the $C_{gd}$ and the injected charge density is calculated and validated to demonstrate the rationale of the model. It is found that the increment of $C_{gd}$ has a linear relationship with the logarithm of the total avalanche energy ( E AV) dissipated on the device. Excellent agreement is also achieved between the simulated degraded data and the measured one, further proving the accuracy of the proposed degradation model.

The complete avalanche process of the trench-gate filed-stop insulated gate bipolar transistor (FS-IGBT) is first investigated based on an infrared visualization technology called step-control infrared thermography method. By this method, the details about the generation, movement, and accumulation of the heat can be monitored during the entire avalanche process, and a new avalanche weak spot of the trench-gate FS-IGBT has been found. It shows that the heat generation takes place not only in the cell region but also at the termination with the increasing avalanche time. The termination region exhibits the highest lattice temperature in the end due to poor heat dissipation. Therefore, the cells close to the termination have much higher p-base resistances due to the high lattice temperature, which results in the triggering of the parasitic n-p-n transistors in these areas. The infrared visualization method can also be extended to other power devices for avalanche research works.

This brief first reports the behaviors of three different kinds of 650-V commercial normally- OFF GaN devices under repetitive reverse freewheeling stress, and the mechanisms are illustrated by experiments and mix-mode technology computer-aided design simulations. After the stress, unlike the stable behaviors of the device with ohmic-type metal/p-GaN gate stack and the device with cascode structure, there are degradations on the threshold voltage, the ON-state resistance, and the source-to-drain reverse voltage for the device with Schottky-type metal/p-GaN gate stack. During the freewheeling stress, there is a dynamic positive gate to drain voltage on the devices. Especially, the Schottky-type contact leads to a barrier height at metal/p-GaN junction and makes the p-GaN layer to become floating, which can lock the injected carriers. Worse more, there is a high electric field at the gate contact, which leads to the trapping of injected electrons. Once the stress is removed, more positive gate voltage is needed during the turn-on process to suppress the influences of unreleased electrons; as the results, the electrical parameters shift. Finally, the mix-mode simulation results prove the carrier injection, and the measured segmental shifts of gate leakage current prove the trapping process in p-GaN layer successfully.

The unexpected resistance reduction effect of double-trench SiC MOSFETs under repetitive avalanche stress is investigated in this work. After enduring repetitive avalanche stress, the ON-state drain-source resistance (Rdson) of the device decreases. With the help of TCAD simulations, the dominant mechanism is proved to be the injection of positive charges into the gate trench bottom oxide, which is almost irreversible under zero-voltage bias condition at room temperature. For the injected positive charges attract extra electrons just beneath the gate trench bottom, where the carriers pass through under ON state, the resistivity there is reduced, improving the conduction capability of the device. Moreover, an optimization method is proposed. Since the impact ionization rate (I.I.) and the vertical oxide electric field (E⊥) along the gate trench bottom oxide interface contribute to the injection of positive charges, it is recommended to make the bottom oxide thicker to suppress this effect.

An anomalous breakdown voltage (BV) walk-in phenomenon of the trench-gate p-type vertical double-diffused metal–oxide–semiconductor (VDMOS) after single avalanche stress has been experimentally investigated. It is found that the BV of the VDMOS is decreased after the single avalanche stress, while other electrical parameters remain unchanged. T-CAD simulations and emission microscope (EMMI) analysis have been carried out. As a result, the shift of the breakdown point of the VDMOS, which results in the hot hole injection and trapping at the termination region, should be responsible for the BV degradation. A novel device structure with different trench depths in the termination region for the trench-gate p-type VDMOS is proposed to suppress the BV walk-in phenomenon.

The step-control infrared thermography method was proposed to investigate comprehensive single-pulse avalanche failure details of Si-superjunction (SJ) mosfet and SiC- mosfet . By this method, the damage location and even its shift in real time during the whole avalanche process can be observed. It is shown that, for the Si-SJ- mosfet , the avalanche damage location is extended from the cell region toward termination region with the increased avalanche time. The parasitic bipolar junction transistors at the cell corner near the termination are triggered due to the increased p-base resistances under relatively high temperature. However, for SiC- mosfet , the avalanche location is always kept within the cell region mainly due to insensitive breakdown voltage dependence on temperature. As a result, its failure site is found to locate at the source pad near the wire bond, likely due to the lattice temperature beyond the melting limit of aluminum contacts. Finally, the schemes to improve avalanche robustness, including the two different N -Epitaxy layers for Si-SJ- mosfet and the double source wire bonds for SiC- mosfet , have been proposed and verified basing on different failure mechanisms.

The super junction has been the most important concept for the design of power devices. However, there are still two problems when the conventional super-junction techniques are applied on lateral power devices: a large portion of the drift region is occupied by a p-type region, and the super junction techniques are not suitable for the gallium nitride-based high electron mobility transistor (GaN-HEMT). To solve the problems, a super field plate (SuFP) technique is proposed as a charge balance principle. Our analyses proved that the SuFP can provide a charge balance effect for a lateral double diffused MOS (LDMOS) without occupying the drift region. As a result, the LDMOS with SuFP has a better performance than the LDMOS with other charge balance realization techniques. Moreover, as a kind of field plate, the SuFP is also suitable for GaN-HEMT. Thereby, the proposed SuFP technique overcomes the two problems in conventional super-junction techniques and is significant for lateral power devices.

High-temperature electrical performances of enhancement-mode (E-mode) high electron mobility transistor with p-type Gallium Nitride (GaN) gate cap are evaluated here. The physics-based mechanisms behind the behaviours are also analysed by the simulations and analytical models. For static electrical performances, the changes of GaN bandgap and the interface states or traps are considered to be influential factors for the little variations of threshold voltage ( V T ). Meanwhile, the on-state resistance increases and trans-conductance decreases at high temperatures due to the reduction in electron mobility ( μ eff ). As for blocking characteristic, high temperature-induced increase of leakage current may result from multi-reasons, such as the increase of intrinsic carrier concentration and lowering of trap barrier. In addition, a segmental method is presented to understand the gate leakage current at high temperatures. For capacitance characteristics, the increase of channel resistance makes the measured gate capacitance lower than the intrinsic value. For dynamic electrical performances, the high temperature-induced decrease of μ eff leads to the increase of plateau voltage, bringing the decreases of total switching time and total switching energy loss, which are quite different from those of the devices with traditional metal-oxide-semiconductor structures.

Rational and purposeful designs of amorphous materials with desirable structures are difficult to implement due to the complex and unordered nature of such materials. In this work, a modelling algorithm was proposed for amorphous covalent triazine-based polymers to construct atomistic representative models that can reproduce the experimentally measured properties of experimental samples. The constructed models were examined through comparisons of simulated and experimental properties, such as surface area, pore volume, and structure factor, and further validated by the good consistency observed among these properties. To assess the predictive capability of the modelling algorithm, we used a new covalent triazine-based polymer and predicted its porosity by constructing a simulated model. The predicted results on the surface area and pore volume of the simulated model were quantitatively consistent with the experimental data derived from the experimentally synthesized sample. This consistency reveals the predictive capacity of the proposed modelling algorithm. The algorithm could be a promising approach to predict and develop advanced covalent triazine-based polymers for multiple applications.

Compared with the full shallow trench isolation (full-STI) lateral double-diffused MOS (LDMOS), the split-STI LDMOS has been demonstrated as a superior device with better breakdown voltage (BVOFF and specific on-resistance ( ${R}_{ {\scriptstyle\mathrm{ON}},\text {sp}})$ by virtue of its low resistance current path and dielectric reduced surface field effect. The layout of STI may not only be restricted in one pattern. Instead, it can have a variety of changes based on the split-STI structure. Actually, improvement of ${R}_{ {\scriptstyle\mathrm{ON}},\text {sp}}$ can be achieved upon modifying the STI layout pattern. In this way, four STI layout patterns, named split-STI, stair-STI, slope-STI, and H-shape-STI, are proposed. However, there is lack of information about the impacts of STI layout patterns on the reliability features of LDMOS. Therefore, in this article, the reliability features of the LDMOS with different STI layout patterns are investigated in detail, including electrical safe operating area (e-SOA), electro-static discharge (ESD) robustness, and hot carrier injection (HCI) degradation. Combining the experiment and technology computer-aided design (TCAD) simulation, the root causes of different reliability features are analyzed and discussed. Comparing them each, the LDMOS with H-shape-STI is recommended because of its better reliability features.

The structures of amorphous materials are generally difficult to characterize and comprehend due to their unordered nature and indirect measurement techniques. However, molecular simulation has been considered as an alternative method that can provide molecular-level information supplementary to experimental techniques. In this work, a new approach for modelling the atomistic structures of amorphous covalent triazine-based polymers is proposed and employed on two experimentally synthesized covalent triazine-based polymers. To examine the proposed modelling approach, the properties of the established models, such as surface areas, pore volumes, structure factors and N2 adsorption isotherms, were calculated and compared with the experimental data. Excellent consistencies were observed between the simulated models and experimental samples, consequently validating the proposed models and the modelling approach. Moreover, the proposed modelling approach can be applied to new covalent triazine-based polymers for predictive purposes and to provide design strategies for future synthesis works.

The creation of new fluorescent cores plays an important role in developing high-performance blue organic light-emitting diode (OLED) materials. In this study, a series of novel bis(benzothiophene-S,S-dioxide) fused blue emitting molecules (FBTO-EHNa, FBTO-EHSF and FBTO-EHFF), which are symmetrically functionalized by naphthalene, spirobifluorene, and 9,9,9′,9′-tetraoctyl-9H,9′H-2,2′-difluoren, respectively, are designed and synthesized successfully. They possess high thermal stability, resulting from the largely fused polycyclic aromatic conformation and polar sulfonyl groups in the FBTO unit. Through incorporating the various electron-donating units, the π-conjugation length is effectively controlled, which exhibits a profound influence on the thermal, photophysical and electrochemical properties. Then, these three small molecules are characterized for solution-processible and non-doped OLEDs, in detail. All of them show typical blue emission from 456 to 470 nm in the electroluminescent devices. In particular, FBTO-EHFF outperforms both FBTO-EHNa and FBTO-EHSF by displaying a maximum current efficiency (CE) of 6.37 cd A−1 with a CIE coordinates of (0.20, 0.24). These results suggest that the rationally designed the bis(benzothiophene-S,S-dioxide) fused polycyclic molecules have great potential capability for achieving solution-processible, high-performance and stable blue OLEDs.

Spot size converter (SSC) plays a role of paramount importance in the silicon photonics integrated circuit. In this article, we report the design of a reconfigurable spot size converter used in the hybrid integration of a DFB laser diode with a silicon photonic waveguide. Our SSC consists of subwavelength gratings and thermal phase shifters. Four subwavelength grating tips are used to improve horizontal misalignment tolerance. Meanwhile, the phase mismatch between two input waveguides is compensated by phase shifters to minimize insertion losses. Our simulated result has yielded a minimum insertion loss of 0.63 dB and an improvement of the horizontal misalignment from ±0.65 µm to ±1.69 µm for 1 dB excess insertion loss at the wavelength of 1310 nm. The phase shifters are designed to compensate any phase error in both the fabrication and bonding processes, which provides a completely new edge-coupling strategy for the silicon photonics integrated circuit.

This brief proposes novel integrated GaN high-electron-mobility transistor (HEMT) with multichannel Schottky barrier diode (SBD) structures to achieve ultrahigh reverse conduction capability and maintain the blocking characteristic at the same time. The simulative results indicate that the reverse voltage drop and reverse ON-state resistance can be reduced by 38.6% and 38% compared with the traditional metal–insulator–semiconductor HEMT, respectively. Meanwhile, the forward conduction capability, the blocking performances, and the capacitance characteristics are little influenced. Moreover, it is proved that the proposed devices also exhibit superior dynamic performances, indicating the application potential of reducing the power loss of power electronic systems. Finally, the key fabrication flows for the novel devices are presented and discussed.

Lithium-sulfur (Li-S) batteries have attracted a great deal of attention for the next-generation energy storage devices due to their inherently high theoretical energy density, high natural abundance, and low cost. However, the dissolution of polysulfides in electrolytes and their undesirable shuttle behavior lead to poor cycling performance, which obstructs practical application. Herein, we report a dual-sulfur-fixing mechanism of epoxy/allyl compound/sulfur system to prepare poly(sulfur-random-4-vinyl-1,2-epoxycyclohexane) (SVE) copolymers as powerful cathode materials. Benefiting from the stable C-S bond and a uniform distribution of ultrafine Li2S/S8 in the SVE-based polymer matrix, the SVE electrodes exerted an embedding effect to reduce polysulfides migration. The thiosulfate/polythionate protective layer derived from the terminal hydroxyl group of SVE also ensured the cycle stability of SVE electrodes during cycling. As a result, optimized SVE electrodes deliver a high reversible specific capacity of 1248 mA h g-1 at rates of 0.1 C, together with a stable cycling performance of no capacity decay per cycle over more than 400 cycles. This work provides an effective strategy for the practical application of organosulfur polymers Li-S batteries and inspires the exploration of the reaction mechanism of epoxy/allyl compound/sulfur system.

This paper reports a new readout integrated circuit designed for hybridization with P-on-N detector such as InSb, HgCdTe and InGaAs, and it can support a wide range of system through flexibility and versatile functions. This ROIC is fabricated using CSMC 0.18um double poly, six metal process that utilized high-speed CMOS transistors. The device can work at temperatures of 80K with 5.5V supply voltage. It still has a build-in temperature sensor to detect the temperature of the chip. The pixel cell occupies an area of 25×25µm2 with an input charge-handling of 18Me- carriers. After testing at 80K, the output swing was larger than 3V; the power consumption of chip was about 180mW; the output noise was about 400uV and its dynamic range was about 78dB.

In this paper, we have comprehensively stud-ied the performance boosts of 4H-SiC VDMOS under the mechanical strain. The electrical properties of 4H-SiC VDMOS under the biaxial and uniaxial tensile and compressive strains along the channel direction are examined thoroughly. We find that the biaxial and uniaxial compressive strain benefit the VDMOS, and the biaxial and uniaxial tensile strain loss the VDMOS. Because the mechanical strain affects carriers’ transportation in 4H-SiC’s inverted channel distinctly, the strain effects are strongly correlated with the gate voltage. It shows that the mechanical strain can enhance the drain current to a greater degree at lower gate voltage, and it also shows that both biaxial and uniaxial strain can cause threshold voltage’s shift.

In this paper, the degradation phenomena and mechanism of the asymmetric trench Silicon carbide (SiC) power metal-oxide semiconductor field-effect transistor (MOSFET) under repetitive unclamped inductive switching (UIS) stress are investigated in details. The trench corner is verified to be the mainly degraded region by Silvaco TCAD simulations and experimental measurements. It is demonstrated that the dominant degradation mechanism is the injection of hot holes into the gate oxide at the trench corner. After enduring 300k UIS stress cycles, the threshold voltage (V th ) decreases by nearly 1V while the gate-drain capacitance (C gd ) increases seriously by 46.2%, leading to the degradations in switching properties. Furthermore, the R on is decreased by 7.2%.

In this work, four LDMOS devices with different split-STI structures (Device A: Ldmos with traditional split-STI, Device B: Ldmos with slope-STI, Device C with step-STI and Device D with H-shape-STI) have been fabricated and investigated. Because they own consistent breakdown voltage $(\text{BV}_{\mathrm{off}})$ , the hot-carrier stresses including the maximum substrate current $(\mathrm{I}_{\text{submax}})$ stress and the maximum gate voltage $(\mathrm{V}_{\text{gmax}})$ stress are carried out successfully. It is found that they exhibit different hot-carrier reliabilities due to the different STI structures. With the assistance of the T-CAD simulation tools, the inner mechanisms of these phenomena are discovered in detail.

In this paper, the reliability of quasi-vertical GaN Schottky barrier diodes under high temperature reverse bias (HTRB) stress has been investigated. The test results indicate that the stress applied on the devices makes reverse leakage current decrease, but the forward performance, capacitance and reverse recovery performance show negligible changes. With the help of experiments and T-CAD simulations, it is demonstrated that there is trapping process of hot electrons along vertical sidewall of the device under high reverse voltage stress, which leads to the decrease of reverse leakage current. An empirical model can be used to predict the variations and good coincidences can be observed based on the acquired experiment data. Moreover, long time over voltage stress on the device leads to the direct failure. By using the infrared thermography analysis and T-CAD simulations, the failure mechanism has been also illustrated.

As a kind of green, environment-friendly and sustainable carbon material, biomass carbon has simple processing technology and undoubtedly been the best candidate for industrialization. Different activation processes can be used to change the internal microstructure of carbons, and design pores that facilitate ions transport and electrons conduction, thereby achieving the ultimate goal of improving electrochemical performance. Herein, we select the same activator (KOH) and activation time (3 h) but change the activation temperature (300 °C, 600 °C, 800 °C) to obtain biomass-derived carbon with the different micromorphology, pores structure and heteroatoms content. Rather, We choose ether-based electrolyte, due to its highly reversible graphite co-intercalation reaction, the problem of extremely low electrochemical activity of graphite in ester electrolytes is avoided. Results indicate, the sample PCS-600 exhibites sheet structure with specific surface area of 38.3 m2/g and large average pore width of 2.77 nm, which providing sufficient conditions for ions transport. PCS-600 has 1.05 at% N and 5.75 at% O heteroatoms, which providing additional pseudocapacitance. In addition, the electrochemical performance of PCS-600 is optimal, at a current density of 0.1 A/g, its specific capacity is 198.6 mA h/g, maintain at ~95% after 100 cycles, with coulomb efficiency ~100%.

In this letter, we present an experimental investigation on electrical properties of lateral IGBTs (LIGBTs) under an uniaxial mechanical strain for the first time. Both ON-state and turn-off characteristics of LIGBT under an uniaxial strain are studied extensively. The uniaxial strain is applied both parallel and perpendicular to the channel direction. The uniaxial tensile strain will increase the collector current ( ${I} _{C}$ ) and the uniaxial compressive strain will decrease the ${I} _{C}$ , while the breakdown voltage ( ${V} _{\textit {BD}}$ ) is not affected. The parallel strain and perpendicular strain affect the ${I} _{C}$ distinctly in both the linear and saturation regions. The piezoresistance coefficient of LIGBT under the parallel strain is more than three times that of nMOSFET in the linear region. The parallel tensile strain declines the ON-state voltage drop ( ${V} _{ \mathrm{\scriptscriptstyle ON}}$ ) and increases the turn-off time ( ${t} _{ \mathrm{\scriptscriptstyle OFF}}$ ) and turn-off loss ( ${E} _{ \mathrm{\scriptscriptstyle OFF}}$ ). While the perpendicular tensile strain decreases the ${V} _{ \mathrm{\scriptscriptstyle ON}}$ , ${t} _{ \mathrm{\scriptscriptstyle OFF}}$ , and ${E} _{ \mathrm{\scriptscriptstyle OFF}}$ simultaneously, which is extremely beneficial for real applications. The mechanisms of these strain effects are studied.

As a kind of Ni-rich cathode material, LiNi0.8Co0.15Al0.05O2 undergoes severe phase transition when cycling under a high cutoff voltage, causing a sharp decline in reversible capacity. In this stud...

In this work, degradations of dynamic characteristics for silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors under repetitive avalanche shocks are investigated in details. With the help of Silvaco TCAD simulations, gate capacitance versus gate voltage ( Cg – Vg ) measurement, and three-terminal charge pumping test, the main damaged position is demonstrated to be the SiC/SiO2 interface along junction FET (JFET) region instead of the body diode where most of the avalanche current passes through. Dominant avalanche degradation mechanism is then confirmed to be the injection of holes into the gate oxide above the JFET region. Since the channel region and the main junction of body diode are not seriously damaged by the avalanche stress, static parameters all remain stable. Meanwhile, due to the injection of holes, the depletion layer beneath the JFET region gets thinner, resulting in the increase of gate-drain capacitance ( C gd) under low drain-source voltage ( V ds) bias condition. It further takes responsibilities for the increments in input capacitance ( Ciss ), output capacitance ( Coss ), and reverse transfer capacitance ( Crss ). Moreover, it results in the extension of Miller plateau. Therefore, the increase of gate charge and delay of turn- off time after being stressed by repetitive avalanche shocks are monitored. Moreover, turn- on and turn- off dissipated energies after different unclamped-inductive-switching stress cycles are extracted. They are rarely influenced by the stress for the overlapping areas of voltage and current during switching procedures are relatively stable.

In this paper, we have comprehensively studied the performance boosts of both nLDMOS and pLDMOS under the mechanical strain. The electrical properties of LDMOS under the uniaxial tensile and compressive strains along the channel direction are examined thoroughly. We find that the uniaxial tensile strain benefits the nLDMOS, and the uniaxial compressive strain benefits the pLDMOS. Because the mechanical strain affects carriers’ transportation in bulk Si and inverted channel distinctly, the strain effects are strongly correlated with the gate voltage, drain voltage, and devices’ dimensions. It is found that the LDMOS with the longer gate length is more preferred for the strain. The piezoresistance coefficients of both nLDMOS and pLDMOS under the uniaxial strain are evaluated for the first time. It is also shown that the mechanical strain can enhance the drain current without the degradation of the breakdown voltage, which suggests a downshift of the ON-resistance versus breakdown voltage curve.

The degradations of electrical parameters for double-trench silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs) under repetitive avalanche stress are investigated in this paper. The injection of hot holes into the bottom oxide of the gate trench during avalanche process is demonstrated to be the dominant degradation mechanism, while the channel is rarely influenced by the stress. The injected holes attract extra electrons in the SiC layer along the SiC/SiO2 interface, decreasing the ON-state drain–source resistance ( ${R}_{{dson}}$ ). Due to this reason, the threshold voltage ( ${V}_{{th}}$ ) of the device also reduces slightly. Moreover, other than static electrical parameters, dynamic characteristics including the gate–drain capacitance ( ${C}_{{gd}}$ ) and the switching characteristics of the device also degrade. After being stressed by repetitive avalanche stress, the depletion region beneath the bottom of the gate trench gets thinner, leading to the increase in ${C}_{{gd}}$ , which further influences the switching behaviors. The turn- ON and turn- OFF switching times of the device are calculated. It illustrates that the repetitive avalanche stress results in an obvious delay in the turn- OFF procedure, but hardly influences the turn- ON behaviors of the double-trench SiC MOSFET.

Ni-rich layered oxides are regarded as next-generation cathode materials for lithium-ion batteries with high energy density. However, these materials suffer capacity degradation and power fade at high cutoff voltages. Herein, a robust La, Zr nanocomposite oxide coating layer is successfully deposited on the LiNi0.6Co0.2Mn0.2O2 surface using a wet-chemical method. The surface modified LiNi0.6Co0.2Mn0.2O2 exhibits improved rate capability and superior cycling performance even at a high cutoff voltage of 4.5 V. Ex situ analyses uncover the capacity fading mechanisms of LiNi0.6Co0.2Mn0.2O2 and the effects of the coating layer by a combination of X-ray diffraction, high-resolution transmission electron microscopy, and X-ray photoelectron spectroscopy. The results show that particle cracking, structural transformation, and interfacial side reactions are responsible for the inferior performance of pristine LiNi0.6Co0.2Mn0.2O2. Nevertheless, the coating layer not only retains structural integrity and suppresses irreversible surface phase transformation, but also alleviates accumulation of highly resistive species on the cathode surface. This investigation highlights the advantages of combining multiple techniques in investigating the effects of surface modification and could be extended to explore other coating materials.

The electrical parameters degradations of a radio frequency lateral-diffused metal–oxide–semiconductor transistor under switch-OFF avalanche breakdown stress have been first experimentally investigated. A modified three-port dc-IV method is proposed to demonstrate the degradation mechanisms. It shows that the interface states generation under the edge of the polygate at the n-drift region brings the increase in ON-resistance due to the decrease in carrier mobility, while the hot-holes injection and trapping there leads to the increase in gate–drain capacitance due to the widening restriction of the depletion layer in the n-drift region. Furthermore, the output power and the power gain are also decreased under the avalanche shocks. However, other electrical parameters, such as threshold voltage, gate–source capacitance, and drain–source capacitance, can be kept unchanged.

In this letter, a novel Superjunction Metal-Oxide -Semiconductor Field Effect Transistor with wave-type field limiting ring (WFLR-SJ-MOSFET) is proposed to improve the di/dt robustness of body diode reverse recovery. When SJ-MOSFET body diode goes through reverse recovery, the WFLR can suppress and rebuild the peak electric field which is resulted from the large current flowing through the sensitive terminal boundary region. As a consequence, the ruggedness of dynamic avalanche during reverse recovery is optimized. Finally, the di/dt robustness of WFLR-SJ-MOSFET body diode reverse recovery is improved by 3.2 times from 72 A/μs to 320 A/μs comparing with the conventional SJ-MOSFET.

Multimodal imaging combining various imaging approaches can provide complementary information about tissue in a single imaging session. Here, we introduce a multimodal approach combining three-photon microscopy (3PM) and spectral-domain optical coherence microscopy (SD-OCM) for the first time. We demonstrate the use of an optical parametric chirped-pulse amplification (OPCPA) laser source, commonly used for three-photon fluorescence excitation and thirdharmonic generation (THG), for simultaneous OCM and three-photon (3P) imaging. We validated the system in deep mouse brain in vivo with neuronal imaging. We visualized small structures such as myelinated axons, neurons, and large fiber tracts in white matter with high spatial resolution in a fast and non-invasive manner using linear and nonlinear contrast in the deep mouse brain (>1 mm) with an OPCPA source operating at 1620 nm central wavelength. Our method demonstrates the potential of the system for simultaneous OCM and 3PM with the same laser source.

Doping porous carbon materials with heteroatoms is an effective approach to enhance the performance in the areas of supercapacitors and the oxygen reduction reaction (ORR). However, most traditional heteroatom-doped metal-free porous carbon materials have random structures and pore distributions with high uncertainty, which is harmful for a deep understanding of supercapacitors and the ORR mechanism. Basing on the molecular design, a series of N, O co-doped porous carbon frameworks (p-PYPZs) has been prepared through the template-free trimerization of cyano groups from our designed and synthesized 2,8-bis(4-isocyanophenyl)-2,3,7,8-tetrahydropyridazino[4,5-g]phthalazine-1,4,6,9-tetraone (PYPZ) monomer and subsequent ionothermal synthesis, which has the advantage that the type, position, content of the heteroatom and the pore structure in the porous carbon material can be regulated. Nitrogen and oxygen atoms introduced via covalent bond and the hierarchically porous structure endow the material with excellent cycling stability, and 110% capacitance retention after 35 000 cycles in 1 M H2SO4. A symmetric supercapacitor was assembled with the material and shows an energy density of 32 W h kg−1. The material can be applied to the area of oxygen reduction reaction as a metal-free catalyst with an onset potential of 0.85 V versus RHE, indicating the good catalytic ability. The material exhibits excellent methanol crossover resistance and a four-electron pathway mechanism. Results also indicate a positive correlation between the N-Q content and the selectivity of the four-electron pathway. In this paper, the electrochemical properties of materials are regulated at the molecular level, which provides a new idea for further understanding the electrochemical mechanism of energy storage devices.