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1,364 results on '"Through-silicon via"'

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1. TSV Based Orthogonal Coils With High Misalignment Tolerance for Inductive Power Transfer in Biomedical Implants

2. The Effect of Pitch Distance on the Statistics and Morphology of Through-Silicon Via Extrusion

3. Structural Integrity of 3-D Metal–Insulator–Metal Capacitor Embedded in Fully Filled Cu Through-Silicon via

4. Cu Protrusion of Different through-Silicon via Shapes under Annealing Process

5. Reliability Simulation and Life Prediction of TSV Under a Thermoelectric Coupling Field in a 3D Integrated Circuit

6. FE Simulation Model for Warpage Evaluation of Glass Interposer Substrate Packages

7. Simplistic approach to reduce thermal issues in 3D IC integration technology

8. Through-Silicon-Via Interposers with Cu-Level Electrical Conductivity and Si-Level Thermal Expansion Based on Carbon Nanotube-Cu Composites for Microelectronic Packaging Applications

9. On the applicability of two‐bit carbon nanotube through‐silicon via for power distribution networks in 3‐D integrated circuits

10. A Novel Silicon-Air-Silicon Through-Silicon-Via Structure Realized Using Double-Side Partially Overlapping Etching

11. <scp>On‐wafer</scp> thermomechanical characterization of a thin film polyimide formed by vapor deposition polymerization for <scp>through‐silicon</scp> via applications: Comparison to <scp>plasma‐enhanced</scp> chemical vapor deposition <scp> SiO 2 </scp>

12. Design, Fabrication, and Comparison of 3D Multimode Optical Interconnects on Silicon Interposer

13. Electroless nickel underlayer deposited between copper filler and silicon substrate: effect of bath pH

14. Facile approach to mitigate thermal issues in 3D IC integration using effective FIN orientation

15. Noise performance improvement in 3D IC integration utilizing different dielectric materials

16. Thermal model for 3-D integrated circuits with integrated MLGNR-based through silicon via

17. Modeling Copper Plastic Deformation and Liner Viscoelastic Flow Effects on Performance and Reliability in Through Silicon Via (TSV) Fabrication Processes

18. Surface Stress Evolution in Through Silicon Via Wafer During a Backside Thinning Process

19. Fully Symmetric 3-D Transformers With Through-Silicon via IPD Technology for RF Applications

20. Optimization of TSV Leakage in Via-Middle TSV Process for Wafer-Level Packaging

21. The effect of silicon anisotropy on the thermal stress of TSV structure of 3D packaging chip under thermal cyclic loads

22. Research on Effect of Annealing on Copper Deposited by Electroplating in High Density TSV

23. The effect of annealing time on the mechanical properties of TSV-Cu

25. Design and Implementation of RF Front-End Module Based on 3D Heterogenous-Integrated Wafer-Level Packaging

26. Three-Dimensional Inkjet-Printed Metal Nanoparticles: Ink and Application Development

27. Assessment of through‐silicon‐vias with different configurations of ground vias and accounting for substrate losses

28. Electrical Characteristics and Reliability of Wafer-on-Wafer (WOW) Bumpless Through Silicon Via

29. Pre-bond Qualification of Through-Silicon Via for the Application of 3-D Chip Stacking

30. S-Connect Fan-out Interposer For Next Gen Heterogeneous Integration

31. Ultrawideband Signal Transition Using Quasi-Coaxial Through-Silicon-Via (TSV) for mm-Wave IC Packaging

32. Flip-Chip Flux Evolution

33. Design Rules for TSV Membranes

34. Analysis of Transmission Characteristics of Copper/Carbon Nanotube Composite Through‐Silicon Via Interconnects

35. Through-Silicon Via-Based Capacitor and Its Application in LDO Regulator Design

36. Stress investigation of annular-trench-isolated TSV by polarized Raman spectroscopy measurement and finite element simulation

37. A New Prewetting Process of Through Silicon Vias (TSV) Electroplating for 3D Integration

38. The Effect of Double-Layer Nonconductive Films on the Solder Sidewall Wetting and the Reliability of 40-$\mu$ m Cu-Pillar/SnAg Microbumps for Chip-on-Chip Interconnection

39. Copper-silicon carbide composite plating for inhibiting the extrusion of through silicon via (TSV)

40. Wideband Electromagnetic Distribution Characterization and Dielectric Analysis of Shielded-Pair Through-Silicon Via Using Recursive Approximation Algorithm

41. Modeling simplification for thermal mechanical stress analysis of TSV interposer stack

42. Extracting Radio Frequency Properties of a Typical Through-Silicon Via Structure With a Self-Developed Deembedding Technique

43. Study on copper protrusion of through-silicon via in a 3-D integrated circuit

44. The effective control of Cu through-silicon via extrusion for three-dimensional integrated circuits by a metallic cap layer

45. Effect of silicon anisotropy on interfacial fracture for three dimensional through-silicon-via (TSV) under thermal loading

46. Nonlinear Electrothermal Model for Investigating Transient Temperature Responses of a Through-Silicon Via Array Applied With Gaussian Pulses in 3-D IC

47. Working mechanism of iodide ions and its application to Cu microstructure control in through silicon via filling

48. Improved transmission line model for high-frequency modelling of through silicon vias

49. Sulfur-Containing Additives for Mitigating Cu Protrusion in Through Silicon via (TSV)

50. Processing-Structure-Protrusion Relationship of 3-D Cu TSVs: Control at the Atomic Scale

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