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To improve the misalignment tolerance for inductive power transfer (IPT) systems in implantable medical devices, like retinal prosthesis, a 3-D through silicon via (TSV) based orthogonal receiving coil is proposed in this brief. The mutual inductance between the receiving coil and the transmitting coil is calculated, analyzed, and compared. Results obtained from the analytical model and finite element method show the proposed coil structure significantly enhances the inductive coupling between coils under misalignment. Furthermore, we present receiving circuits with current summing techniques to enhance the energy transfer between the receiving coil to the load. The prototype of the inductive power transfer system is developed and the experimental results demonstrate that the proposed coil structure can provide a good misalignment tolerance. A maximum variation of the power transfer efficiency (PTE) is only 18.0% under angular misalignment of 90° and 23.4% under lateral misalignment of 37.5% of the transmitting coil’s diameter, which indicates the proposed coil structure can meet the demand of IPT systems in retinal prosthesis applications.

In this work, we investigated the effect of pitch distance on the statistical variation and morphology of extrusion in Cu through-silicon vias (TSVs) and the underlying mechanisms. Extrusion statistics were obtained from TSV samples with two different pitch distances. A notable increase in the magnitude of extrusion was observed in vias with smaller pitch, yet the extrusion spread was largely unaffected. The morphologies of the extruded vias were characterized and categorized, and a finiteelement analysis was carried out to study the effect of pitch distance on stress and deformation. The results suggested that the overlapping of stress fields from neighboring vias resulted in larger stress in the small-pitch vias, which subsequently led to higher extrusion. The morphologies observed in the extruded vias were related to the operation of different deformation mechanisms under the combined effect of stress and microstructure. The statistical spread of via extrusion, which was similar in both groups of vias, was related to the stochastic nature of the via microstructure. By using a thin cap layer of Ta to suppress the vacancy sources at the via top surface, the adverse effect of the pitch distance was minimized and a pronounced reduction of extrusion was achieved in vias of both pitch distances.

A novel way to implement integrated metal–insulator–metal (MIM) capacitor with ultrahigh capacitance density of up to 5.621.8 nF/mm2 has been proposed earlier. This technology embeds 3-D MIM capacitor into the existing trench of through-silicon via (TSV) prior to Cu filling to achieve >90% planar surface area reduction. However, the previous study was on the early-stage test vehicles without Cu filling. In this work, complete test vehicles with fully filled Cu TSVs have been successfully fabricated whose trench diameters are 0 (D00), 10 (D10), 20 (D20), and 30 $\mu \text{m}$ (D30), respectively. First, the design layout and the process flow are disclosed in detail. Then under scanning electron microscope (SEM) and transmission electron microscope (TEM), it is found that the peak of the Si scallop on the sidewall is deformed for the D30 test vehicle. For the first time, the damage is found in Si substrate, instead of TSV SiO2 liner, due to the thermomechanical stress between the TSV Cu core and the surrounding structures. In addition, the Al2O3 dielectric layer is also impaired at the damaged Si peaks. Finally, the leakage current density is measured and normalized at a bias of 1.5 V: $4 \times 10^{-9}$ A/cm2 for D00, $4.1\times 10^{-8}$ A/cm2 for D10, 1.1 $\times 10^{-6}$ A/cm2 for D20, and $7.4\times 10^{-1}$ A/cm2 for D30, respectively. Therefore, the structural integrity of the D10 and D20 test vehicles with fully filled Cu TSVs is preserved, but the D30 test vehicle is not intact due to higher stress. The capacitance density of 6.547.1 and 7.091.7 nF/mm2 is recorded for the D10 and D20 test vehicles, respectively.

The through-silicon via (TSV) 3D integration method has become one of the most widely used techniques for achieving system-level integration for applications that require smaller package sizes, higher interconnection density and high performance. This is because the TSV fabrication technology provides the mechanism for facilitating communications between various layers of the 3D integration system and for interconnecting stacked devices at wafer-level. Although there are several reported studies on TSV 3D integration R&D, with most of these studies focused on the improvement of TSV fabrication process, there are very limited in-depth studies associated with the TSV reliability issues and challenges. In this paper, we investigate the effect of TSV geometries on the associated TSV reliability factors. Different TSV geometries including I-type, tapered, elliptical, triangular, quadrangular and circular shapes (with same volume) are investigated to find the most reliable structure under annealing process. The results show that the tapered TSV shape releases thermo-mechanical stress more uniformly than other shapes and larger top surface shows better reliability.

The reliability of through silicon via (TSV) in a 3-dimensional integrated circuit (3D IC) determines whether the electronic system can operate continuously and steadily. The finite element method was adopted to study the response of TSV to thermoelectric coupling, the effect of different dielectric layer materials and the filling degree of carbon nanotubes (CNT) on TSV reliability were investigated, respectively. Through orthogonal simulation experiments, the high reliability of a type of TSV with benzocyclobutene (BCB) dielectric layer and filling by a coaxial hybrid CNT bundle was verified, and its lifetime was predicted by the failure of the physical model. The simulation results show that the most important influence factor to TSV reliability is the depth-to-width ratio, the second important factor is the choice of dielectric material, and the least important factor is the filling degree of CNT. The parameter values with the optimum reliability are as follows: the depth-to-width ratio of copper column is 20, the dielectric material is BCB, and the CNT filling degree is 4–8%.

Glass interposer substrates have attracted growing interest as an alternative to traditional organic and silicon-based interposers for 3-D integrated circuit (IC) and 2.5-D through silicon via (TSV) packages in recent years. However, while glass substrates have the advantages of excellent electrical isolation, superior RF performance, good coefficient of thermal expansion (CTE) adjustability, and the potential for large-scale fabrication, they are inherently brittle. Consequently, an appropriate choice of glass and epoxy molding compound (EMC) material is essential for minimizing the warpage of the molded wafer. To facilitate the package design process, this study, therefore, develops an ANSYS simulation model to predict the warpage of the molded glass wafer given the use of different glass and EMC materials. The validity of the simulation model is confirmed by comparing the numerical results for the warpage of an 8-in molded glass wafer with the experimental measurements obtained using an Advanced Metrology Analysis (aMA) system. Single-factor-analysis experiments are then conducted to examine the effects of five different control factors, namely, the glass substrate thickness, the glass CTE, the glass modulus, the EMC CTE, and the EMC modulus, on the warpage performance of the molded glass wafer. The simulation results provide useful guidelines for the design of robust glass substrate packages.

A practical exhibition of the consequences of the 3D IC in heat management by adding the fin and heat spreaders to thermal through silicon via (TTSV) and IC respectively is proposed in this paper. Thermal cooling and its distribution of burnt potentials at various conditions are the different possessions which can be simulated using FEM simulator. This paper illustrate materials like Silicon nitride (Si3N4), Aluminium oxide (Al2O3), Silicon dioxide (SiO2) as they have the high thermal conductivity and high temperature capabilities which leads to the thermal management in the 3D IC design. Currently, semiconductor industries has cognizance of the metrics such as low density, high thermal strength, good facture of toughness, excellent wear resistance of Silicon nitride and it also shows better capabilities of high temperature, oxidation resistance and high retention strength compared to other metals. Besides silicon nitride has good resistance to thermal shock due to low coefficient of thermal expansion. Aluminium oxide is known for an better electrical insulator but has high thermal conductivity and which can be utilized as the substrate for integrated circuits. The high temperature furnace insulations and electrical insulations are designed by using the aluminium oxides as it has high boiling points and melting points. This makes the rapid use of alumina films in manufacture of IC industry. The other uses of alumina films include spark plug insulators, micro-electric substrates and insulating heat sinks. Silicon dioxide has the properties which helps to use them as the insulator material in IC technology as it has high thermal stability and making it useful for device integration and has high dielectric strength and thermal expansion coefficient is very low and in this paper we have taken these three materials and these materials have been implemented in our model and advertence the outcomes that which material is working efficiently and preciously.

Through-silicon-via (TSV) interposers using silicon and copper represent a critical element in microelectronic packaging, as they bridge between fine-pitch inputs/outputs at the integrated circuit ...

This study investigates the possibility of the carbon nanotube (CNT)‐based through‐silicon vias (TSVs) for improving power integrity of 3‐D integrated circuits (3‐D ICs). The circuit model is developed for 2‐bit CNT TSV and validated through the full‐wave electromagnetic simulator HFSS simulations. The 2‐bit CNT TSV is applied to power distribution networks (PDNs) by combining the validated equivalent‐circuit model and that TSV‐based PDN impedance is compared with the traditional one. By virtue of the large capacitance and low inductance of the 2‐bit CNT TSV, the PDN impedance of the 3‐D IC can be suppressed significantly and the anti‐resonant frequency can be increased.

This letter presents the design and fabrication of a through-silicon-via (TSV) structure using ultra-low-resistivity-silicon (ULRS) as the central conductor and air-gap as the insulation layer. Silicon-air-silicon (SAS) TSVs are successfully fabricated using a simple and low-cost fabrication process based on a novel double-side half-annular Si etching technique. A comparative study on different overlapping areas of the double-side Si etching is carried out to guarantee the proper formation of the air-gap insulation layer and to minimize the lateral undercutting effect occurred near the openings of the air-gaps. Thanks to the good isolation nature of the air and the successful formation of the air-gaps, we have achieved a capacitance density of 0.137 nF/cm2 and a leakage current density of 3.85 nA/cm2 for a single SAS TSV, indicating superior electrical properties in terms of ultra-low parasitic capacitance and excellent insulating performance, which shows an alluring prospect in future 3-D integration strategies and applications.

While conventional silicon photonic (SiP) waveguides achieve high data rates with low loss, they can only be placed on top of the chip surfaces horizontally. In this article, we present a design approach for multimode chip-to-chip interconnects with similar low-loss and high-bandwidth density properties as SiP waveguides. The state-of-the-art fabrication of optical through silicon via (OTSV) requires conventional back end of line (BEOL) processing with an additional step: metal coating lowers the loss of air-filled TSVs. Alternatively, the TSV is converted into a polymer waveguide by filling of low-loss polymer (Ormocore) to achieve

This research proposed intermediate materials between Cu filler and Si wafer to reduce the coefficient of thermal expansion (CTE) mismatch in the through silicon via (TSV) structure. The proposed m...

Thermal through silicon via (TTSV) and heat spreaders plays a vital role in heat management in 3-Dimentional IC integration. However in recent years FIN to TTSV and heat spreaders has proposed to detects and spread heat in any one direction which leads to the damage of an integration circuit (IC). This paper proposes a FIN with optimal directions and heat spreaders to spread the heat in various directions and finally the heat absorb towards heat sink effectively. In this work, we have also demonstrated various thermal cooling effects and its impact on the distribution of potential across IC at different conditions. We have studied these using FEM Simulator for (1) 3D IC architecture with FIN and heat spreaders using Graphene and CNT material, (2) TTSV with FIN and heat spreaders of Graphene, (3) TTSV with fin and heat spreaders of CNT, (4) TTSV with FIN direction towards heat source made of Graphene and CNT, and (5) TTSV with FIN direction towards TSV made of CNT and Graphene. Our result shows that CNT has better thermal cooling management towards heat source as well TSVs than Graphene with order greater than 100 Kelvin.

Semiconductor Industries are mainly facing problems by using planar integration (2D IC) in order to overcome the paradigm shift has been adopted as vertical IC integration so called 3D IC. It not only provides higher bandwidth, higher system performance, but also consumes less power with system scaling. 3D IC has an ability to coordinate IC chips by stacking them vertically and electrically associated utilizing TSV's (Through Silicon Via). By utilizing TSV's in 3D IC, TSV noise coupling is one of the vital factors for the system performance aspects. TSV's play major role in carrying the electrical signal between the IC’s of 3D integrated structures. Noise coupling is the major drawback between the signal carrying TSV’s (ETSV) and victim TSV’s. In this work, we have shown better electrical integrity by reducing the noise coupling from TSV to Silicon substrate by essentially changing the CMOS compatible dielectric materials as liner structures. In addition to this performance of various proposed structures are analyzed and verified under different parameters like electrical signal and at high frequencies. Also, the noise coupling analysis has been studied for Electrical TSV’s (ETSV), TTSV (Thermal Through Silicon Via) and heat source. Finally, our work shows liner material Teflon AF1600 shows comparably better noise coupling performance for all the proposed models even at higher frequencies like THz.

This paper applies the multi-layer graphene nanoribbon as a new prospective filler material for through silicon via to solve the complex heat problems in the 3-D integrated circuits. An equivalent thermal model for 3-D integrated circuits with the MLGNR-based through silicon via is presented in this work, which take lateral heat transfer of through silicon via into account. The experimental results show that the heat transfer performance of MLGNR-based through silicon via is better than the conventional Cu-based through silicon via. Furthermore, it is found that the temperature predicted by the proposed model are in good accordance with the ANSYS simulation, and the maximum relative deviation is less than 4.0%

Copper plastic deformation and liner viscoelastic flow effects on performance and reliability are studied for TSV-middle and backside TSV-last fabrication processes. Incremental plasticity model with nonlinear hardening and Maxwell viscoelasticity model are employed to characterize TSV copper and liner dielectrics material behaviors. The model parameters are chosen to match experimental data. It is found that both plastic deformation in copper and viscoelastic flow in dielectrics affect the trade-off between TSV keep-out-zone (KOZ) size and TSV extrusion. The backside TSV-last process generates less residual stresses and mobility changes in active silicon than the TSV-middle process, and avoids M1 metal resistance increase due to TSV extrusion at elevated process temperatures. The TSV plastic deformation and liner viscoelastic flow effects on residual stresses and reliability in M1 interconnects and dielectrics are also examined for two different M1 configurations.

During Through Silicon Via (TSV) wafer backside thinning process, excessive surface stress will cause undue warpage or fracture of wafer in subsequent de-bonding step, and further impair the precision of following wafer stacking and packaging. Therefore, it is considerable to investigate the evolution mechanism of wafer stress and how to control it in backside thinning process. Aiming at the above problem, a calculation method is proposed in this paper to characterize surface stress of TSV wafer in a bonding structure, and the method has been confirmed by micro-Raman spectroscopy; Then, based on the method, the change of stress in TSV wafer during a whole backside thinning process is described, and the formation and evolution mechanism of surface stress is analyzed; At last, the stress control performance and corresponding mechanism explanation under different process parameters are demonstrated, and the optimal process condition is selected, which can release more than 80 percent of generated stress. In summary, this work can be regarded as a reference in three-dimension integrated circuit (3D IC) industry to select proper thinning conditions in order to obtain an optimized stress relief performance.

This article presents the design, characterization, and modeling for the novel 3-D transformer structures based on the in-house developed 3-D integrated circuit (3-D IC) via-last backside-through-silicon via (TSV) interposer process. Differing from the conventional 2-D planar structure, the 3-D TSV design allows achieving a fully symmetric transformer with a compact size. The equivalent circuit model parameters are extracted based on the S-parameters to investigate the design tradeoff. With an inner diameter of $40~\mu \text{m}$ in the 3-D 1:1 transformer, the measured inductances of the primary and second coils are 439 and 482 pH with the $Q$ factors of 4.59 and 5.11, respectively, and the coupling coefficient is 0.136.

Through silicon via (TSV) offers a promising solution for the vertical connection of chip I/O, which enables smaller and thinner package sizes and cost-effective products by using wafer-level packaging instead of a chip-level process. However, TSV leakage has become a critical concern in the BEOL process. In this paper, a Cu-fulfilled via-middle TSV with 100 µm depth embedded in 0.18 µm CMOS process for sensor application is presented, focusing on the analysis and optimization of TSV leakage. By using etch process, substrate defect, and thermal processing co-optimization, TSV leakage failure can be successfully avoided, which can be very instructive for the improvement in TSV wafer-level package yield as well as device performance in advanced semiconductor technology.

Due to the existence of anisotropy, the previous isotropic assumption of silicon-based materials can no longer accurately characterize the mechanical behavior of materials. In this study, finite element analysis (FE A) method was adopted to research the effect of silicon anisotropy on the thermal stress of through silicon via (TSV) structure including copper pillar arrays in stacked 3D packaging chips under thermal cyclic loads. The simulation results show that, in both isotropic and anisotropic cases, the high thermal stress is always located at the interface between two materials in the structure. Compared to the isotropic case, the magnitude of thermal stress is always larger in the anisotropic case. In both isotropic and anisotropic cases, the maximum thermal stress in the bottom TSV copper column arrays is always slightly larger than that in the upper layer arrays, and the thermal stress of the copper column at the farthest diagonal line is most concentrated.

Through silicon via (TSV) has proved to be a vital interconnection component in three dimensional circuit intergration and advanced packaging, for it has incomparable superiorities in device miniaturization, high density and multifunction. However, in TSV structure, the stress of thermal mismatch between silicon and electroplating deposition(ECD) copper and the accumulated residual stress in process make thermal-mechanical reliability become a main factor affecting the development of TSV technology, which may perhaps result in serious reliability problems once an appropriate destressing treatment is not taken. In order to improve the reliability of TSV, annealing is used to facilitate the recrystallization of ECD copper and reduce structure stress. In this article, a large size TSV in which the diameter is 30µm and the depth is 200µm with a high density of 0.59% was fabricated and then filled with ECD copper. After a pre-CMP process, annealing experiments at different conditions were designed to get a less residual stress structure. TSV pumping was measured by Step Profiler. Scanning Electronic Microscopy (SEM) and Electron Backscattered Diffraction (EBSD) were used to characterize ECD copper after annealing. Effect of annealing on ECD copper was studied and appropriate annealing parameters were acquired according to the measured results above.

Relying on the advantages like high density integration and stacking, through silicon via (TSV) as an advanced technology has been widely used for three-dimensional integrated circuits (3D ICs). Copper filled in through silicon via (TSV-Cu) should be annealed to eliminate defects and residual stress after electroplating, which is beneficial to improve the performance of transistors. The subsequent deformation and thermomechanical reliability of TSV devices would be affected due to the change of the mechanical properties of TSV-Cu via annealing. With the help of nanoindentation characterization and finite element method (FEM) inversion, this paper studied the stress-strain relationship of TSV-Cu on five different annealing time at 400°C. The results showed that TSV-Cu had been softened by annealing and this phenomenon would be intensified with annealing time extended. However, up to 200 min annealing time resulted in indentation load and yield strength increasing instead of decreasing. This work provided theory guide for calculating the deformation and stress of TSV structure and reducing thermomechanical reliability issues.

In this paper, a three-dimensional heterogenous-integrated (3DHI) wafer-level packaging (WLP) process is proposed, and a radio frequency (RF) front-end module with two independent ultra-high frequency (UHF) receiving channels are designed and implemented, which covers 400 MHz–600 MHz and 2050 MHz–2200 MHz respectively for unmanned aerial vehicle (UAV) applications. The module is formed by wafer-to-wafer (W2W) bonding of two high-resistivity silicon (HR-Si) interposers with embedded bare dies and through silicon via (TSV) interconnections. Double-sided deep reactive ion etching (DRIE) and conformal electroplating process are introduced to realize the high-aspect-ratio TSV connection within 290 µm-thick cap interposer. Co-plane waveguide (CPW) transmission lines are fabricated as the process control monitor (PCM), the measured insertion loss of which is less than 0.18 dB/mm at 35 GHz. The designed RF front-end module is fabricated and measured. The measured return loss and gain of each RF channel is better than 13 dB and 21 dB, and the noise figure is less than 1.5 dB. In order to evaluate the capability of the 3DHI process for multi-layer interposers, the module is re-designed and fabricated with four stacked high-resistivity silicon interposers. After W2W bonding of two pairs of interposers and wafer slicing, chip-to chip (C2C) bonding is applied to form a four-layer module with operable temperature gradient.

The field of printed electronics is a rapidly-emerging area of research and development primarily concerned with low-cost fabrication materials and processes for electronic devices. As conventional, silicon-based electronics continue to push the physical boundaries of scaling in order to eke out increased performance for electronic devices, the field of printed electronics instead focused on niche applications where form, function, and cost are more important than absolute performance. To date, the application of printed materials and processes has yet to make a large impact in industry. However, while the application space currently being explored is vast, certain applications within the realm of printed electronics are particularly poised for adoption to industrial processes. Namely, the application of printed conductors.This work emphasizes this point by exploring a particular application of conductive materials of interest to the electronics industry at-large: packaging interconnects. Without high-performing, robust interconnects, packaged electronic devices and circuits may both suffer from degraded performance due to sub-par electrical performance and fail well before their expected lifetime. Therefore, the development of improved materials and processes for the purpose of fabricating electrical interconnects is of interest to all corners of the electronics community. Unfortunately, in order to fabricate these structures with printed materials and processes, the printed electronics community must first overcome a number of barriers, most of which are discussed in this work.First, the development of stable jetting conditions for inks containing metal nanoparticles is discussed. A general yet powerful approach to the formulation of rudimentary inks is developed. In tandem with developing strategies for creating reliable inks with respect to jetting, both the solubility enhancement and bound ligand minimization of metal nanoparticles are explored in order to ultimately boost the performance of printed conductors. Using a heuristic-driven experimental approach, metal nanoparticles with very high solubility (nearly 40% by mass) and relatively low ligand content are achieved.Next, two applications of three-dimensional printing of metal nanoparticle inks are explored. The first is the fabrication of freestanding pillars with the intention of replacing existing solder bump materials and processes. The process parameters most important to this technique, jetting frequency and substrate temperature, are thoroughly explored using both commercially-available as well as custom-made metal nanoparticle inks. In addition, characterization methods including electrical, mechanical, and chemical techniques are applied in order to investigate the sintering process for these three-dimensional features. Ultimately, the electrical and mechanical performance of freestanding pillars are shown to outcompete existing solder bump structures at process conditions that do not exceed 200 °C.The second application explored is the development of a single-step filling and bumping process for through-silicon vias (TSVs). Using the process developed for freestanding pillars as a foundation, fully-filled TSV processes are developed and studied in detail. The effects of process parameters such as jetting frequency and substrate temperature are investigated. Finally, arrays of successfully filled and bumped TSVs are finally bonded using thermocompression flip-chip bonding and electrically and mechanically characterized. The results indicate that, indeed, printed TSVs provide robust electrical and mechanical interfaces for electronic applications.

Electrical characteristics and reliability of the wafer-on-wafer (WOW) bumpless through-silicon via (TSV) structure are investigated, and the new lumped circuit model is proposed to simulate the performance of the structure. Including the actual contact resistance in the model, the integrity of the high-frequency signal can be accurately simulated. For the 12-layer stacked bumpless TSV structure with plasma cleaning at the via bottom, the transmission loss of the signal up to 20 GHz can be lower than 2 dB. High eye height and low jitter at 3.2 Gbps show excellent signal integrity for high bandwidth memory (HBM) applications. In addition, a complete reliability study, including thermal cycling test (TCT), highly accelerated stress test (HAST), and electromigration test, reveals excellent electrical and mechanical properties, indicating that the structure is robust with great potential for 3-D integration.

In this paper, the fabrication of the through-silicon via (TSV) is introduced and characterized. Pre-bond structural analysis and electrical tests were performed and analyzed to examine the robustness of the fabrication process and the structural integrity of the TSVs. It is shown that the TSVs are robust even after given stress. The influence of the presence of TSVs on nearby metal-oxide-semiconductor field-effect transistor (MOSFET) devices and metal interconnects is also characterized by means of electrical tests. The results show that the fabricated TSV is robust and that the presence of TSV does not pose significant impact on the performance of MOSFET as long as they are sufficiently distanced from each other.

Semiconductor products used in high-performance computing (HPC) and artificial intelligence (AI) applications require higher memory bandwidth, greater input/output (I/O) count, better power delivery network (PDN) performance and improved heat dissipation characteristics. To meet these requirements, a 2.5D package architecture with a Through Silicon Via (TSV)-bearing silicon (Si) interposer is mainly used in volume production. However, a redistribution layer (RDL) interposer is emerging as a cost effective and higher performance alternative. To implement an improved high-performance, multifunctional interposer, S-Connect technology has been developed that uses a multi-chip, fan-out interposer with various functionalities, such as a die-to-die (D2D) connection, where integrated passive devices (IPDs) and active devices can be integrated. If active devices are included in the interposer, S-Connect technology enables a 3D system where multiple active chips are vertically integrated. In this paper, the S-Connect design differences from the existing 2.5D package using Si interposer with TSVs and its fabrication process flow are explained. S-Connect technology provides manufacturing flexibility to apply various types of interconnects. Two different connect features will be discussed. Firstly, a Si connect will be explored having a back end of line (BEOL) and TSV approach that can provide the same die-to-die routing with smaller than $1-\mu \mathrm{m}$ line/space (L/S) and vertical connections as a Si interposer. The second option uses a multilayer RDL, which can be fabricated on Si, glass and even on the epoxy mold compound (EMC). The RDL can also provide vertical interconnects such as TSVs in Si. For demonstration, a test vehicle (TV) with one logic chip and two memory chips mounted on a multi-chip, fan-out interposer with an area approximately 1.5 times larger than the reticle was used. The interposer consists of two connect chips with $2-\mu \mathrm{m}$ L/S RDL and 6 mechanical IPDs located under the logic die. Two types of the connect chips were used - RDL on Si wafer and RDL on EMC having TMVs. The top die to interposer joints were made using $\mu$ -bumps with $25-\mu \mathrm{m}$ size on a $45-\mu \mathrm{m}$ pitch in the logic and $25-\mu \mathrm{m}$ size on a $55-\mu \mathrm{m}$ pitch in the memory die. Both the top and bottom sides of the fan-out interposer have a single layer of RDL. To interconnect the bottom side of the interposer and the package substrate, copper (Cu) pillar C4 bumps at $150-\mu \mathrm{m}$ pitch were formed. Once the top die and interposer assembly is complete, the subsequent processes are standard flip chip ball grid array (FCBGA) process flows. Moisture sensitivity and long-term reliability test results will be presented as well as warpage behavior, which is critical for the large body packages. Lastly, the advantages of the S-Connect package will be compared to other 2.5D and flip chip solutions in terms of manufacturability, ability to integrate multiple functionalities and cost.

In this letter, a quasi-coaxial through-silicon-via (TSV) is presented for millimeter-wave integrated circuit (IC) packaging. The quasi-coaxial-via (Q-COV) structure in which one side ground metal is removed can minimize the interconnect length when it is mounted, in comparison to the coaxial-via (COV) structure. Simulation analysis shows that the Q-COV has similar electrical characteristics as the COV up to 100 GHz even though there is no GND on one side. To make the small signal core of the Q-COV, the silicon-core metallization process was used and a Si-interposer with Q-COVs of 50- $\mu \text{m}$ core diameter was fabricated and mounted on the glass board for signal transition analysis. The measured transition loss in the mounted Si-interposer was very small, only about 0.6 dB at 100 GHz, and the return loss was more than 20 dB for the entire measured frequency band (0–110 GHz).

Flip-chip assembly accounts for more than 80% of the advanced packaging technology platform, compared to fan-in, fan-out, embedded die, and through silicon via (TSV). Flip-chip interconnect remains a critical assembly process for large die used in artificial intelligence processors; thin die that warps at elevated temperatures; heterogeneous integration in SiP applications; flip-chip on leadframe; and MicroLED die usage. This paper will first outline trends in evolving flip-chip and direct chip placement (DCP) technology, then will examine the changing nature of the solder bump, the interconnect itself, and the substrate. Many variables of the flip-chip assembly process will be discussed, including standard solder bumps to micro Cu-pillar bumps with different alloys; different pad surface finishes of Cu OSP, NiAu, and solder on pad (SOP); and from regular pads on substrates to bond-on-trace applications. A major focus will be on flip-chip assembly methods, from old C4 conventional reflow processing to thermocompression bonding (TCB), and the latest laser assisted bonding (LAB) technology, with an emphasis on how the usage of different technologies necessitates different assembly materials, especially fluxes. Flip-chip fluxes such as the commonly used water-washable flux, the standard no-clean flux, and the ultra-low residue flux, and how these fluxes react to different processing methods, will be an area of discussion. Finally, the paper will examine the need for increased reliability as the technology inevitably moves into the high-volume, zero-defect arena of automotive electronics.

The thermo-mechanical robustness of the bottom edge of an open through silicon via (TSV) is investigated by simulating the most critical step during the TSV process flow. In this step, stress arises due to the different thermal expansion coefficients of the materials forming the TSV. By employing the finite element method, the potential energy release rate of a crack at the TSV edge is calculated. The potential energy release rate, which quantifies the crack driving force, reaches its maximum when the diameter of the metal layers is ${\sim }1.25\times $ and ${\sim }1.5\times $ of the TSV diameter. Furthermore, when the metal diameter is three times the TSV, the crack driving force is reduced by ~50% for both aluminum and copper layers forming the TSV membrane. It was found that the crack tends to propagate perpendicularly to the TSV conductive layer, consistently with experimental observations. Meanwhile, the influence of the TSV membrane on the TSV conductive layer is negligible at distances further than 10% of the TSV height. Results show also that the reduction of 25% of the metal amount of the thickest layer lowers the crack driving force by 40% in comparison to the continuous layer.

We investigated the transmission characteristics of Cu/CNT composite Through-silicon via (TSV) interconnects. The equivalent lumped-element circuit model was established, with the effective conductivity employed for impedance extraction. The impacts of CNT filling ratio, temperature, and other geometrical parameters on the performance were examined.The sensitivity analysis of Cu/CNT composite TSVs was carried out. The electrical performance of Cu/CNT composite TSVs were optimized by utilizing low-permittivity dielectrics or even air-gap.

Using coaxial through-silicon technologies, a new 3-D capacitor integrated on a silicon interposer is proposed. The capacitance of coaxial through silicon via (CTSV) capacitors is extracted, analyzed, and compared. The results obtained from the analytical model and the finite-element method exhibit good agreement with various design parameters, and the error between the proposed model and measurement remains less than 7.41%. Due to high capacitance density up to 22.4 nF/mm2, the 3-D capacitor is adopted as a decoupling capacitor for the on-chip low-dropout (LDO) regulator design. The proposed LDO is developed in a 180-nm CMOS technology and shows unique advantages regarding the power supply rejection (PSR) performance, quiescent current, and area compared with that of the conventional LDOs with off-chip capacitors and capacitor-less (CL) LDOs.

As a 3D integration technology, the through silicon via (TSV) has attracted increasing interest owing to the need for reducing energy consumption in devices. However, high thermal stress is induced owing to large mismatches in the coefficients of thermal expansion (CTE) between the copper via and the silicon (Si) substrate in TSVs, causing critical reliability issues such as the performance degradation of stress-sensitive devices. We proposed a novel structure, the annular-trench-isolated (ATI) TSV, as a possible solution for the reliability issues caused by thermal stress in 3D packaging technology with TSVs. The ATI TSV structure has an extra Si ring outside of the metal core. We successfully fabricated an ATI TSV with a 10-μm diameter using separate etching processes for the insulator trench and the metal core. A narrow insulator trench with a thickness of 2 μm was formed, and its aspect ratio (AR) was as high as 10. A Si ring with a thickness of 1 μm remained between the insulator layer and the metal core. In order to study the stress level of the ATI TSV, we investigated the radial and axial thermal stresses using polarized Raman spectroscopy and a simulation by the Finite Element Method. Agreement between the simulation results and the measured stress data was observed and validated the simulation model. Furthermore, we revealed that the Si substrate of the ATI TSV had a lower thermal stress level than the regular TSV. This was accomplished using the validated simulation model owing to the redistribution of stress by the Si ring in the ATI TSV.

Three-dimensional (3-D) integration based on the through silicon via (TSV) technology involves the processes of wafer thinning, TSV etching and plating, re-distribution layer (RDL) formulation, and FC chip bonding. TSV plating is a key to the 3-D electrical interconnection, whereas the prewetting process is one of the important factors that can decide the filling depth and quality of the TSV plating. In this paper, a new three-step prewetting process with high efficiency and low cost is developed and includes absolute ethanol infiltration, deionized water washing, and a copper electrolyte bath. In the electroplating process, blind vias with an aspect ratio of 10:1 prewetted by our three-step prewetting process were fully filled. [2018-0190]

Cu-pillar/SnAg microbumps have been used for the latest 3-D through silicon via chip stacking. This microbumps flip-chip interconnection method can significantly further reduce the dimensions of the package and enhance the electrical performance by reducing interconnection path. As the pitch of the Cu-pillar/SnAg microbumps becomes extremely smaller, nonconductive films (NCFs) have recently been introduced to solve interconnection problems induced by the fine size microbumps. However, the applied pressure and heat during the thermo-compression (TC) bonding processes deform the SnAg solder and cause SnAg solder wetting on the sidewall of the Cu-pillar. The SnAg solder sidewall wetting causes rapid Sn consumption at the interface between the Cu-pillar and solder and decreases the joint gap heights of the SnAg solder joints. In this paper, the effects of the new double-layer NCFs (D-NCFs) were investigated for 40- $\mu \text{m}$ pitch chip-on-chip interconnection. The D-NCFs consisted of two NCF layers. The bottom NCF layer behaves as a conventional single NCF layer, and the top NCF layer, covering the Cu-pillar, prevents the movement of molten SnAg solder to the sidewall of Cu-pillar during the TC bonding process. As a result, the gap height of SnAg solder joints was doubled without SnAg solder sidewall wetting of Cu-pillar using the D-NCFs. SnAg solder joints using D-NCFs showed excellent reliability during thermal cycle tests up to 3000 cycles and pressure cooker test up to 72 h because of the significantly remaining Sn at the SnAg solder joint interface and increased joint gap height.

For 3D packaging using TSV technology, it is required various techniques such as forming via holes on a wafer, filling conductive materials and interpretation of TSV reliability etc. Among them, solving the issue of reliability are standing out as a big problem for reaching commercialization in the future. When the conductive material filled in the TSV is expanded by the high-temperature process during the packaging process, it breaks the insulating layer and the metal interconnection which exist on via hole by extruding from the surface of the Si wafer. In this study, in order to suppress the Cu extrusion, electroplating was attempted by adding silicon carbide powder having almost no difference in thermal expansion coefficient with the Si chip in the Cu electroplating solution. As a result, the extrusion height of Cu-SiC was about 164 nm that is a height corresponding to 14.6% of the extrusion height of Cu. This is considered to be the result of extremely effectively suppressing the extrusion phenomenon after annealing by adding SiC powder with a low coefficient of thermal expansion into the conventional Cu plating solution.

The shielded-pair through-silicon vias (SPTSVs) proposed in this paper feature superior transmission properties and high jamming immunity suitable for differential-mode and common-mode transmissions. Based on the recursive approximation algorithm, a novel and efficient method for characterizing the electromagnetic-temperature distribution in dielectrics is proposed for SPTSVs. In addition, considering the proximity effects and eddy current effect in substrate, the ultrabroadband parasitic admittance and electrical coupling models are derived based on 2-D time-varying field and transient polarization mechanism. The collaborative finite-element analysis shows that the proposed model highly agrees with the 3-D full-wave simulation (HFSS 14.0 and Maxwell v16) and the analytical calculation. Then, the dielectric relaxation properties for substrate and oxide are deeply characterized with different design parameters. Finally, the impacts of the substrate effect on electrical characteristics of SPTSVs are revealed.

The generalized plane deformation (GPD) mode is a simplified model that effectively reflects the information of whole chip and local regions. In this paper, we propose a modified-GPD model for thermal-stress analysis of through silicon via (TSV) interposer application. Highly doped poly silicon is used to fill TSV in our modeling. The boundary conditions are optimized. The accuracy is largely improved and the computation time is reduced compared with conventional GPD model.

The parasitic effect inside through-silicon via (TSV) packaging under radio frequency (RF) operation may cause abnormal signals in circuit performance. On the bases of a self-developed deembedding technique, we investigated the high-frequency characteristics of a typical TSV structure through direct measurements. To this end, a silicon substrate layout was first designed and constructed, followed by packaging mounting to build a suitable setting for RF measurements. Behaviors up to 3 GHz on different circuit segments in an actual TSV packaging were then measured directly by using an RF-inductance, capacitance, and resistance (LCR) meter, and R, L, and impedance (Z) data for test structures were then extracted and compared with those reported in the literature. To study the environmental effect on the RF properties of the TSV test samples, we monitored behaviors during a temperature-humidity reliability test.

The through-silicon via (TSV) approach is crucial for three-dimensional integrated circuit (3-D IC) packaging technology. However, there are still several challenges in the TSV fabrication process. One of the widely known challenges is via protrusion phenomenon. Annealing a TSV wafer makes the copper (Cu) TSVs under high stress and may form a protrusion where the Cu is extruded out of the TSV structure. The phenomenon occurs because of the large mismatch in the coefficient of thermal expansion between Cu via and silicon (Si) layer. Cu protrusion is able to cause crack, delamination of the back-end-of-line and short circuit of the chip, thus, it is a dangerous threat to the metal layer interconnect. Experiments are conducted to characterize the protrusion using several techniques. Scanning electron microscope is used to observe the protrusion topography and measure the height. Electron backscatter diffraction (EBSD) technique is implemented to study the grain size distribution, local texture and microstructure evolution inside Cu vias. For the experiment, arrays of 10 μm diameter TSVs are fabricated and annealed in argon gas environment in six different temperatures. In this paper, finite element analysis (FEA) is carried out to study the Cu protrusion under different annealing conditions. Correlation between numerical results and experimental data is then performed. Based on the verified FEA methodology, several parametric studies are then conducted, including the effects of annealing temperature on Cu protrusion, residual stress distributions of TSV structures. The simulation results are helpful to understand and solve the key problem in TSV fabrication process and reliability challenge.

This work demonstrated a new and promising approach to control via extrusion for three-dimensional integrated circuits (3DICs). By depositing 50 nm of Ta as a metallic cap, a significant reduction in both the magnitude and the statistical spread of extrusion was achieved. Thermo-mechanical and interfacial characterization were further carried out to study the mechanism of the observed effect. The results suggested that the Ta cap layer was able to effectively suppress the mass transport at via top surface and along grain boundaries, therefore reducing extrusion.

The anisotropy property of silicon is a basic property which has been discussed widely in the reliability assessment of electronic components. However, the effect of silicon anisotropy on the fracture behavior of through-silicon-via (TSV) has not been discussed in the available literatures. In this paper, the effect of silicon anisotropy on the crack driving force, e.g. energy release rate (ERR), is discussed thoroughly by considering different crack depths, aspect ratios as well as heating and cooling effects in typical TSV under three dimensional (3D) conditions. A semi-empirical formula to estimate the ERR of TSV crack under thermal loading is proposed incorporating the effect of silicon anisotropy. Through numerical computation and theoretical analysis of ERR for interface crack in TSV under thermal loading, the influence of silicon crystal orientation on ERR has been presented and compared. Because of silicon anisotropy, the level of ERR under 3D case considering silicon anisotropy is much more remarkable than that of ERR under linearly isotropic 3D case and linearly isotropic 2D case, which reveals the significant role of silicon anisotropy on interface fracture of TSV. A discussion is also carried out to show the neglect of silicon anisotropy will lead to underestimation of cracking behavior for interface crack of TSV. The effect of TSV-Cu plasticity on the interface cracking behavior is also presented in which the so-called “constraint effect” is also found in the interface cracking behavior of TSV. The crack driving forces under various sizes of TSV with different crack depths are also given and discussed in this paper, which shows that the size effect also exists on the estimation of ERR for interface crack in TSV under thermal loading.

In this paper, a through-silicon via (TSV) array under Gaussian pulse is studied comprehensively with a rigorous consideration of its electrothermal characteristics. To enhance the computational efficiency and reduce the memory cost, we develop a unified radial point interpolation method (RPIM) to handle these TSV electrothermal coupling problems. The comparison between the results of the proposed formulas and fine-grid finite-element method (FEM) shows that the RPIM has a very high accuracy and reduces computational time by up to 88% in comparison with the fine-grid FEM. The transient temperature responses are studied in detail for three layouts of single-layered TSV arrays with different silicon dioxide layer thicknesses and areas enclosed by TSVs. Furthermore, the two-layered TSV array structure including microbumps and RDLs is simulated electrothermally to verify the scalability of this method. Our work demonstrated the capability of addressing a large number of TSV arrays and the proposed method enables faster and more accurate electrothermal design of TSV-based 3-D ICs.

Through silicon via (TSV) is one of the most important technologies in 3-dimensional wafer/chip stacking. However, there are some issues related to defect-free TSV filling and Cu pumping. In this study, a defect-free TSV filling was achieved using iodide ions. The working mechanism of iodide ions in TSV filling was systemically investigated by electrochemical measurements; It was found that the formation of CuI on the electrode surface is a key process for inhibiting Cu ion reduction. This inhibition effect of iodide ions enables defect-free TSV filling. Furthermore, the study of microstructure of the filled Cu revealed that the electrochemical reduction of CuI during the TSV filling forms small Cu grains in TSV. The small Cu grains cause Cu pumping in subsequent processes, which damages semiconductor devices. We achieved a defect-free TSV filling with enlarged Cu grains using a two-step filling method that effectively promotes the direct reduction of Cu ions rather than electrochemical reduction of CuI.

Accurate and reliable models can support Through Silicon Via (TSV) testing methods and improve the quality of 3D ICs. A model for expressing resistance and inductance of TSVs at frequencies...

A phase-field-crystal model is used to investigate the processing-structure-protrusion relationship of blind Cu through-silicon vias (TSVs) at the atomic scale. A higher temperature results in a larger TSV protrusion. Deformation via dislocation motion dominates at temperatures lower than around 300°C, while both diffusional and dislocation creep occur at temperatures greater than around 300°C. TSVs with smaller sidewall roughness $R_{a}$ and wavelength $\lambda _{a}$ exhibit larger protrusions. Moreover, different protrusion profiles are observed for TSVs with different grain structures. Both protrusions and intrusions are observed when a single grain is placed near the TSV top end, while the top surface protrudes near both edges when it contains more grains. Under symmetric loading, coalescence of the grains occurs near the top end, and a symmetric grain structure can accelerate this process. The strain distributions in TSVs are calculated, and the eigenstrain projection along the vertical direction can be considered an index to predict the TSV protrusion tendency.