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In this article, we design, demonstrate, and characterize a 3-D printed package-level polymer jet impingement cooling solution on a $23\times23$ mm2 thermal test chip. The experimental hardware results for a nozzle pitch of 2 mm show that, with 1-kW power dissipation, at a coolant (deionized (DI) water) flow rate of 3 liters per minute (LPM), the measured average chip temperature increase is ~65 °C with a cooler pressure drop of 0.15 bar between the inlet and outlet connections. It is also shown that bare die cooling without lid [and thermal interface material (TIM)] shows better cooling performance than the lidded package. Second, an advanced 3-D printed manifold with an additional flow redistribution structure is demonstrated. The experimental results show that the improved design achieves a better chip temperature uniformity compared to the reference design, showing a reduction of the chip temperature gradient with a factor of 4 and 2.3 for a flow rate of 0.5 and 3 LPM, respectively, while no significant impact on the cooler pressure drop was measured. The numerical modeling studies predict an additional 15.4% thermal performance improvement, by reducing the nozzle pitch from 2 to 1 mm, for a flow rate of 3 LPM.

This article presents the design, fabrication, experimental characterization, and modeling analysis of the chip-level hotspot targeted liquid impingement jet cooling for high-power electronics. The hotspot targeted jet impingement cooling concept is successfully demonstrated with a chip-level jet impingement cooler with a 1-mm nozzle pitch and 300- $\mu \text{m}$ nozzle diameter fabricated using high-resolution stereolithography (additive manufacturing). The computational fluid dynamics (CFD) modeling and experimental analysis show that the improved hotspot targeted cooler design with fully open outlets can reduce the on-chip temperature difference by 70% compared with the full array cooler at the same pumping power of 0.03 W. The local heat transfer coefficient can achieve $15\times 10^{4}$ W/m2 K with a local flow rate per nozzle of 40 mL/min, requiring a pump power of 0.6 W. The benchmarking study proves that the hotspot targeted cooling is much more energy-efficient than uniform array cooling, with lower temperature difference and lower pump power.

The chip-level bare die direct liquid impingement jet cooling is regarded as a highly efficient cooling solution for high-performance applications. Furthermore, it shows potential to be integrated inside the chip package. In previous studies, we demonstrated this cooling concept using a prototype fabricated with mechanical micromachining using polymers. With the improvement of fabrication resolution, additive manufacturing or 3-D printing technology enables the fabrication of low-cost polymer microjet coolers with complex internal 3-D geometries and allows easy customization of the cooler design. In this paper, a chip-level impingement jet cooler with a $4 \times 4$ jet array and 575- $\mu \text{m}$ nozzle diameter is fabricated with high-resolution stereolithography, and assembled directly on the top of the bare die. The modeling study shows that the pressure drop in the 3-D printed cooler is reduced by 24% compared to the micromachined (MM) cooler with the same nozzle dimensions thanks to an improved more complex internal geometry. The fabrication quality and tolerances of the printed cooler are evaluated using optical measurements, scanning acoustic microscope (SAM) inspection, and cross-sectional analysis, showing a measured average nozzle diameter of 575 $\mu \text{m}$ compared to the designed nozzle diameter of 600 $\mu \text{m}$ . Moreover, the 3-D computational fluid dynamics (CFD) simulations used in this paper are experimentally validated by chip temperature measurements. The achieved minimal thermal resistance of 3-D printed $4 \times 4$ cooler is 0.16 cm $^{2}\cdot \text{K}$ /W for a flow rate of 1000 mL/min. The benchmarking study shows the cooler size can be reduced by a factor of 6.5 by using the 3-D printing technology compared to the MM cooler.

In this paper the stacking process development and the characterizations of multi-die stacks N=16, which contain 15 thinned top dies on a bottom die, are described. A comparison study between sequential and vertical collective bonding, to see the impact on their characteristics is examined in detail. Also, an in-situ temperature measurement during stacking is performed and a simulation is done to find the proper thermo compression bonding (TCB) profile to stack a large number of dies with good soldering connection also on the bottom die. Multi-die stacks with high alignment accuracy and good electrical yield (e-yield) are made and characterized by cross-section SEM, SAM and X-RAY analysis.

3D wafer-to-wafer bonding is a promising fabrication method to create 3D systems with a very high interconnect density. The thermal resistance of the 3D bonding interface can represent a significant contribution of the overall thermal resistance in the 3D chip stack and should therefore be accurately characterized. In this paper, we present the experimental characterization of two different types of 3D wafer-to-wafer bonding: Cu/dielectric hybrid bonding and via-last dielectric bonding. First, we introduce the wafer-level test vehicles and the characterization methodology for the analysis of both bonding interfaces. Then, we estimate the thermal resistance of the bonding interface based on a combination of temperature measurements and finite element thermal simulations. Benchmarking of the measurement results with available literature data on thermal resistance values of 3D interfaces shows that wafer-to-wafer bonding results in a reduction of the bonding layer thermal resistance of 5x and 20x for the hybrid bonding and dielectric bonding respectively, compared to the standard die-to-wafer bonding approach with micro-bumps and underfill.

Future high-performance applications require in-package optical modules to enable the high bandwidth requirements. This is enabled by the co-integration of a silicon photonics module with a host IC in a single package. Since the silicon photonic elements are very sensitive to temperature changes, the optical performance can be affected by the thermal coupling effects in these co-integrated packages.In this paper, a thermal modeling study is presented for the test case of a BGA package that contains a 300W host IC and an Si photonics optical I/O module with 32 channels. The thermal model, calibrated with global package level measurements, are well as with local device measurements, shows a large level of thermal coupling from the host IC to the optical module. Although the thermal coupling between individual photonic elements is shown to be in the order of 1%, the combined thermal coupling for the 32 channels reaches 28%, indicating the clear need for a detailed thermal analysis.

In this paper, spacer bumps concept is introduced to increase the process window for TCB, lower the sensitivity of electrical yield to bump height variation, maintain the gap between two dies and to prevent too much solder deformation for a test vehicle having multi-diameter bumps from 40um down to 5um pitches. Adding spacer bumps improves the electrical yield dramatically to close to 100% and ensures having good solder joint and IMC formation for both face to face N=2 and back to face N=4 stacks.

This work presents, for the first time, a package- level, bare die liquid jet impingement 3D polymer microfluidics heatsink fabricated using 3D printing, or additive manufacturing for large die size and high-power applications. The heatsink achieves a chip temperature increase of 17.5°C at a chip power of 285 W for a coolant flow rate of 3.25 LPM, demonstrating that 3D printing enables the design for low-cost, high efficiency direct on-chip microfluidic heatsink with complex internal 3D manifold liquid delivery channels. The measurement results show that the jet impingement cooling performance can be successfully described using a unit cell approach, allowing an easy scaling of the thermal performance for arbitrary die size applications. Long term thermal tests of 1000h show a constant thermal performance and no degradation of the cooler material.

In this paper we address the thermal, mechanical and reliability performance of wafer-to-wafer hybrid bonded CMOS wafers manufactured using standard 65nm technology. Proprietary chip design includes different test structures which enable assessment of hybrid interconnect yield and mechanical induced stress as well as thermal measurements with high spatial resolution. Different tests are conducted to reproduce thermo-mechanical stresses similar to the ones induced in flip-chip assemblies. The study, supported by the finite element simulations includes hot-spot thermal analysis where thermal resistance of hybrid interface is evaluated and the heat spreading effect in both wafers is compared.

In this work a Cu pillar design that combines a stiff metal pedestal with a soft polymer as buffer layer has been integrated in a dedicated test vehicle to investigate the thermo mechanical stress induced during flip chip assembly. In-situ electrical measurements of dedicated stress sensors during a Bump Assisted BEOL Stability Indentation (BABSI) test were performed to assess the strength of the bump designs. Furthermore, the package induced stress was monitored in different regions of the test chips by measuring and comparing the ION current of the stress sensors before and after packaging. By combining in-situ electrical measurements and finite element modeling it was possible to quantify the stress level induced in the Si die after packaging. Additionally, the package out of plane deformation has been measured after flip chip to laminate and after molding. The results show that the use of a stiff pedestal is very efficient to mitigate packaging induced stress. It has also been shown that the out of plane deformation is independent of the Cu pillar design.

Jet impingement cooling with distributed outlet configuration is regarded as an efficient cooling solution for high performance systems. This work develops the Nusselt number Nu ¯ f - R e d and pressure drop k -factor correlations for microscale multi-jet impingement cooling with alternating feeding and draining jets. An extensive design of experiments (DOE) of unit cell modeling-based simulations is used for the correlation fitting. In order to understand the flow and thermal behavior, the impact of single variables including the inlet diameter, outlet diameter, jet-to-target distance and nozzle length is studied systematically. On the other hand, this work firstly shows the predictive model with k - R e d , including the impact of nozzle length t/L, cavity height H/L and inlet diameter ratio d i /L. Finally, the extracted correlations are experimentally validated, both with experimental data of different jet impingement demonstrators, as well as with the literature experimental data.

Package level bare die jet impingement cooling on the chip backside has been previously demonstrated as a highly efficient jet cooling solution for high power devices, by eliminating the thermal interface material. However, bare die jet impingement cooling is a disruptive cooling technology requiring direct access to the backside of the semiconductor device. A less disruptive cooling implementation in which the impingement cooling is applied on the lid is now investigated as an intermediate step. In this work, the first comparison of the cooling performance with the liquid micro-jet array impingement cooling on lidded and bare die package is conducted and experimentally characterized for polymer coolers fabricated by additive manufacturing. The thermal characterization is performed on a 2.5D integrated system that contains two advanced thermal test dies. In addition, besides the reference cooler with vertical coolant supply channel, an improved design of 3D printed fluid delivery manifold with lateral inlet/outlet channels is introduced and benchmarked. The experimental and numerical comparison show that the cooler with the lateral feeding manifold requires 60% less pumping power with respect to the vertical feeding manifold for the same high thermal performance while reducing the overall thickness of the cooling solution by a factor of 2.

3D ICs integration has shown significant advantage in performance enhancement and power reduction. One of the key components in 3D integration technology is to stack multi-layer thinned ICs to make a reliable electrical and mechanical connection. Thermo compression bonding (TCB) has been used to manufacture 3D ICs due to its capability to bond fine pitch micro bumps. However, it has been a challenge for TCB process to control the temperature over the bonding interfaces and it increases its complexity when multi bonding interface are bonded at once. In this paper we use integrated thermo sensor to investigate temperature gradient during TCB for multi die stacking. The real time temperature measurements are combined with finite element modeling (FEM). The calibrated model is used to explore temperature in bonding interfaces that are not accessible through measurement and enhance the understanding of heat transfer during the TCB process for multi die stacks.

This work focuses on the experimental evaluation of thermo-mechanical stress induced in flip-chip BGA packages. The proprietary Si chip with integrated piezoresistive stress sensors is used to electrically measure chip package interaction (CPI) effects with high spatial resolution of 5$\mu$ m. The electrical measurements are supported by finite element modeling which consecutively simulates different assembly steps such as flip-chip, application of underfill (UF), molding, and uses the experimentally determined thermo-mechanical properties of the packaging materials.

In this paper a novel solder-based die-to-die or wafer-to-wafer interconnect approach is introduced. This technique allows for microbump interconnects with different diameters on a single die and allows for pitch scaling down to 5μm A metal damascene process is used to create the metal pad layers for soldering. Solder μm bumps are created by semiadditive electroplating. After embedding the solder u bumps in a partially cured polymer, the wafer surface is planarized and the solder surface is exposed. This results in flat die surfaces of the die before bonding. Using a thermo-compression bonding process these flat surfaces can be aligned, the solder reacts with the metal pad to form a solder joint and the polymer can bond and cure to ensure a void less underfill layer for mechanical strength and increased reliability. The selection of suitable metals and polymers as well as the different process steps together with reliability data will be discussed in detail. Electrical yield and quality of bonding is demonstrated using imec 5μm pitch PTCU/W test vehicle for die to wafer bonding.

Liquid microjet impingement cooling has shown the potential to be the solution for heat removal from electronic devices such as very-large-scale integration (VLSI) chips. The post-impingement dynamics of the jet, specifically the interaction between the liquid fronts on the surface engendered by the jets is a critical criterion improving the heat transfer characteristics. While some seminally important experimental studies have investigated this attribute, the amount of accurate data and analysis is limited by the shortcomings of real-life experiments. In this article, numerical investigations into the fluid dynamics and heat transfer in microjet cooling systems are carried out. Specifically, this paper addresses the question regarding the necessary fidelity of the simulations. Different Reynolds-averaged Navier&ndash, Stokes (RANS) models are compared to the Large Eddy Simulations (LES) simulation and the potential fidelity of different eddy-viscosity-based closures is clearly shown. Recommendations are made regarding the RANS closures that should give the best performance. It is demonstrated that the transition Shear Stress Transport (SST) model and k - &omega, SST model both show excellent ability to predict the local or average Nu, and also local level pressure coefficient f with less than 5% difference in the range of 30 &lt, Red &lt, 4000, compared with the reference LES model. For the experimental measurements in the range of 130 &lt, 1400, the LES model, transition SST model and k - &omega, SST model all show less than 25% prediction error. Moreover, it is shown that the validity of the unit cell assumption for the temperature and flow distribution depends on the flow rate.

© 1986-2012 IEEE. A high-efficiency three-dimensionally (3-D) shaped polymer multi-jet impingement cooler based on cost-efficient fabrication techniques is introduced for the cooling of high-power applications. State-of-the-art highly efficient multi-jet cooling solutions rely on expensive Si or ceramic fabrication techniques, while low-cost cooling solutions have been proposed for less performant single-jet impingement. In this paper, we present the concept, modeling, design, fabrication, experimental characterization, and benchmarking with literature data of a multi-jet impingement based liquid cooling solution, fabricated using low-cost polymer fabrication techniques, targeted to directly cool the backside of high-power devices. For the modeling study, unit cell model and full system level models are used to study the nozzle array scaling trends and thermal and fluidic jet-to-jet interactions. Furthermore, design guidelines for high-power electronics cooling are provided, including geometry selections, material selection, and fabrication techniques. Based on the design guidelines and cooling concept, this paper demonstrates a 3-D-shaped polymer impingement cooler with a 4 × 4 nozzle array, showing a very good thermal performance with low required pumping power. The multi-jet cooler can achieve heat transfer coefficients up to 6.25 × 10 4 W/m 2 ·K with a pump power as low as 0.3 W. The benchmarking study confirms furthermore that multi-jet cooling is more efficient than single-jet cooling and that direct cooling on the backside of the semiconductor device is more efficient than cooling the substrate or base plate. ispartof: IEEE TRANSACTIONS ON POWER ELECTRONICS vol:34 issue:7 pages:6601-6612 status: published

Bare die liquid jet impingement cooling is an efficient cooling technique that has been successfully applied using various materials to create high performance cooling solutions. 2.5D Si interposer packages with several Si chips integrated side by side are a potential integrated solution for high performance systems. In this paper, we present the design, modeling, fabrication and experimental thermal characterization of 3D-printed impingement coolers applied to 2.5D Si interposer packages that contain two 8×8 mm2 thermal test chips with integrated heaters and sensors. 3D-printing enables to use low cost materials for the cooler fabrication, to print the whole geometry in one piece and to customize the design to match nozzle array to the chip power map. The fabricated coolers have been applied to both lidless packages allowing the cooling solution to be directly applied to the backside of the chips, and to lidded packages that require a TIM between chip and lid. The thermal performance of the impingement cooler, including the chip self-heating and the thermal coupling, has been assessed for both package configurations using CFD simulations and experiments. A design of experiments of the TIM and lid properties has been performed to assess the tradeoff of the beneficial and detrimental impact of the lid for different flow rates, in order to define guidelines for 2.5D interposer package thermal management solutions.

Electromigration mechanisms of W-heaters with Cu connections at each line end to supply the current to the heater were studied. For making reliable lifetime estimates, a temperature profile is proposed based on infra-red (IR) microscopy, electromigration activation energies and failure location. For our structure, we show that the temperature of the void location is close to the ambient temperature and hence the lifetime prediction methodology should take this into account. Also, different test methodologies for this application are benchmarked, where we show that iso-thermal electromigration tests have only a limited impact on the lifetimes of our structures.

We describe an X-ray diffraction imaging technique for nondestructive, in situ measurement of die warpage in encapsulated chip packages at acquisition speeds approaching real time. The results were validated on a series of samples with known inbuilt convex die warpage, and the measurement of wafer bow was compared with the results obtained by optical profilometry. We use the technique to demonstrate the impact of elevated temperature on a commercially sourced micro quad flat nonlead chip package and show that the strain becomes locked in at a temperature between 94 °C and 120 °C. Using synchrotron radiation at the Diamond Light Source, warpage maps for the entire $2.2~\textrm {mm} \times 2.4~\textrm {mm} \times 150$ - $\mu \text{m}$ Si die were acquired in 50 s, and individual line scans in times as short as 500 ms.

Previous research studies showed that bare die liquid multi-jet impingement coolers with locally distributed outlets using silicon processing, mechanical micromachining, and additive manufacturing technology can achieve high cooling efficiency for high power electronic applications. The nozzle density is a crucial factor for thermal performance as well as for selecting the required fabrication technology. However, general design guidelines for the optimal nozzle density and cavity height are still missing in literature. In this paper, the impact of nozzle density on direct multi-jet impingement jet cooling is investigated using experiments and numerical modeling for an N × N nozzle array. The general scaling analysis with experimentally validated models is investigated based on three independent design parameters: nozzle density (N2/A), nozzle diameter (di) and cavity height (H). The objective is to find the optimal design parameters and to study the scaling trends. The experimental studies show that a very good thermal performance for the 8 × 8 jet array cooler with 1 × 1 mm2 cooling cells has be achieved as low as 0.13 cm2-K/W for a flow rate of 1000 ml/min. The best cooler design, expressed as the cooler with the highest COP value, can be achieved in the middle range of the nozzle density between 30 and 300 nozzles per cm2 for the constant flow rate consideration. Comparisons in terms of constant cooler flow rate or constant pumping power will result in different optimal design parameter values.

High efficiency direct liquid jet impingement cooling with locally distributed outlets is very promising in high power electronic devices. In order to elucidate the flow-thermal interaction for micro-scale jet impingement cooling, sensitive temperature measurements with high spatial and temporal resolution are required. In this work, a programmable thermal test chip with 832 heater cells with 75% heater uniformity and 3232 array of temperature sensors is introduced. The detailed measured temperature maps for different power dissipation patterns allow the in-depth study of the thermal performance of liquid jet impingement coolers and the detailed experimental validation of complex CFD models. The modeling and measurement study is applied to two jet impingement cooling implementations: 1) a single jet cooler with a 2 mm diameter nozzle, and 2) a multi-jet cooler with a 4×4 array of 500 µm inlet nozzles and distributed outlet nozzles. For both cooler configurations, the temperature measurements and CFD modeling results are investigated and compared for uniform and hot spot power dissipation patterns. ispartof: APPLIED THERMAL ENGINEERING vol:152 pages:308-318 status: Published online

In this work we demonstrate that high power density of 600 W cm−2 can be effectively dissipated by conductive/convective cooling using a silicon interposer with integrated micro-channels. This technology proved to limit the temperature increase of a 5 mm2 power chip to only 34 K when operated at 150 W. The cooler technology is developed on a silicon semiconductor platform and is applicable to interposer technologies.

In this paper optimization process of D2W (Die to Wafer) TCB (Thermal Compression Bonding) stacking for thinned, warped and large dies are investigated. TCB related characteristics of WLUF (Wafer Level Underfill) is studied in detail by both analytical calculations/simulations and insitu deformation measurement techniques and then the results are used to lower the required bond force of TCB profile. Further optimizations include the enhancement of the interface temperature uniformity, and modification of the top bond tool called Thermode. These optimizations result in good flattening of the thin and warped large die, and uniform pressure distribution during the TCB process. The large stacked dies show very low warpage, very good joint formation between TSVs and 20um pitch microbumps and close to 100{\%} electrical yield.

In this work, an in-situ resistance measurement method is proposed to investigate the interfacial solid state reaction of alternative metallurgies, such as Ni and Cu/Ni as UBM materials, with Sn solders. The electrical properties of formed IMC phases for different metallurgies systems are extracted and discussed. Kinetic parameters, such as activation energy and power factor, of Ni/Sn and Cu/Ni/Sn solid-state reaction are extracted from in-situ resistance measurement. Power factor of Ni/Sn and Cu/Ni/Sn kinetic reaction indicate that the IMC evolution behaviors involve bulk diffusion-controlled (the time exponent n = 0.5) for Ni/Sn, while the growth evolution of (Cu,Ni) 6 Sn 5 in Cu/Ni/Sn solid state reaction involves grain-boundary diffusion controlled (the time exponent n = 0.33) from in-situ resistance measurement. This proposed in-situ measurement methodology has the advantages of being quick and accurate to understand and characterize the reaction and phase formation between UBM and solder materials for 3D applications.

In this paper, we report on a silicon-based compact micro channel heat sink that enables high heat flux dissipation. Using advanced CMOS compatible silicon fabrication, high aspect ratio micro channels, 32 μm wide and 160 μm deep were realized. The heat sink was interfaced to a small 5.0 mm × 5.0 mm silicon-based thermal test chip. A very low thermal contact resistance between the heat sink and the heater die was achieved using an optimized Cu/Sn-Au interface. As a result, a low total thermal resistance of 0.36 K/W (9mm2K/W) at the pump power of about 2 W was achieved on the assembled device. The design, fabrication, measurements on cooling performance and 3D modelling of the device are included in this paper.

In this paper, we present the assessment of the thermal performance of four different 3D packaging concepts for the integration of logic and memory in a generic 5” mobile device: package-on-package (PoP), 3D stacked die in BGA package, Si interposer in BGA package and a reconstructed wafer level chip scale package (RWL-CSP) interposer. The thermal performance is compared using an experimentally validated conduction model. The simulation study for the evaluation of different system level cooling solutions for all four packages show that spreading the heat close to the heat source (in the package) is more efficient than the system level spreading.

© 2018 IEEE. Liquid jet impingement cooling is a very efficient cooling technology for high performance devices. Previous studies demonstrated that polymers can be used as a cost effective alternative for Si for the fabrication of impingement coolers. The recent developments in additive manufacturing or 3D printing technology enable the potential to fabricate low cost polymer coolers with complex internal channels. In this paper, the use of 3D printing is discussed for the fabrication of a chip level polymer impingement cooler. The paper presents the cooler design, the manufacturability aspects and the characterization of several 3D printed coolers with different nozzles arrays. The challenges and opportunities for the use of 3D printing for this applications are discussed. A methodology to provide design guidelines for 3D printed liquid impingement jet coolers is elaborated. ispartof: pages:2389-2396 ispartof: 2018 IEEE 68th Electronic Components and Technology Conference vol:2018-May pages:2389-2396 ispartof: 2018 IEEE 68th Electronic Components and Technology Conference location:San Diego date:29 May - 1 Jun 2018 status: Published online

In this work the focus is on thermo-mechanical aspects of Chip Package Interaction (CPI) in flip-chip Chip Scale packages (fcCSP) packages. To minimize mechanical stress induced during flip-chip process, the laminate substrate with very low coefficient of thermal expansion (CTE) of the core material (?5 ppm/°C) is used. Mechanical stress induced in Si chip after every main assembly step is measured using the proprietary chip with integrated stress sensors and is simulated using calibrated finite element models. In particular, two flip-chip processes, i.e. Mass Reflow (MR) and Thermo-Compression Bonding (TCB) are benchmarked. The effect of application of capillary underfill (CUF) on mechanical stress is separately studied and shown to be not significant. The CPI effect of low-CTE substrate on mechanical stress is benchmarked with that induced by the substrate with conventional thermo-mechanical properties. The benefits of lowering core' CTE in terms of stress are clearly demonstrated. This is also confirmed by finite element modeling which reveals that stress induced in Si after flip-chip die attach process is very sensitive to the effective CTE of the substrate.

Where the introduction of 3D stacked ICs offers opportunities for new and faster applications, the use of ultra-thin stacked Si dies leads to new reliability challenges. One such challenge is to cope with the thermo-mechanical stresses induced by mismatches in the Coefficient of Thermal Expansion between the different materials used for stacking and packaging such as Si, copper, overmoulds, laminates and underfills, amongst others. These stresses are a key-concern for today's 2D-technologies and are even more severe for 2.5/3D-stacking and -packaging technologies with high interconnect densities.

Graphical abstractDisplay Omitted We combine the BABSI test with in-situ monitoring of the response of stress sensors below the Cu pillar.Good agreement was found between the applied loads, the response of stress sensors and FEM.Electrical and mechanical failures are detected during the BABSI test. Chip-package interaction (CPI) is becoming a critical issue for the reliability of back-end-of-line (BEOL) during or after package assembly. Complex BEOL layer stacks must have sufficient mechanical strength to survive the thermally induced stresses during processing or working lifetime. Therefore, it is necessary to assess possible failure mechanisms already at early phases of development so that the integrity of the chips can be guaranteed. This paper presents an advanced experimental stability test that combines a BABSI test (Bump Assisted BEOL Stability Indentation test) with in-situ monitoring of the induced stress during this test. A good agreement was found between the applied loads to the BEOL stack, the response of stress sensors below the bump (a Cu pillar) and finite element simulations.

© 2017 IEEE. A novel 3D-shaped polymer multi-jet impingement cooler based on low cost fabrication techniques is introduced for high performance applications. This paper presents the modeling study, design, fabrication, experimental characterization and benchmarking of this cooling concept, showing a very good thermal performance with low required pumping power. ispartof: pages:733-736 ispartof: 2017 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) pages:733-736 ispartof: 63rd IEEE Annual International Electron Devices Meeting (IEDM) location:San Francisco: CA date:2 Dec - 6 Dec 2017 status: published

In this paper the passivation effect of thin electroless metallic layers such as Au, NiB or Immersion Sn or thin organic layers such as Self Assembled Monolayer (SAM) on Cu, Co and Ni UBM microbumps is studied during Thermo-Compression-Bonding (TCB) and after anneal with conditions that were identified to be equal to 10 years working device at 80°C on an electrical test vehicle. Characterization with X-section SEM is done to look at the wettability and joint formation and electrical resistance measurement are performed to determine the yield.

Cobalt based UBM (under bump metallization) has the advantages of less UBM consumption, single and ductile IMC (intermetallic compound)) and no Kirkendall voids formation which makes it interesting for 3D stacking specially in fine pitch microbumps. In this paper for first time the electrical properties of Co-Sn IMC and kinetics of IMC growth are investigated by in-situ resistance measurement. Extracted parameters are verified by conventional cross section SEM analysis. This technique has the advantages of being non-destructive, quick and accurate measurement for any UBM and solder materials for 3D applications.

Thermal compression bonding (TCB) is becoming an increasingly important process step in the assembly of advanced components such as fine pitch flip chip packages, system-in-package products, and 3D IC's. To increase the throughput and robustness of TCB processes, it is crucial to understand and control important process parameters like time, force and temperature. However, for TCB processes it becomes challenging to measure and control the temperature over the bond interface, since typically different temperature profiles are applied to top chip and substrate. This paper proposes and validates a new methodology for temperature measurements and characterization of heat transfer during a TCB process. On-chip thermal sensors measure the temperature in real time during the TCB process, at different locations on both top and bottom chips. Since the proposed methodology does not require the insertion of a thermocouple in between the top chip and substrate, it will enable more reliable measurements, especially for fine pitch micro bump devices.

In this work a Cu pillar design that combines a stiff metal pedestal with a soft polymer as buffer layer has been integrated in a dedicated test vehicle to investigate the thermo mechanical stress induced during flip chip assembly. In-situ electrical measurements of dedicated stress sensors during a Bump Assisted BEOL Stability Indentation (BABSI) test were performed to assess the strength of the bump designs. Furthermore, the package induced stress was monitored in different regions of the test chips by measuring and comparing the ION current of the stress sensors before and after packaging. By combining in-situ electrical measurements and finite element modeling it was possible to quantify the stress level induced in the Si die after packaging. The results show that the use of a stiff pedestal is very efficient to mitigate packaging induced stress.

This paper presents the performance of a MEMS zero-level chip cap package implemented with through-the-cap vertical interconnects. The interconnect as well as the hermetic bond and sealing are established using flip-chip thermo-compression bonding by creating a copper-tin to gold metallic (solder) joint. The hermeticity of the packages is assessed via electrical measurements of encapsulated MEMS resonators and the RF performance of 3D interconnects is evaluated via microwave measurements of integrated coplanar waveguides. Design guidelines imposed by concurrent requirements of the flip-chip assembly process and the RF performance are discussed. The developed technology for the MEMS cap uses CMOS-compatible materials and the CMOS fabrication process.

Chip Package Interaction (CPI) gained a lot of importance in the last years. The reason is twofold. First, advanced node IC technologies requires dielectrics in the BEOL (back-end-of-line) with a decreasing value for the dielectric constant k. These so-called (ultra) low-k materials have a reduced stiffness and reduced adhesion strength to the barrier materials, making the BEOL much more vulnerable to externally applied mechanical stress due to packaging. Secondly, advanced packaging technologies such as 3D stacked IC’s use thinned dies (down to 25 μm) which can cause much higher stresses at transistor level, resulting in electron mobility shifts of the transistors. Also the copper TSV (through-silicon-via) generates local stress which affects the device performance. This paper considers both the packaging impact on BEOL integrity and transistor mobility shifts for 3D stacked IC (integrated circuit) technologies.

Barrier reliability in 3D through-Si via (TSV) Cu interconnections requires particular attention as these structures come very close to the active devices and Cu diffusion into the silicon substrate would significantly affect device performance. This work focuses on a via-middle process flow, which implies processing of the 3D-TSV after the front-end-of-line (FEOL) process, but before the back-end-of-line (BEOL) interconnect process. This results in several high temperature processing steps after TSV fabrication, including a final device wafer sintering step, generally in the 400^oC range. Thus, it becomes essential to study the stability of the TSV Cu-barrier at these temperatures to ensure a reliable integration of 3D TSV in CMOS wafers. TSV aspect ratios can vary as function of the integration scheme, for instance in a via-last or via-middle flow, and thus barrier continuity requires conformality which guarantees the presence of a diffusion barrier until the bottom of the TSV. Target conformality can either be obtained by PVD, typically for TSV A.R.=

This paper reports on the mechanical design, the fabrication technology and the key performance and reliability aspects of novel 0-level thin film vacuum packages for (RF-)MEMS. The packages typically feature a dielectric cap composed of nanoporous alumina and PECVD silicon nitride with a total thickness between 6 and 8.3 μm. The surface micromachining fabrication process is based on a relatively simple method for the wafer-level formation of freestanding nanoporous alumina membranes, featuring extremely narrow cylindrical nanopores with diameters in the range of 10–20 nm and aspect ratio exceeding 100. The package impact on an encapsulated coplanar waveguide (CPW) is minimized (up to 67 GHz) by locally narrowing the RF feedthroughs underneath the package anchor. Furthermore, the hermeticity of various package configurations is evaluated by means of optical monitoring of the cap deflection under different environmental conditions, including short-term exposure to helium and long-term (up to 14 months) exposure to air. Finally, a comprehensive investigation of the reliability of the thin film packages and their compatibility with high-pressure epoxy overmolding 1-level packaging is discussed.

In this work a calibrated 3D finite element model (FEM) was used to broaden the understanding of mechanical stress induced by chip package interaction (CPI). This was done by varying geometric design parameter, such as μbump pitch, μbump array size, space between μbumps array and die thickness, and investigate their effect on mechanical stress build up during the stacking processing of 2 IC's dies. This work also includes an analyze of the use of a soft material integrated between the stacked dies to act as stress buffer and consequently reduce CPI induced stress. Looking for an alternative to optimize packaging process, thermo compression bonding (TCB) where the die is pre-heated before to be assemble to a laminate has also been investigated. The results showed that the most critical design parameter for stress, between those studied in this work, is the interconnect μbumps pitch. The results also showed a significant reduction in mechanical stress in the Si die when a buffer layer is used between the stacked dies. Last but not least, pre-heating a Si die before attaches to laminate substrate reduces the thermal strain of the laminate consequently reduces stress induced by packaging.

In this paper, we present the design of a passive test chip with thermal test structures in the Metal 1 layer of the back-end of Line (BEOL) for the experimental thermal characterization of the inter-die thermal resistance of wafer-pairs fabricated by hybrid Cu/dielectric wafer-to-wafer bonding. The thermal test structures include heater elements and temperature sensors. The measurement data is combined with a modeling study to extract the thermal resistance of the bonded interface for the fabricated bonded wafer pair. The extracted thermal resistance of the die-die interface created by hybrid wafer-to-wafer bonding is compared to literature data on µbump stacking. The low thermal resistance of the thin bonded dielectric interface indicates that hybrid Cu/dielectric bonding is a promising technology to create 3D chip stacks with a low thermal die-to-die resistance.

Next generation “More than Moore” integrated circuit (IC) technology will rely increasingly on the benefits attributable to advanced packaging ( www.itrs.net [1] ). In these increasingly heterogeneous systems, the individual semiconductor die is becoming much thinner (25 to 50 μm, typically) and multiple dies can be stacked upon each other. It is difficult to assess non-destructively, non-invasively and in situ the stress or warpage of the semiconductor die inside these chip packages and conventional approaches tend to monitor the warpage of the package rather than the die. This paper comprises an account of a relatively new technique, which we call B-Spline X-Ray Diffraction Imaging (B-XRDI) and its application, in this instance, to the non-destructive mapping of Si semiconductor die lattice misorientation inside wire bonded encapsulated Low-profile Fine-pitch Ball Grid Array (LFPGA) packages. B-XRDI is an x-ray diffraction imaging technique which allows the user to reconstruct from a series of section x-ray topographic images a full profile of the warpage of the silicon semiconductor die inside such a chip package. There is no requirement for pre-treatment or pre-processing of the chip package and we show that synchrotron-based B-XRDI mapping of wafer warpage can be achieved with angular tilt resolutions of the order of 50 μrad ≈ 0.003° in times as short as 9–180 s (worst case X–Y spatial resolution = 100 μm) for a full 8.7 mm × 8.7 mm semiconductor die inside the fully encapsulated LFBGA packages. We confirm the usefulness of the technique by correlating our data with conventional warpage measurements performed by mechanical and interferometric profilometry and finite element modelling (FEM). We suggest that future developments will lead to real-time, or near real-time, mapping of thermomechanical stresses during chip packaging processes, which can run from bare wafer through to a fully encapsulated chip package.

In this paper, we present the experimental characterization of three-dimensional (3D) packages using a dedicated stackable test chip. An advanced complementary metal oxide silicon (CMOS) test chip with programmable power distribution has been designed, fabricated, stacked, and packaged in molded and bare die 3D packages. The packages have been experimentally characterized in test sockets with and without cooling and soldered to the printed circuit board (PCB). Using uniform and localized hot spot power distribution, the thermal self-heating and thermal coupling resistance and the lateral spreading in the 3D packages have been studied. Furthermore, the measurements have been used to characterize the thermal properties of the die–die interface and to calibrate a thermal model for the calculation of equivalent properties of underfilled μbump arrays. This model has been applied to study the tradeoff between the standoff height reduction and the underfill thermal conductivity increase in order to reduce the interdie thermal resistance.

Several SiGe Micro–Electro Mechanical (MEM) double clamped beam resonators with different lengths were chemically functionalized and electrically measured. The impact of each functionalization step, including oxidation, silanization, immobilization and blocking, on the resonators’ performance was studied. The resonance frequency of these resonators was measured before and after each processing step. The oxidation and blocking steps were found to have the greatest impact on the resonator’s performance. Fragility of long beam resonators is investigated.

In this paper, we present test structures and measurement techniques that enable the extraction of the significance of the thermal-mechanical stress in 3D-stacked integrated circuit technology. Heaters and integrated diodes have been used to determine the impact of hotspots in 3-D systems. The results obtained showed that in 3-D case, the peak temperature of a hotspot is three times higher compared to a traditional 2-D system. For the characterization of through silicon vias (TSVs)-induced stress and its impact on analog metal-oxide semiconductor (MOS) devices, a 10-bit current steering digital-to-analog converter (DAC) test structure is utilized. The DAC has been optimized to detect ion changes down to 0.5% due to TSV proximity, TSV orientation, thermal hotspots, and wafer thinning or stacking process. The results obtained from stand-alone short-channel MOS devices and the DAC structure clearly indicate the impact of TSV proximity and TSV orientation on the carrier mobility of nearby transistors.

This paper presents the process challenges for the fabrication of 0-level packages using chip capping with through silicon via's (TSV) in the capping chip/wafer. The key processing challenges addressed include the fabrication of TSVs on capping wafers that are thinned down to 100μm and further, the Cu/Sn/Cu diffusion soldering to make an intermetallic bond for the chip capping. Integration of the TSVs on the cap wafer enables the vertical interconnection, thus making the package with a small form factor and readiness for 3D integration. The Cu/Sn/Cu bond and seal process provides a hermetic package and at the same time provide electrical connection between the cap and the device wafer. Adequate processing conditions are proposed.

Thermal compression bonding (TCB) process in combination with a pre-applied underfill material has been developed and investigated for assembling 20 μm pitch Sn-based micro bumps. It is found bonding force has a profound impact on the joint formation behavior. A low bonding force produces bump joints with heavier underfill entrapment and incompletely reacted solder. A higher bonding force leads to more solder squeezing-out, leaving a thin and completely reacted inter-metallic compound (IMC) layer in the joints. Electrical measurement of the daisy chains on the as-bonded chips does not reveal any significant difference between the samples made with different bonding forces. The reliability of the two types of joints were further studied in two post-bonding tests, namely the resistance measurement of daisy chains at an elevated temperature and stack-level thermo-cycling test. Both tests show a better reliability performance from the bump joints with less underfill entrapment and completely reacted IMC layer.

In this paper, we present the experimental characterization of 3D packages using a dedicated stackable test chip. An advanced CMOS test chip with programmable power distribution has been designed, fabricated, stacked and packaged in molded and bare die 3D packages. The packages have been experimentally characterized in test sockets with and without cooling, and soldered to the PCB. Using uniform and localized hot spot power distribution, the thermal self-heating and thermal coupling resistance and the lateral spreading in the 3D packages have been studied. Furthermore, the measurements have been used to characterize the thermal properties of the epoxy mold compound and the die-die interface and to calibrate a thermal model for the calculation of equivalent properties of underfilled μbump arrays. This model has been applied to study the trade-off between the stand-off height reduction and the underfill thermal conductivity increase in order to reduce the inter die thermal resistance.