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The synergistic effects of the total ionizing dose (TID) and analog transient radiation effects in electronics (ATREE) in vertical NPN (VNPN) bipolar transistor were explored experimentally. The technology computer-aided design (TCAD) simulation was also accomplished to analyze the impact of TID-induced positive charge and Si/SiO2 interface traps on the primary and secondary photocurrents of the transistor under the transient ionizing radiation environments. The results indicate that the TID-ATREE synergistic effects in the VNPN bipolar transistor include faster decrease of secondary photocurrents and shorter transient durations across various dose rates. TID-induced Si/SiO2 interface traps enhance the carrier recombination, decreasing the number of electrons emitted from the emitter to the base region near the oxide layer and the number of carriers collected by the collector contact, which is the dominant cause of the synergistic effects, however, TID-induced positive charge in the oxide layer has little influence.

Latch up (LU), an inherent destructive phenomenon owning to P-N-P-N structure in bulk Complementary Metal-Oxide -Silicon (CMOS) circuits, is highly sensitive to pulsed irradiation. A criterion for LU is concluded, and the impact of total ionizing dose (TID) on LU criterion is discussed. In the progress of accumulating TID, generated oxide trapped charges and interface states enhance surface recombination in the base of the parasitic bipolar junction transistor (PBJT), leading to increase of the base recombination current; and the trapped charges in the shallow trench isolation (STI) can also increase leakage current. In spite of hindering effect of the base recombination in PBJTs to LU, the STI leakage current plays a dominant role to gain sensitivity of LU. Experimental results confirm the fact that TID can lower the dose rate threshold for LU. For instance, the threshold in the device with doses 150 krad(Si) is nearly 50% lower than that in the pristine device. Simulations in SPICE and Sentaurus are conducted, and the results agree with that of experiments.

several types of Low drop-out (LDO) regulator, manufactured in different technologies, are irradiated in the transient radiation environment. The experimental results show that outputs of all of LDOs are disrupted when irradiated. For the LDO manufactured in the complimentary metal-oxide -semiconductor (CMOS) technology, latch up (LU) occurs at the lower dose rate due to the parasitical PNPN structure, and the output voltage drops to zero. For the LDOs manufactured in the bipolar technology, if based on the two bipolar junction transistors (BJTs) band gap reference source, the output voltages are pulled up to the higher levels. If based on the three BJTs band gap reference source, the output voltages are pulled down to the lower levels. However, the output voltage disturbances of the bipolar LDOs recover in several micro minutes. In addition, different types of load result in different radiation responses of LDOs.

This paper investigates the core voltage’s reduction of electronics induced by transient ionizing radiation and how it influences TREE (Transient Ionizing Radiation Effect of Electronics) on SRAM. 6T memory cell of 40nm SRAM was constructed in TCAD and the dose-rate upset threshold of it was 1.5×1011Gy(Si)/s when working at nominal core voltage. However, the transient ionizing radiation experiment of 40nm SRAM carried out on “QiangGuang-I” accelerator indicated that the dose-rate upset threshold of the whole SRAM chip was1.0×107 Gy(Si)/s. And the simulation results indicated that the reduction of memory cell’s core voltage would reduce the dose-rate upset threshold significantly as the memory cell’s SNM (Static Noise Margin) decreases with the reduction of memory cell’s core voltage. As there is LDO (Low Dropout Regulator) inside SRAM for conversion of voltage from I/O to core, we also did the transient ionizing radiation experiment of LDO and the experimental results showed that the output voltage of LDO would decrease during transient ionizing radiation which verified the probability of the reduction of memory cell’s core voltage during transient ionizing radiation. Combined with the experiment and simulation results, it can be assumed that the reduction of core voltage during radiation is a main reason causing SRAM upset.

Transient ionization radiation experiment is carried out with the "Qiang Guang-I" accelerator in Northwest Institute of Nuclear Technology to investigate the dose rate damage pattern of 0.18μm SRAM (Static Random Access Memory). The experiment result shows that the transient ionization radiation damage pattern of 0.18μm SRAM (static random access memory) is mainly because of the photocurrent generated in memory cell flowing into the power bus which reduces core voltage of memory cell during transient radiation. Spice is also used to demonstrate the reliability between the transient ionization radiation sensitivity and the reduction of core voltage which can reduce the static noise margin of the SRAM memory cell.

Total ionizing dose (TID) can cause the threshold voltage of complementary metal oxide semiconductor (CMOS) transistors to shift backward and the current gain of the parasitic triode to degrade; these two factors will compete while devices accumulating TID expose to transient ionizing irradiation, and the data status depends on the dominant one. Micrometer (CD4007) and sub-micrometer (IDT71256) CMOS devices were investigated on the synergistic effects of TID and transient ionizing irradiation. The results reveal that the current gain degradation induced by TID, for CD4007, plays a significant role; whereas the shrink of the static noise margin (SNM) induced by TID, for IDT71256, is the dominant factor and the influence of the parasitic transistor can be ignored. The reasons are sub-micrometer devices have the thinner gate oxide, resulting in the current gain degradation induced by TID not evident; and the collection volume of photocurrent is too small to generate enough primary photocurrent for driving the parasitic transistor on. In sum, the synergistic effects of TID and transient ionizing irradiation are evident in large-scale devices, while not evident in small-scale devices.

The physical reason behind the much more rapid short-term annealing progress in the presence of electrons in P-type silicon irradiated by pulse neutrons is investigated. Continuum equations coupled with defect reactions are used for the numerical simulation on the temporary evolutions of defects at different electron injection ratios. It is indicated that electron injections can significantly accelerate the creations of boron and carbon interstitials, but may have little influence on the creation of the vacancy-oxygen complex. The calculations on the relative concentrations of interstitials and vacancies in different charge states via the electron injection ratio show that more and more interstitials in the doubly positive charge state change into neutral ones, and neutral vacancies are always dominant with an increase in the electron concentration. The thermal diffusion coefficient of neutral interstitials is much larger than the ones of interstitials in other charge states. As a consequence, normal ionization enhanced diffusion for interstitials in the presence of electrons can significantly accelerate the short-term annealing progress in P-type silicon. Ionization enhanced diffusion coefficients for interstitials due to athermal diffusion are further estimated using the Bourgoin mechanism, and results indicate that the diffusion coefficients of positively charged interstitials are improved by several orders of magnitude when compared to their corresponding thermal diffusion coefficients. However, the production of boron and carbon interstitials is only accelerated by about one order of magnitude, which would be ascribed into such large thermal diffusion coefficients of neutral interstitials.

This paper presents experimental results of transient gamma irradiation effects on two kinds of circuits. One is a two-stage circuit consisting of a bipolar power device L7805CV and a bulk complementary metal-oxide-semiconductor (CMOS) device IDT6116, the other is a two-stage circuit consisting of a bipolar power device L7805CV and the equivalent circuit of the parasitic P-N-P-N structure in bulk CMOS devices. The results show that the L7805CV’s output interruption after transient irradiation can prevent latch-up from occurring on the second stage circuit. The demanded minimum interruption duration to avoid latch-up varies with dose rate, and this is confirmed by the experimental results.

This paper presents the experimental results of a combined irradiation environment of neutron and gamma rays on 80C196KC20, which is a 16-bit high performance member of the MCS96 microcontroller family. The electrical and functional tests were made in three irradiation environments: neutron, gamma rays, combined irradiation of neutron and gamma rays. The experimental results show that the neutron irradiation can affect the total ionizing dose behaviour. Compared with the single radiation environment, the microcontroller exhibits considerably more severe degradation in neutron and gamma ray synergistic irradiation. This phenomenon may cause a significant hardness assurance problem.

Linear response theory was used to predict threshold-voltage shifts for CC4007-NMOS device at dose rates of 0.1, 2.3, 44 and 91rad(Si)/s. These predictions were compared with the threshold-voltage shifts obtained after 60Co irradiations actually performed at these dose rates, and the agreement is excellent. Also, we use the linear response theory to predict the response of CC4007-NMOS device during radiation and 25℃ annealling for high and low-dose-rates. According to the predictions, under the same conditions of radiation and annealling, the threshold-voltage shifts caused by high dose-rate irradiation after room temperature annealling were equal to that by low-dose-rate irradiation within the limit of error, but the total times for both were the same. Finally, the failure doses for CC4007-NMOS device at different dose rates of irradiation were predicted also using the linear response theory.

In this paper the characteristics of isothermal and isochronal annealing for post-radiated MOS transistor were studied. The results show that 100℃ isothermal a nnealing is the most effective treatment, while the time of isochronal annealing is the shortest. Secondly, the recovery of threshold voltage under the +5V bias is the fastest and biggest, compared to that under 0V and float bias. These predictied results by using isochronal annealing data were compared with the ex periment curve obtained from isothermal annealing, and the agreement is good.