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A multiscale technology computer-aided design (TCAD) simulation methodology is presented to calculate the intrinsic transit time of InP double heterojunction bipolar transistors (DHBTs). A 2-D hyd-rodynamic (HD) simulator is employed to produce the dc characteristics and electrostatic potentials of the selected devices. Utilizing the cuts of the obtained potential profiles as inputs, a 1-D full-band, atomistic quantum transport (QT) solver is then deployed to determine the ballistic electronic transport properties of these components. The transit times of DHBTs based on InGaAs/InP and GaAsSb/InP technologies are finally investigated with the proposed approach. Good qualitative agreements are observed with the experimental measurements. The observed underestimations of the experimental transit times are justified with the physics-based compact model HiCuM, thus providing a basis for structure and performance optimizations toward real terahertz transistors. [ABSTRACT FROM AUTHOR]

This paper presents a new physical compact model for interface state creation due to hot-carrier degradation in advanced SiGe heterojunction bipolar transistors (HBTs). An analytical model for trap density is developed through an accurate solution of the rate equation describing generation and annihilation of interface traps. The analytical aging law has been derived and implemented in terms of base recombination current parameters in HiCuM compact model and its accuracy has been validated against results from long-term aging tests performed close to the safe-operating areas of various HBT technologies. The model implementation uses a single additional node, alike previous implementations, thereby preserving its simplicity, yet improving the accuracy and the physical basis of degradation. [ABSTRACT FROM AUTHOR]

In this paper, we report a physics-based compact model for monolayer graphene field-effect transistors (m-GFETs) based on the 2-D Density of States of monolayer graphene and the drift-diffusion equation. Furthermore, the Ward-Dutton charge partitioning scheme has been incorporated to the model extending its capabilities to AC and transient simulations. The model has been validated through comparison with DC and RF measurements from two different long-channel m-GFET technologies. Moreover, values of parasitic elements included in the model are extracted from measurements on dedicated test structures and verified through electromagnetic simulations (EM). Finally, an EM-SPICE co-simulation has been carried out to assess the applicability of the developed m-GFET model for the design of “balun” circuits. [ABSTRACT FROM PUBLISHER]

We present and validate a physics-based model to describe the underlying mechanisms of hot-carrier degradation in bipolar transistors. Our analysis is based on a deterministic solution of the coupled system of Boltzmann transport equations for electrons and holes. The full-band transport model provides the energy distribution functions of the charge carriers interacting with the passivated Si–H bonds along the oxide interface. The simulation results assert the dominant role of hot holes along the emitter–base spacer oxide interface in the long-term degradation of an n-p-n SiGe heterojunction bipolar transistor under low and high-current conditions at the border of the safe-operating area. The interface trap density is calculated by incorporating an energy driven paradigm for the microscopicmechanisms of defect creation into a reaction-limitedmodelwith dispersive reaction rates. These interface traps increase the forward-mode base current via Shockley–Read–Hall recombination and degrade the overall device performance. The Gummel characteristics of a degraded device and time evolution of the excess base current for different stress conditions are verified versus the experimental data obtained for a state-of-the-art toward-terahertz SiGe HBT. [ABSTRACT FROM AUTHOR]

In this paper, an accurate compact model based on physical mechanisms for dual-gate bilayer graphene FETs is presented. This model is developed based on the 2-D density of states of bilayer graphene and is implemented in Verilog-A. Furthermore, physical equations describing the behavior of the source and drain access regions under back-gate bias are proposed. The accuracy of the developed large-signal compact model has been verified by comparison with measurement data from the literature. [ABSTRACT FROM PUBLISHER]

In this paper, we report on the development of a versatile compact model for graphene FETs (GFETs). Aging studies have been performed on the GFETs via bias stress measurements and aging laws were implemented in the compact model, including failure mechanisms in the GFETs. The failure mechanisms are identified to be originated from the generation of traps and interface states causing a shift in the transfer characteristics and mobility degradation, respectively. For the development of the aging compact model, the trap density is implemented in the prestress compact model to modulate the channel potential. Moreover, the interface state generation is implemented to reflect on the modification of the source/drain access region charges. The implemented aging model is compared with reported bias-stress measurement results as well as the aging measurements carried out on chemical vapor deposition GFETs which show a very good agreement. [ABSTRACT FROM AUTHOR]

A compact model for dual-gate carbon nanotube FETs (dual-gate CNTFETs) is presented. This compact model includes the most significant mechanisms present in dual-gate CNTFETs such as the Schottky barrier at the metallic–nanotube interface, the band-to-band tunneling effect, and quasi-ballistic transport through the Landauer equation. An innovative logic circuit using the dual-gate CNTFET model is presented. Finally, the logic cell operation is analyzed while taking into account some of the CNT technological dispersions. [ABSTRACT FROM PUBLISHER]

A compact model for dual-gate (DG) carbon-nanotube field-effect transistors (FETs) (CNTFETs) is presented. This compact model includes the most significant mechanisms present in DG CNTFETs such as the Schottky barrier at the metal–nanotube interface, charge and electrostatic modeling, the band-to-band tunneling effect, and quasi-ballistic transport through the Landauer equation. Also, the structure of our DG CNTFET model and its associated equations are versatile and can be used to model different kinds of 1-D ballistic DG FETs, such as graphene-nanoribbon-based devices. Furthermore, this compact model is compared with measurements from two different technologies. Finally, a simple ring oscillator circuit has been simulated using ten identical devices. [ABSTRACT FROM AUTHOR]

This paper presents a computationally efficient physics-based compact model for the Schottky barrier (SB) carbon nanotube field-effect transistor (CNTFET). This compact model includes a new analytical formulation of the channel charge, taking into account the influence of the source and drain SBs. Compact model simulation results ( I–V characteristic and channel density of charge) as well as Monte Carlo simulation results, which are provided by a recent work, will be given and compared to each other and also to experimental data to validate the used approximations. Good agreement is observed over a large range of gate and drain biases. Furthermore, a scaling study is presented to examine the impact of technological parameters on the device figure of merit. Then, for the assessment of the SB on circuit performances, traditional logical circuits are designed using the SB-CNTFET compact model, and results are compared with a conventional CNTFET with zero-SB height. Finally, exploiting the particular properties of SB-CNTFETs, a three-valued static memory that is suitable for high density integration is presented. [ABSTRACT FROM AUTHOR]