1. Low-delay FPGA-based implementation of finite field multipliers
- Author
-
José Luis Imaña
- Subjects
Polynomial basis ,Finite field ,Binary number ,Multiplication ,Multiplier (economics) ,Field (mathematics) ,Coding theory ,Electrical and Electronic Engineering ,Trinomial ,Arithmetic ,Hardware_ARITHMETICANDLOGICSTRUCTURES ,Inteligencia artificial ,Mathematics - Abstract
Arithmetic operations over binary extension fields $GF(2^{m})$ have many important applications in domains such as cryptography, code theory and digital signal processing. These applications must be fast, so low-delay implementations of arithmetic circuits are required. Among $GF(2^{m})$ arithmetic operations, field multiplication is considered the most important one. For hardware implementation of multiplication over binary finite fields, irreducible trinomials and pentanomials are normally used. In this brief, low-delay FPGA-based implementations of bit-parallel $GF(2^{m})$ polynomial basis multipliers are presented, where a new multiplier based on irreducible trinomials is given. Several post-place and route implementation results in Xilinx Artix-7 FPGA for different $GF(2^{m})$ finite fields are reported. Experimental results show that the proposed multiplier exhibits the best $delay$ , with a delay improvement of up to 4.7%, and the second best $Area\times Time$ complexities when compared with similar multipliers found in the literature.
- Published
- 2021