Search

Processing-in-memory (PIM) seeks to eliminate computation/memory data transfer using devices that support both storage and logic. Stateful logic techniques such as IMPLY, MAGIC and FELIX can perform logic gates within memristive crossbar arrays with massive parallelism. Multiplication via stateful logic is an active field of research due to the wide implications. Recently, RIME has become the state-of-the-art algorithm for stateful single-row multiplication by using memristive partitions, reducing the latency of the previous state-of-the-art by ${5.1\times }$. In this brief, we begin by proposing novel partition-based computation techniques for broadcasting and shifting data. Then, we design an in-memory multiplication algorithm based on the carry-save add-shift (CSAS) technique. Finally, we develop a novel stateful full-adder that significantly improves the state-of-the-art (FELIX) design. These contributions constitute MultPIM, a multiplier that reduces state-of-the-art time complexity from quadratic to linear-log. For 32-bit numbers, MultPIM improves latency by an additional ${4.2\times }$ over RIME, while even slightly reducing area overhead. Furthermore, we optimize MultPIM for full-precision matrix-vector multiplication and improve latency by ${25.5\times }$ over FloatPIM matrix-vector multiplication. [ABSTRACT FROM AUTHOR]

Y-Flash memristors utilize the mature technology of single polysilicon floating gate nonvolatile memories. It can be operated in a two-terminal configuration similar to the other emerging memristive devices, e.g., resistive random-access memory and phase-change memory. Fabricated in production complementary metal-oxide-semiconductor technology, Y-Flash memristors allow excellent reproducibility reflected in high neuromorphic products yields. Working in the subthreshold region, the device can be programmed to a large number of fine-tuned intermediate states in an analog fashion and allows low readout currents (1 nA ∼ 5 μA). However, currently, there are no accurate models to describe the dynamic switching in this type of memristive device and account for multiple operational configurations. In this paper, we provide a physical-based compact model that describes Y-Flash memristor performance in both DC and AC regimes and consistently describes the dynamic program and erase operations. The model is integrated into the commercial circuit design tools and is ready to be used in applications related to neuromorphic computation. [ABSTRACT FROM AUTHOR]

Computationally intensive neural network applications often need to run on resource-limited low-power devices. Numerous hardware accelerators have been developed to speed up the performance of neural network applications and reduce power consumption; however, most focus on data centers and full-fledged systems. Acceleration in ultra-low-power systems has been only partially addressed. In this article, we present multiPULPly, an accelerator that integrates memristive technologies within standard low-power CMOS technology, to accelerate multiplication in neural network inference on ultra-low-power systems. This accelerator was designated for PULP, an open-source microcontroller system that uses low-power RISC-V processors. Memristors were integrated into the accelerator to enable power consumption only when the memory is active, to continue the task with no context-restoring overhead, and to enable highly parallel analog multiplication. To reduce the energy consumption, we propose novel dataflows that handle common multiplication scenarios and are tailored for our architecture. The accelerator was tested on FPGA and achieved a peak energy efficiency of 19.5 TOPS/W, outperforming state-of-the-art accelerators by 1.5× to 4.5×. [ABSTRACT FROM AUTHOR]

In-memory processing can dramatically improve the latency and energy consumption of computing systems by minimizing the data transfer between the memory and the processor. Efficient execution of processing operations within the memory is therefore, a highly motivated objective in modern computer architecture. This article presents a novel automatic framework for efficient implementation of arbitrary combinational logic functions within a memristive memory. Using tools from logic design, graph theory and compiler register allocation technology, we developed synthesis and in-memory mapping of logic execution in a single row (SIMPLER), a tool that optimizes the execution of in-memory logic operations in terms of throughput and area. Given a logical function, SIMPLER automatically generates a sequence of atomic memristor-aided logic (MAGIC) NOR operations and efficiently locates them within a single size-limited memory row, reusing cells to save area when needed. This approach fully exploits the parallelism offered by the MAGIC NOR gates. It allows multiple instances of the logic function to be performed concurrently, each compressed into a single row of the memory. This virtue makes SIMPLER an attractive candidate for designing in-memory single instruction, multiple data (SIMD) operations. Compared to the previous work (that optimizes latency rather than throughput for a single function), SIMPLER achieves an average throughput improvement of 435 ×. When the previous tools are parallelized similarly to SIMPLER, SIMPLER achieves higher throughput of at least 5 ×, with 23 × improvement in area and 20 × improvement in area efficiency. These improvements more than fully compensate for the increase (up to 17% on average) in latency. [ABSTRACT FROM AUTHOR]

Memristor-aided logic (MAGIC) is a technique for performing in-memory computing using memristive devices. The design of a MAGIC NOR gate has been described in detail, and it serves as the basic building block for several processing-in-memory architectures. However, the input stability of the MAGIC NOR gate forces a limitation on the threshold voltages: the magnitude of the set voltage must be higher than the magnitude of the reset voltage. Unfortunately, many of the current leading resistive switching technologies, particularly, valence change memory (VCM), have the opposite ratio between the threshold voltages. In this article, we experimentally demonstrate the undesirable effects of input instability. Furthermore, we introduce three new MAGIC gates for devices with low set-to-reset voltage ratios and experimentally demonstrate their robust operation using Pt/Ta2O5/W/Pt devices. The three gates, combined with constant values, are functionally complete and are demonstrated as building blocks for in-memory logic on VCM devices. [ABSTRACT FROM AUTHOR]

Cytomorphic engineering attempts to study the cellular behavior of biological systems using electronics. As such, it can be considered analogous to the study of neurobiological concepts for neuromorphic engineering applications. To date, digital and analog translinear electronics have commonly been used in the design of cytomorphic circuits; Such circuits could greatly benefit from lowering the area of the digital memory via memristive circuits. In this article, we propose a novel approach that utilizes the Boltzmann-exponential stochastic transport of ionic species through insulators to naturally model the nonlinear and stochastic behavior of biochemical reactions. We first show that two-terminal memristive devices can capture the non-linear and stochastic behavior of biochemical reactions. Then, we present the design of several building blocks based on analog memristive circuits that inherently model the biophysical mechanisms of gene expression. The circuits model induction by small molecules, activation and repression by transcription factors, biological promoters, cooperative binding, and transcriptional and translational regulation of gene expression. Finally, we utilize the building blocks to form complex mixed-signal networks that can simulate the delay-induced oscillator and the p53-mdm2 interaction in the cancer signaling pathway. Our approach can provide a fast and simple emulative framework for studying genetic circuits and arbitrary large-scale biological networks in systems and synthetic biology. Some challenges may be that memristive devices with frequent learning and programming do not have the same longevity as traditional transistor-based electron-transport devices, and operate with significantly slower time constants, which can limit emulation speed. [ABSTRACT FROM AUTHOR]

The emerging spin-transfer torque magnetic tunnel junction (STT-MTJ) technology exhibits interesting stochastic behavior combined with small area and low operation energy. It is, therefore, a promising technology for security applications, specifically the generation of random numbers. In this paper, STT-MTJ is used to construct an asynchronous true random number generator (TRNG) with low power and a high entropy rate. The asynchronous design enables the decoupling of the random number generation from the system clock, allowing it to be embedded in low-power devices. The proposed TRNG is evaluated by a numerical simulation, using the Landau–Lifshitz–Gilbert (LLG) equation as the model of the STT-MTJ devices. Design considerations, attack analysis, and process variation are discussed and evaluated. We show that our design is robust to process variation, thus achieving an entropy generating rate between 99.7 and 127.8 Mb/s with 6–7.7 pJ per bit for 90% of the instances. [ABSTRACT FROM AUTHOR]

Memristors have gained increasing interest recently as emerging memory technologies. Their unique ability to perform logic operations within the memory makes them even more attractive. MAGIC NOR is one such logic gate that can be integrated within memristive memory cells, thus opening possibilities for real in-memory computing. This paper explores the integration of MAGIC NOR gates within large-scale memory crossbar arrays. We evaluate both analytically and numerically different non-ideality parameters that influence the logic gate performance. First, we investigate the effect of parasitic resistance and capacitance within the memory array. Then, process and device variations are considered and modeled, as well as environmental conditions such as temperature and power supply variations. These non-idealities are formulated in the form of process corners that enable designers to estimate the effect of variations on their design in worst case scenarios, similar to the manner in which such effects are estimated in CMOS-based VLSI design. [ABSTRACT FROM AUTHOR]

In this paper, a scalable lumped model that accurately predicts the steady-state high-frequency behavior of nanoscale RF memristive devices is presented. The model is described 1) analytically by a set of closed-form equations that determine the parameters based on the device physical structure, allowing for optimized circuit design and performance through structure modifications, and 2) numerically to fit the model parameters to experimental data, allowing for evaluation of the accuracy of the model. This model is, to the best of our knowledge, the first lumped RF memristor model that includes device parasitics obtained from empirical measurements reported in the literature. Results show that the model is reasonably accurate, with 9.6% and 13% relative RMS error for the on-state magnitude and phase, respectively. Furthermore, we propose three topologies (series, shunt, and series-shunt) of nonvolatile single-pole double-throw switches using our lumped RF memristor model. The series and shunt topologies are single-voltage-controlled, while the series-shunt requires two control signals. Simulation results of these topologies exhibit low insertion loss and high isolation (below 0.25 dB and over 63 dB, respectively). The added nonvolatility and nanoscale size will result in reduced power consumption and higher density devices. [ABSTRACT FROM AUTHOR]

Data movement between processing and memory is the root cause of the limited performance and energy efficiency in modern von Neumann systems. To overcome the data-movement bottleneck, we present the memristive Memory Processing Unit (mMPU)-a real processing-in-memory system in which the computation is done directly in the memory cells, thus eliminating the necessity for data transfer. Furthermore, with its enormous inner parallelism, this system is ideal for data-intensive applications that are based on single instruction, multiple data (SIMD)-providing high throughput and energy-efficiency. [ABSTRACT FROM AUTHOR]

Summary: Using memristive devices within a crossbar array could pave the way for memories with higher density and speed than state‐of‐the‐art Flash memory, while maintaining relatively low energy. However, memristive crossbar arrays have great difficulty distinguishing logical states because of sneak path currents. The row grounding technique eliminates the sneak path effect, allowing reliable sampling of the memristor state. In this paper, we analyze the row grounding technique and propose several methods and constraints for the design of memristive crossbar arrays. When the row grounding technique is used for these arrays, our analysis shows that increasing the number of rows can help reduce read latency and energy, in contrast to the case of capacitive memory arrays. Simulation results confirm the theoretical analysis proposed in this paper. Copyright © 2017 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

In a memristor crossbar array, functioning as a memory array, a memristor is positioned on each row–column intersection, and its resistance, low or high, represents two logical states. The state of every memristor can be sensed by the current flowing through the memristor. In this paper, we study the sneak path problem in crossbar arrays, in which current can sneak through other cells, resulting in reading a wrong state of the memristor. Our main contributions are modeling the error channel induced by sneak paths, a new characterization of arrays free of sneak paths, and efficient methods to read the array cells while avoiding sneak paths. To each read method, we match a constraint on the array content that guarantees sneak-path free readout, determine the resulting capacity, and provide an efficient encoder that achieves the capacity. [ABSTRACT FROM PUBLISHER]

Realizing logic operations within passive crossbar memory arrays is a promising approach to enable novel computer architectures, different from conventional von Neumann architecture. Attractive candidates to enable such architectures are memristors, nonvolatile memory elements commonly used within a crossbar, that can also perform logic operations. In such novel architectures, data are stored and processed within the same entity, which we term as memristive memory processing unit (MPU). In this paper, Memristor-Aided loGIC (MAGIC) family is discussed with various design considerations and novel techniques to execute logic within an MPU. We present a novel resistive memory—the transpose memory, which adds additional functionality to the memristive memory, and compare it with a conventional memristive memory. A case study of an adder is presented to demonstrate the design issues discussed in this paper. We compare the proposed design techniques with the memristive IMPLY logic in terms of speed, area, and energy. Our evaluation shows that the proposed MAGIC design is 2.4 $\times$ faster and consumes 66.3% less energy as compared with the IMPLY-based computing for N-bit addition within memristive crossbar memory. Additionally, we compare the proposed design with IMPLY logic family on ISCAS-85 benchmarks, which shows significant improvements in speed (2$\times$) and energy (10 $\times$), with similar area. [ABSTRACT FROM PUBLISHER]

In recent years, memristive technologies, such as resistive random access memory (RRAM), have emerged. These technologies are usually considered as alternates for static RAM, dynamic RAM, and Flash. In this paper, a novel digital circuit, the multistate register, is proposed. The multistate register is different from conventional types of memory, and is used to store multiple data bits, where only a single bit is active and the remaining data bits are idle. The active bit is stored within a CMOS flip flop, while the idle bits are stored in an RRAM crossbar co-located with the flip flop. It is demonstrated that additional states require an area overhead of 1.4% per state for a 64-state register. The use of multistate registers as pipeline registers is demonstrated for a novel multithreading architecture—continuous flow multithreading (CFMT), where the total area overhead in the CPU pipeline is only 2.5% for 16 threads compared with a single thread CMOS pipeline. The use of multistate registers in the CFMT microarchitecture enables higher performance processors (40% average performance improvement) with relatively low energy (6.5% average energy reduction) and area overhead. [ABSTRACT FROM AUTHOR]

Memristors are novel electrical devices used for a variety of applications, including memory, logic circuits, and neuromorphic systems. Memristive technologies are attractive due to their nonvolatility, scalability, and compatibility with CMOS. Numerous physical experiments have shown the existence of a threshold voltage in some physical memristors. Additionally, as shown in this brief, some applications require voltage-controlled memristors to operate properly. In this brief, a Voltage ThrEshold Adaptive Memristor (VTEAM) model is proposed to describe the behavior of voltage-controlled memristors. The VTEAM model extends the previously proposed ThrEshold Adaptive Memristor (TEAM) model, which describes current-controlled memristors. The VTEAM model has similar advantages as the TEAM model, i.e., it is simple, general, and flexible, and can characterize different voltage-controlled memristors. The VTEAM model is accurate (below 1.5% in terms of the relative root-mean-square error) and computationally efficient as compared with existing memristor models and experimental results describing different memristive technologies. [ABSTRACT FROM PUBLISHER]

Associative Processor (AP) combines data storage and data processing, and functions simultaneously as a massively parallel array SIMD processor and memory. Traditionally, AP is based on CMOS technology, similar to other classes of massively parallel SIMD processors. The main component of AP is a Content Addressable Memory (CAM) array. As CMOS feature scaling slows down, CAM experiences scalability problems. In this work, we propose and investigate an AP based on resistive CAM—the Resistive AP (ReAP). We show that resistive memory technology potentially allows scaling the AP from a few millions to a few hundred millions of processing units on a single silicon die. We compare the performance and power consumption of a ReAP to a CMOS AP and a conventional SIMD accelerator (GPU) and show that ReAP, although exhibiting higher power density, allows better scalability and higher performance. [ABSTRACT FROM PUBLISHER]

Memristors are passive components with a varying resistance that depends on the previous voltage applied across the device. While memristors are naturally used as memory, memristors can also be used for other applications, including logic circuits. In this brief, a memristor-only logic family, i.e., memristor-aided logic (MAGIC), is presented. In each MAGIC logic gate, memristors serve as an input with previously stored data, and an additional memristor serves as an output. The topology of a MAGIC nor gate is similar to the structure of a common memristor-based crossbar memory array. A MAGIC nor gate can therefore be placed within memory, providing opportunities for novel non-von Neumann computer architectures. Other MAGIC gates also exist (e.g., and, or, not, and nand) and are described in this brief. [ABSTRACT FROM PUBLISHER]

Memristors are novel devices, useful as memory at all hierarchies. These devices can also behave as logic circuits. In this paper, the IMPLY logic gate, a memristor-based logic circuit, is described. In this memristive logic family, each memristor is used as an input, output, computational logic element, and latch in different stages of the computing process. The logical state is determined by the resistance of the memristor. This logic family can be integrated within a memristor-based crossbar, commonly used for memory. In this paper, a methodology for designing this logic family is proposed. The design methodology is based on a general design flow, suitable for all deterministic memristive logic families, and includes some additional design constraints to support the IMPLY logic family. An IMPLY 8-bit full adder based on this design methodology is presented as a case study. [ABSTRACT FROM AUTHOR]

In-memory computation is one of the most promising features of memristive memory arrays. In this paper, we propose an array architecture that supports in-memory computation based on a logic array first proposed in 1972 by Sheldon Akers. The Akers logic array satisfies this objective since this array can realize any Boolean function, including bit sorting. We present a hardware version of a modified Akers logic array, where the values stored within the array serve as primary inputs. The proposed logic array uses memristors, which are nonvolatile memory devices with noteworthy properties. An Akers logic array with memristors combines memory and logic operations, where the same array stores data and performs computation. This combination opens opportunities for novel non-von Neumann computer architectures, while reducing power and enhancing memory bandwidth. [ABSTRACT FROM AUTHOR]

Memristor-based memory computing has attracted much attention recently. By combining the storability and computability of memristor devices together, the memristor-based in-memory computing could break the so-called von Neumann bottleneck. Logic-in-memory (LIM) aims at implementing any computing task in memory. IMPLY family and MAGIC family are two of the most popular stateful logic families of LIM. The two families have their own respective advantages and disadvantages. However, there is few work combining the two family gates together in a same memristor crossbar. In this paper, we would present X-IMPLY family gates that eliminates the required external resistors of conventional IMPLY family gates. We then show by combining X-IMPLY and MAGIC family gates, the advantages of both logic families are exploited. At last, we evaluate the proposed method on state-of-art benchmarks. The results show, averagely, our method saves more than 15% of cell usage and is more than 22% faster and increases lifetime by more than 41% compared with MAGIC SIMPLER for different size constrains of crossbar row/column. [ABSTRACT FROM AUTHOR]