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The development of novel hardware computing systems and methods has been a topic of increased interest for researchers worldwide. New materials, devices, and architectures are being explored as a means to deliver more efficient solutions to contemporary issues. Along with the advancement of technology, there is a continuous increase in methods available to address significant challenges. However, the increased needs to be fulfilled have also led to problems of increasing complexity that require better and faster computing and processing capabilities. Moreover, there is a wide range of problems in several applications that cannot be addressed using the currently available methods and tools. As a consequence, the need for emerging and more efficient computing methods is of utmost importance and constitutes a topic of active research. Among several proposed solutions, we distinguish the development of a novel nanoelectronic device, called a "memristor", that can be utilized both for storing and processing, and thus it has emerged as a promising circuit element for the design of compact and energy-efficient circuits and systems. The memristor has been proposed for a wide range of applications. However, in this work, we focus on its use in computing architectures based on the concept of Cellular Automata. The combination of the memristor's performance characteristics with Cellular Automata has boosted further the concept of processing and storing information on the same physical units of a system, which has been extensively studied in the literature as it provides a very good candidate for the implementation of Cellular Automata computing with increased potential and improved characteristics, compared to traditional hardware implementations. In this context, this paper reviews the most recent advancements toward the development of Cellular-Automata-based computing coupled with memristor devices. Several approaches for the design of such novel architectures, called "Memristive Cellular Automata", exist in the literature. This extensive review provides a thorough insight into the most important developments so far, helping the reader to grasp all the necessary information, which is here presented in an organized and structured manner. Thus, this article aims to pave the way for further development in the field and to bring attention to technological aspects that require further investigation. [ABSTRACT FROM AUTHOR]

The use of memristors and resistive random access memory (ReRAM) technology to perform logic computations, has drawn considerable attention from researchers in recent years. However, the topological aspects of the underlying ReRAM architecture and its organization have received less attention, as the focus has mainly been on device-specific properties for functionally complete logic gates through conditional switching in ReRAM circuits. A careful investigation and optimization of the target geometry is thus highly desirable for the implementation of logic-in-memory architectures. In this paper, we propose a crossbar-based in-memory parallel processing system in which, through the heterogeneity of the resistive cross-point devices, we achieve local information processing in a state-of-the-art ReRAM crossbar architecture with vertical group-accessed transistors as cross-point selector devices. We primarily focus on the array organization, information storage, and processing flow, while proposing a novel geometry for the cross-point selection lines to mitigate current sneak-paths during an arbitrary number of possible parallel logic computations. We prove the proper functioning and potential capabilities of the proposed architecture through SPICE-level circuit simulations of half-adder and sum-of-products logic functions. We compare certain features of the proposed logic-in-memory approach with another work of the literature, and present an analysis of circuit resources, integration density, and logic computation parallelism. [ABSTRACT FROM PUBLISHER]

The recent discovery of the memristor has renewed the interest for fast arithmetic operations via high-radix numeric systems. In this direction, a conceptual solution for high-radix memristive arithmetic logic units (ALUs) was recently published. The latter combines CMOS circuitry for data processing and a reconfigurable "segmented" crossbar memory block. In this paper we build upon such a conceptual design and propose a 3D extension of the classic crossbar topology via 2T1M cross-points which still permits the parallel creation of partial products for faster multiplication with lower circuit complexity. Furthermore, we present a binary to high-radix data conversion circuit to complement the state-programming module of the previous work. A simulation-based validation of read/write multi-level memory operations from/to the 2T1M 3D memristive crossbar was performed using SPICE and a threshold-type switching model of a bipolar voltage-controlled memristor. Such realization of in-memory computations could lead to faster arithmetic algorithms in future memristive ALUs. [ABSTRACT FROM AUTHOR]

An introduction is presented in which the editor discusses various reports within the issue on topics including memristor models, circuits, and architectures.

Resistive random access memory (ReRAM), referred to as memristor, is an emerging memory technology to potentially replace conventional memories, which will soon be facing serious design challenges related to continued scaling. Memristor-based crossbar architecture has been shown to be the best implementation for ReRAM. However, it faces a major challenge related to the sneak current (current sneak paths) flowing through unselected memory cells, which significantly reduces the voltage read margins. In this paper, five alternative architectures (topologies) are applied to minimize the impact of sneak current; the architectures are based on the introduction of insulating junctions within the crossbar. Simulations that were performed while considering different memory accessing aspects, such as bit reading versus word reading, stored data background distribution, crossbar dimensions, etc., showed that read margins can be increased significantly (up to $4\times $ ) as compared with standard crossbar architectures. In addition, the proposed architectures eliminate the requirement for extra select devices at each cross point and have no operational complexity overhead. [ABSTRACT FROM PUBLISHER]

The recent discovery of the 'modern' memristor has drawn great attention of both academia and industry. Given their favorable performance merits, memristors are expected to play a fundamental role in electronic industry. Modeling of memristive devices is essential for circuit design, and a number of Simulation Program with Integrated Circuit Emphasis (SPICE) models have already been introduced. The common problem in most models is that there is no threshold consideration; hence, only a few address the nonlinear nature of the device. This paper aims to present a SPICE implementation of a threshold-type switching model of a voltage-controlled memristive device that attributes the switching effect to a tunneling distance modulation. Threshold-type switching is closer to the actual behavior of most experimentally realizable memristive systems, and our modeling approach addresses the issue of programming thresholds. Both the netlist and the simple schematic are provided, thus making it easy to comprehend and ready to be used. Compared with other modeling solutions, it involves significantly low-complexity operation under an unlimited set of frequencies, and its simulation results are in good qualitative and quantitative agreement with the theoretical formulation. The proposed model is used to simulate an antiserial memristive switch, proving that it can be efficiently introduced in complex memristive circuits. Copyright © 2013 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

This work focuses on the creation of logic circuits by employing the collective dynamics of assembles of reciprocal memristors. A novel circuit design methodology is described where the computing systems comprise passive memristors interfaced with active CMOS circuitry, working under already known circuit design principles from the CMOS technology. The accuracy and completeness of this straightforward methodology is demonstrated through SPICE simulations which are based on a threshold-type device model for memristors. Overall, this work contributes to the creation of proper methodologies which will enable the development of efficient design flows for circuits and architectures comprising memristors. (© 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [ABSTRACT FROM AUTHOR]

This brief contributes to the design of computational and reconfigurable structures that exploit unique threshold-dependent switching response of single memristors and their compositions. A new logic circuit design paradigm, which assumes parallel processing of input signals, is proposed, along with a methodology for the construction of robust programmable composite memristive switches of variable precision. This methodology is applied to the design of memristive computing circuits. A SPICE simulation-based validation of the proposed circuits and systems is provided. [ABSTRACT FROM AUTHOR]

Abstract: The crossbar architecture is viewed as the most likely path towards novel nanotechnologies which are expected to continue the technological revolution. Memristor-based crossbars for integrating memory units have received considerable attention, though little work has been done concerning the implementation of logic. In this work we focus on memristor-based complex combinational circuits. Particularly, we present a design methodology for encoder and decoder circuits. Digital encoders are found in a variety of electronics multi-input combinational circuits (e.g. keyboards) nowadays, converting the logic level ‘1’ data at their inputs into an equivalent binary code at the output. Their counterparts, digital decoders, constitute critical components for nanoelectronics, mainly in peripheral/interface circuitry of nanoelectronic circuits and memory structures. The proposed methodology follows a CMOS-like design scheme which can be used for the efficient design and mapping of any 2 n ×n (n×2 n ) encoder (decoder) onto the memristor-based crossbar geometry. For their implementation, a hybrid nano/CMOS crossbar type with memristive cross-point structures and available transistors is elaborated, which is a promising solution to the interference between neighboring cross-point devices during access operation. Circuit functionality of the presented encoder/decoder circuits is exhibited with simulations conducted using a simulator environment which incorporates a versatile memristor device model. The proposed design and implementation paradigm constitutes a step towards novel computational architectures exploiting memristor-based logic circuits, and facilitating the design and integration of memristor-based encoder/decoder circuits with nanoelectronics applications of the near future. [Copyright &y& Elsevier]

Over 30 years ago L. Chua proposed the existence of a new class of passive circuit elements, which he called memristors and memristive devices. The unique electrical characteristics associated with them, along with the advantages of crossbar structures, have the potential to revolutionize computing architectures. A well-defined and effective memristor model for circuit design combined with a design paradigm based on well-understood underlying logic design principles would certainly accelerate research on nanoscale circuits and systems. Toward this goal, we propose a memristor crossbar circuit design paradigm in which memristors are modeled using the quantum mechanical phenomenon of tunneling. We use this circuit model to design and simulate various logic circuit designs capable of universal computation. Finally, we develop and present a new design paradigm for memristor-based crossbar circuits. [ABSTRACT FROM PUBLISHER]