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Gallium Nitride (GaN) power devices can offer better switching performance and higher efficiency than Silicon Carbide (SiC) and Silicon (Si) devices in power electronics applications. GaN has extensively been incorporated in electric vehicle charging stations and power supplies, subjected to harsh environmental conditions. Many reliability studies evaluate GaN power devices through thermal stresses during current conduction or pulsing, with a few focusing on high blocking voltage and high humidity. This paper compares GaN-on-Si High-Electron-Mobility Transistors (HEMT) device characteristics under a High Humidity, High Temperature, Reverse Bias (H3TRB) Test. Twenty-one devices from three manufacturers were subjected to 85 °C and 85% relative humidity while blocking 80% of their voltage rating. Devices from two manufacturers utilize a cascade configuration with a silicon metal-oxide-semiconductor field-effect transistor (MOSFET), while the devices from the third manufacturer are lateral p-GaN HEMTs. Through characterization, three sample devices have exhibited degraded blocking voltage capability. The results of the H3TRB test and potential causes of the failure mode are discussed. [ABSTRACT FROM AUTHOR]

We introduce the concept of constant-gate-charge scaling to increase the short-circuit withstand time of SiC power MOSFETs without increasing their ON-state resistance, gate charge, or oxide field. In gate-charge scaling, we scale the oxide thickness and gate drive voltage, keeping the oxide field constant. Short-circuit measurements on 1200 V SiC double-implanted MOSFETs (DMOSFETs) confirm that short-circuit withstand times can be increased by 2– $4\times $ without increasing ON-resistance, simply by reducing the oxide thickness and the gate drive voltage. [ABSTRACT FROM AUTHOR]

Silicon carbide (SiC) is becoming a preferred technology of choice for power dense application compared with silicon (Si). A more comprehensive analysis of the long-term pulsed power reliability of SiC is necessary so that the technology can make the transition commercially. In this article, a testbed is utilized to evaluate research grade 15-kV SiC MOSFETs and 20-kV SiC IGBTs manufactured by Wolfspeed, a Cree Company. A testbed was developed here at Texas Tech University (TTU), Lubbock, TX, USA, to test these two devices. The narrow pulse testbed’s capacitor bank can be charged up to 10 kV and output square waveform pulse up to $2.0~\mu \text{s}$. The waveform has a full-width at half-maximum pulse and is tested at a repetition pulse rate of three seconds. The electrical characteristics of the forward conduction and reverse breakdown of the device under test (DUT) are measured periodically during the experiment. The DUTs were pulsed at different current levels, up to 340 A (1.06 kA/cm2) for the IGBTs and 74 A (296 A/cm2) for MOSFETs, while the electrical device degradation was monitored. This work discusses the results of the long-term pulsed power reliability, failure modes, and their robustness in overcurrent operations of high-power SiC MOSFETs and IGBTs. [ABSTRACT FROM AUTHOR]

Commercialization of 1200-V silicon carbide (SiC) MOSFET has enabled power electronic design with improved efficiency as well as increased power density. High-voltage spikes induced in applications such as solenoid control, solid-state transformer, boost converter, and flyback converter can drive the MOSFET into avalanche mode operation due to high di/dt coupled with parasitic inductance. Avalanche mode operation is characterized by high-power dissipation within the device due to the high voltage and current crossover. This study focuses on the evaluation of two commercially available SiC MOSFETs from different manufacturers, each rated for 1200 V with an ON-state resistance of 80 mΩ, during unclamped inductive switching (UIS) mode operation. To determine device reliability, a decoupled UIS testbed was developed to evaluate the avalanche energy robustness at 22 \,^\circC and 125 \,^\circC during two specific conditions: high current and low energy, and low current and high energy. The SiC MOSFETs were evaluated using a load inductance of 1.42, 5.1, 10.5, and 15.8 mH to understand the effect of current and avalanche energy on device failure. To correlate the experimental results with the failure mechanism, estimated junction temperature and static device characteristics are presented; additionally, MOSFETs were decapsulated to examine the failure sites on the semiconductor die. [ABSTRACT FROM AUTHOR]

SiC MOSFETs are a leading option for increasing the power density of power electronics; however, for these devices to supersede the Si insulated-gate bipolar transistor, their characteristics have to be further understood. Two SiC vertically oriented planar gate D-MOSFETs rated for 1200 V/150 A were repetitively subjected to pulsed overcurrent conditions to evaluate their failure mode due to this common source of electrical stress. This research supplements recent work that demonstrated the long term reliability of these same devices [1]. Using an RLC pulse-ring-down test bed, these devices hard-switched 600 A peak current pulses, corresponding to a current density of 1500 A/cm2. Throughout testing, static characteristics of the devices such as $B_{{\rm VDSS}}$ , $R_{{\rm DS}({\rm on})}$, and $V_{{\rm GS}({\rm th})}$ were measured with a high power device analyzer. The experimental results indicated that a conductive path was formed through the gate oxide; TCAD simulations revealed localized heating at the SiC/SiO2 interface as a result of the extreme high current density present in the device's JFET region. However, the high peak currents and repetition rates required to produce the conductive path through the gate oxide demonstrate the robustness of SiC MOSFETs under the pulsed overcurrent conditions common in power electronic applications. [ABSTRACT FROM PUBLISHER]

The high-voltage silicon carbide MOSFET is a state-of-the-art solution for increasing power density and efficiency in power electronics; nonetheless, a full-scope of failure modes during extreme operating condition has not been established. Past efforts evaluated short-circuit capability of 10-kV silicon carbide MOSFET, however, in this manuscript, the single-pulse avalanche mode operation of a research-grade 10-kV/10-A silicon carbide MOSFET is explored for the first time. A decoupled unclamped inductive circuit was selected for evaluation, and avalanche energy was increased until catastrophic failure occurred. The maximum tolerable avalanche energy was measured to be 2.84 J corresponding to an energy density of 8.8 J·cm −2 . This result was compared with 1.2-kV silicon carbide MOSFETs to evaluate device robustness. Post failure analysis included: estimation of junction temperature, scanning electron microscopy, and focused ion beam cut. Peak junction temperature of 1010 °C was estimated using a thermal RC model and measurement results suggested gate degradation as the primary mechanism responsible for device destruction. Microscopy of the device validated gate failure which occurred at, or beneath, the gate metallization. A narrow cavity with-in the failure region was discovered during failure analysis and is hypothesized to have protruded the epitaxial region of the semiconductor. [ABSTRACT FROM AUTHOR]