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Device operations of the monolayer molybdenum disulfide (MoS2) based FETs are analyzed using first principle atomistic simulations, revealing the similarity of device operation in monolayer and Si transistors. Taylor expansion is employed on Si potential modeling framework, assuming an ultra-thin (delta function like) channel for MoS2 devices. The method accurately reproduces the gate control of the MoS2 FETs in both long channel and short channel transistors including the subthreshold characteristics. First principle simulations verify the developed model, suggesting that the monolayer MoS2 MOSFET can be modeled by extending Si MOSFET equations with incorporating material parameters. [ABSTRACT FROM AUTHOR]

This paper presents a noncharge-sheet channel potential and drain current model for long-channel dynamic-depletion (DD) silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs). Based on the Poisson–Boltzmann equation, an analytical solution of the channel potentials in the front, back silicon/oxide and substrate/oxide interfaces is developed. It is a universal solution which predicts the channel potential accurately in all cases from accumulation to strong inversion. A unified noncharge-sheet drain current expression is derived from the three-interface analysis based on the universal channel potential solution. The proposed model shows excellent agreements with two-dimensional numerical simulations with varying geometrical structures at different device operation regions. This model provides a useful tool to study the device physics and develop a complete compact model for DD SOI MOSFET. [ABSTRACT FROM AUTHOR]

A high-voltage lateral double-diffused MOSFET with N-island (NIS) and step-doped drift (SDD) region in partial silicon-on-insulator (PSOI) technology is proposed. In the lateral direction, the SDD region and the NIS on the buried oxide layer (BOX) introduce two additional electric field peaks, which can improve the surface field distribution and breakdown voltage (BV). In the vertical direction, due to the highly doped NIS, a higher electric field is induced into the BOX layer, which can achieve a higher vertical BV. As a consequence, the BV is enhanced significantly. Moreover, the NIS with a larger doping concentration can provide a higher current of the proposed device, and thus, the ON-resistance ( $R_{{\mathrm{\scriptscriptstyle ON}}})$ is reduced. The 2-D simulation results show that the BV of the proposed structure can achieve 680 V, and $R_{{\mathrm{\scriptscriptstyle ON}}}$ is reduced by 10.2% and 14.7% in comparison with the conventional PSOI and buried n-type layer PSOI, respectively. [ABSTRACT FROM AUTHOR]

In this paper, a SPICE compatible analytical surface-potential-based model for junctionless symmetric double-gate (JLDG) MOSFETs is described. By using the gradual-channel-approximation, the 1-D Poisson’s equation is solved to obtain the surface and central potential in the JLDG MOSFET for long channel case. A continuous drain current model with smooth transitions from fully depleted region to partially depleted and accumulation regions is then derived from the Pao-Sah’s dual integral as a function of the surface and central potential at the source and drain terminals. The model is verified and validated by numerical simulations over a wide range of doping concentrations and device geometries. The model has been implemented in a circuit simulator and used to simulate some circuit building blocks without any convergent problem. [ABSTRACT FROM PUBLISHER]

An eight-FinFET fully differential SRAM cell is proposed in this paper to achieve stronger data stability and enhanced write ability. The p-type transistors are used for data access during read operations and transmission gates are employed to force new data into the cell during write operations. At the nominal process corner, the proposed SRAM cell enhances the read data stability, write voltage margin, and write data transfer speed by up to $2.7\times $ , 15.8%, and 76%, respectively, while consuming similar leakage power as compared with the previously published six-FinFET fully differential SRAM cells in 15-nm FinFET technology. Under isodata stability, the proposed SRAM cell allows the lowering of the power supply voltage by up to 44.3% as compared with the other SRAM cells that are investigated in this paper. [ABSTRACT FROM AUTHOR]

SPICE modeling of double-gate (DG) tunnel FETs (TFETs) including channel transports is reported. An ideal drain current model neglecting the channel transport is developed first. It captures the interband tunneling characteristics, describes their geometry dependences, and is suitable for DG TFETs with limited drivability. The ideal current model and previously proposed charge model are then extended to include the channel transports. One way to model the transport is appending a DG MOSFET in series with the ideal TFET model. The dependences of TFETs current and terminal charges on channel transports are reproduced. Another way by inserting a resistance at the TFET source side is also proposed with reduced simulation time. [ABSTRACT FROM PUBLISHER]

An analytical charge model for double gate (DG) tunnel FETs (TFETs) is proposed. By splitting the TFET into a series combination of a gated tunnel diode and a DG MOSFET, we solved the Poisson equation with matching boundary conditions to obtain a surface potential model for the DG TFET. Based on that, the source depletion charge and the mobile channel charge are derived. Comparisons between the proposed model and TCAD simulations show good agreements and suggest a 100/0 drain/source channel inversion charge partition. Terminal capacitances calculated based on the proposed charge model are also evaluated and show good agreement with TCAD simulations. [ABSTRACT FROM AUTHOR]

Uniaxial strain effects on electron ballistic transport in extremely scaled gate-all-around nanowire MOSFETs with both [100] and [110] orientations are investigated in this paper. Band structures of nanowires without and with strain are calculated using the empirical \sp^3\d^5\s^ \ast tight-binding model. The top-of-the-barrier model is utilized to simulate the electron ballistic transport. It is found that uniaxial [110] strain reduces the electron transport mass, but its effect gradually decreases and becomes insignificant when the dimension of the nanowire is scaled. In addition to existing band splitting caused by quantum confinement, [100] and [110] tensile strains induce further band splitting. Hence, the impact of the strain effects depends on whether the nanowire operates in the nondegenerated or degenerated mode. Simulation results show that uniaxial strain effects are more significant in [110] nanowires. The impact of surface orientation can still be observed even in deeply scaled nanowires. [ABSTRACT FROM PUBLISHER]

A study is conducted to investigate the relative advantages of different driving devices for phase-change memory cells using 3-D numerical device simulation. Among various possible choices, p-n diodes and vertical gate-all-around (GAA) metal–oxide–semiconductor field-effect transistors (MOSFETs) are studied in detail as they represent distinct classes of driving devices. Different performance parameters including cell size, current drive, disturb immunity, power dissipation, and scalability are carefully compared. While p-n diodes show superiority in technology nodes with large device dimensions, the scaling process has improved the performance of GAA MOSFETs significantly to outperform that of p-n diodes in extremely scaled technologies. [ABSTRACT FROM PUBLISHER]

This paper describes a unified framework to model the floating-body effects of various SOI MOSFET operation modes, including body-contacted mode, partially depleted mode and fully depleted mode. As the operation mode is dimension and bias dependent, different modes can co-exist in a single SOI technology. A smooth transit from one type of operation mode to another is thus essential and has been included in the model. In addition, the floating-body effects can couple to a number of other SOI specific phenomena such as heating assisted impact ionization, gate tunneling induced dynamic behavior, and operation mode dependent small signal output resistance. A methodology to model the overall SOI MOSFET behavior due to the combination of multiple floating-body related effects will also be described. [Copyright &y& Elsevier]

Presents a methodology to design high-performance metal oxide semiconductor field-effect transistor on the large-grain polysilicon-on-insulator film. Summary of general grain structural-related parameters; Devices design for channel length scaling; Effects of width and length co-scaling; Ladder layout strategy.

Deals with a study which examined narrow-width effects in thin-film silicon-on-insulator (SOI) metal-oxide-silicon-field-effect transistor (MOSFET) with MESA isolation technology. Device fabrication; Suppression of substrate bias effect in narrow-width FD SOI MOSFET; Impact of narrow-width effect on threshold voltage; Short channel effect in narrow-width SOI MOSFET; Conclusion.

Studies the characteristics of reoxidized MESA isolation for silicon-on-insulator (SOI) metal oxide semiconductor field-effect transistors (MOSFET). Device fabrication; Scaling silicon film thickness; Process optimization; Conclusion.

Presents a non-quasi-static (NQS) metal-oxide semiconductor field-effect transistor (MOSFET) model for both transient and small-signal alternating current analysis. Formulation of the model; Simulation results of the model using the BSIM3 version 3 release; Discussion and limitation of the model; Conclusions.

A unified scale length formula for four-terminal double-gate (DG) MOSFETs is proposed in this paper to provide a guideline for device design to obtain a practical threshold voltage and a subthreshold swing. By investigating the boundary conditions for Laplace's equation in the channel of DG MOSFETs, the evanescent-mode analysis method is extended to form a unified scaling scheme. The unified model is proved to be applicable to two common device structures: ultrathin-body silicon-on-insulator and symmetric DG MOSFETs based on 2-D technology computer-aided design simulation. With this model, the relationship among different well-known scaling rules can be well explained and understood. [ABSTRACT FROM PUBLISHER]

Gate-all-around (GAA) MOSFETs with elliptical cross section are studied in this letter. From the solution of the Poisson equation, an effective radius concept (Reff) is proposed to convert elliptical GAA MOSFETs into equivalent circular GAA MOSFETs for the study of short-channel effect. The Reff approach is used to estimate the subthreshold swing, drain-induced barrier lowering, and Qon/Qoff ratio of elliptical GAA MOSFETs. The predictions are validated by numerical 3-D TCAD simulations, and good agreement is achieved. Reff is also simplified to an area-to-perimeter ratio of the channel under some special conditions, and its physical meaning is explained. [ABSTRACT FROM PUBLISHER]

Introduces a large-grain polysilicon-on-insulator metal oxide semiconductor field-effect transistors formed from amorphous silicon by high-temperature metal-induced-lateral crystallization. Device design and fabrication; Device characterization and discussion.

Abstract: This paper presents an explicit surface-potential-based analytic model for the undoped long-channel symmetric double-gate MOSFET. The analytic model is derived from the rigorous solution of Poisson’s equation. Unlike the exiting analytic models using the numerical iterative method, this analytic model is based on an explicit analytic approximation. The accuracy of the proposed analytic model is justified by extensive comparisons with the numerical calculations. The relative error in nV range has been achieved. The resulting current–voltage and the derivative curves are in complete agreement with the numerical iterative results. [Copyright &y& Elsevier]

In this paper, MOSFET layout-dependent gate-around capacitance which include gate-to-source/drain fringing capacitance ( C f ) separated from gate-to-contact capacitance ( C co ), has been extracted in SPICE model. This work focuses on layout-dependent-effect (LDE) in AC characteristics such as C f and C co of MOSFET. To separate C f and C co , novel test structures have been designed and fabricated by 40 nm process. According to the silicon data, the apparent variation of C f with contact to poly space (CPS) and contact to contact space (CCS) has been modeled and exactly extracted. The errors between silicon data and simulation are mainly under 5%. The extraction and modeling of the layout-dependent C f in this work will contribute high accuracy for digital and RF circuit simulation in advanced CMOS node. [ABSTRACT FROM AUTHOR]

Abstract: This paper presents a unified charge-based model for symmetric double-gate (DG) MOSFETs with a wide range of channel doping concentrations. From one dimensional (1D) Poisson–Boltzmann equation in the DG MOSFET structure, an accurate inversion charge model is proposed, which predicts the inversion charge density precisely from weak inversion, through moderate inversion and finally to strong inversion region for both heavily doped and lightly doped condition. Based on that, the unified drain current model is developed from Pao-Sah’s dual integral. The unified terminal charge and trans-capacitance models are derived out from Ward and Dutton’s linear-charge-partition scheme. Extensive numerical simulations are performed on DG MOSFETs to verify the unified charge-based models and good agreements between them are obtained, proving the validity of the proposed model for further circuit simulation. [Copyright &y& Elsevier]

Abstract: A generic numerical model which is valid both in the strong inversion regime and sub-threshold regime for the detection of terahertz radiation utilizing Metal–Oxide–Semiconductor (MOS) Field-Effect Transistors (FETs) is developed in this paper. A general carrier density equation and gate leakage current are coupled to the basic hydrodynamic equations which govern the electron transport in the 2D channel of the MOS field-effect transistor to obtain the numerical solution; a progress-based photo-response signal of the terahertz radiation of MOSFET is calculated. The simulation results are compared with existing analytical results, proving the validity of the proposed numerical model and overcoming limitations of the analytical theories. [Copyright &y& Elsevier]

Abstract: This paper reported the sub-threshold behavior of long channel undoped surrounding-gate (SRG) MOSFETs with respect to body radius. Based on a rigorous channel potential model presented in this work, the ideal room temperature subthreshold slope of 60mV/dec can only be achieved when the silicon body radius is smaller than a critical value. With larger silicon body radius, SRG MOSFETs display a dual subthreshold slope of 60mV/dec and 120mV/dec. Based on the complex subthreshold characteristics, a new definition of threshold voltage together with an extraction method is adopted to investigate threshold voltage characteristics of undoped SRG MOSFETs in this paper. [Copyright &y& Elsevier]

Abstract: This paper presents a charge-based compact model for predicting the current–voltage and capacitance–voltage characteristics of heavily doped long-channel cylindrical surrounding-gate (SRG) MOSFETs. Starting from Poisson’s equation with fixed charge and inversion charge terms, a closed-form equation of inversion charge is obtained with the full-depletion approximation. Substituting this inversion charge expression into Pao-Sah’s dual integral, a drain current expression with concise form is derived. Based on the Ward-Dutton linear-charge-partition method and the current continuity principle, all trans-capacitances are obtained analytically. The developed model is valid in all operation regions from the sub-threshold to strong inversion and from the linear to the saturation region without any smooth function. The model predictions have been extensively compared with 3D numerical simulations and a good agreement is observed in most of the operation regions with a wide range of geometrical parameters. [Copyright &y& Elsevier]

Abstract: In this paper a novel device named as SDOV MOSFET is proposed for the first time. This structure features localized void layers under the source and drain regions. The short channel effects of this device can be improved due to the SOI-like source/drain structure. In addition, without the dielectric layer under the channel region, this device can avoid some weaknesses of UTB SOI devices caused by the thin silicon film and the underlying buried oxide, such as mobility degradation, film thickness fluctuation and self-heating effect. Based on self-aligned hydrogen and helium co-implantation technology, the new device can be fabricated by a process compatible with the standard CMOS process. The SDOV MOSFETs with 50nm gate length are experimentally demonstrated for verification. [Copyright &y& Elsevier]

Abstract: This paper outlines the charge-based core and the model architecture of the BSIM5, an advanced charge-based MOSFET model for nanoscale VLSI circuit simulation. Compared with the previous charge-based models with an assumption of the linearization of the bulk and inversion charges with respect to the surface potential at a fixed gate bias, the BSIM5 model is directly derived from the solution of the Poisson equation coupled to the current density equation. The comparisons of the inversion charge and the channel current between the BSIM5 and the Pao–Sah model indicate that the BSIM5 model maintains the inherent device physics and high accuracy of the Pao–Sah model. BSIM5 model is further extended to include the short-channel effects, narrow-width-effects, and the wide comparison with the experiment data demonstrates its validity to simulate the nanoscale circuits. Moreover, the symmetry and RF function of BSIM5 have also been demonstrated in the Gummel tests and high-order distortion analysis. [Copyright &y& Elsevier]

Abstract: An explicit current–voltage model for undoped double-gate MOSFETs based on an accurate analytic approximation to the carrier concentration is presented in this paper. An analytic approximation solution to the carrier (electron) concentration is derived from the Taylor expansion of the exact solution of the Poisson equation. This analytic approximation gives a highly accurate result of the electron concentration when compared with that evaluated by Newton–Raphson iterative. The resulting electron concentration is then coupled to the Pao–Sah current equation to produce an explicit current–voltage model for symmetric undoped double-gate MOSFETs. The model predictions have been extensively validated by numerical simulations. [Copyright &y& Elsevier]

Abstract: A carrier-based analytic DCIV model for the long channel undoped cylindrical surrounding-gate MOSFETs is presented in this paper. It is based on an exact solution of the Poisson equation and a Pao–Sah current formulation in terms of the carrier concentration. From this model, the different dependences of the surface potential, centric potential, inversion charge and the current on the silicon body thickness and the gate oxide are elucidated analytically and then the predicted DCIV characteristics are compared with the 3D numerical simulations. The analytical results of the model presented also show in a good agreement with the 3D simulation, demonstrating the model is valid for all operation regions and traces the transition between them without any need for the fitting parameter. [Copyright &y& Elsevier]

Abstract: Fast switching signals drive MOSFET into non-quasi-static operation, causing significant charging current in both on-state and off-state. Since MOSFET can be worked as a varactor in RF circuits, the modeling in the off-state is important. In this paper, a compact model is developed to model the fast-switching behavior of transistors in both states. Instead of solving the continuity and drift–diffusion equations, the model reduces the distributed network into a lumped circuit model, which is more compatible with the framework of compact model. The proposed model has been implemented in conjunction with the BSIM model and has been shown to be valid from the accumulation to the inversion. The model is developed independently from the existing I–V and C–V models and can be applied to any advanced model besides BSIM. [Copyright &y& Elsevier]

A simple process to fabricate double gate SOI MOSFET is proposed. The new device structure utilizes the bulk diffusion layer as the bottom gate. The active silicon film is formed by recrystallized amorphous silicon film using metal-induced-lateral-crystallization (MILC). While the active silicon film is not truly single crystal, the material and device characteristics show that the film is equivalent to single crystal SOI film with high defect density, like SOI wafers produced in early days. The fabricated double gate MOSFETs are characterized, which demonstrate excellent device characteristics with higher current drive and stronger immunity to short channel effects compared to the single gate devices. [Copyright &y& Elsevier]

A compact waffle MOSFET using an enhanced waffle-layout strategy is presented together with the comparison with the traditional waffle design. The enhanced compact waffle MOSFET’s have been fabricated using a 0.35-μm standard CMOS process. The true compactness of the enhanced compact waffle design is verified by the experimental results which show a reduction of about 25% in drain diffusion capacitance per unit transistor width but without any performance compromise in driving current, transconductance and subthreshold characteristics of the waffle MOSFET. With its compactness, the enhanced waffle layout uses about 35% less active device area compared with the multifinger counterpart. All these benefits are obtained without any extra processing cost. [Copyright &y& Elsevier]

Normalized mutual integral difference operator (NMIDO), a novel experimental method for extracting the threshold voltage of MOSFETs, is presented in this paper. The basic principle of this method is to use the extreme spectrum characteristics of the NMIDO to find the threshold voltage. We have demonstrated numerically that this method is applied in the extraction of the threshold voltage of MOSFETs with different effective channel length and different parasitic series resistance cases. It has been shown that this method is sensitive to the channel length variation while insensitive to the parasitic resistance component. The extracted results on the threshold voltage of MOSFETs have also been compared with those obtained by the second-derivative method and the good agreement has been found, showing the advantage of the method presented here. [Copyright &y& Elsevier]

Abstract: An analytic subthreshold potential model for gate underlap cylindrical gate-all-around (GAA) MOSFETs is presented in this work. The fringing field from the gate to underlap regions is derived by using channel length transformation and conformal mapping. The result is then applied to solve the Poisson equation to obtain the subthreshold potential distribution in the channel region of a GAA MOSFET. The model has been verified by extensive three dimensional numerical simulations. [Copyright &y& Elsevier]