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A gate-last process for fabricating HfSiON/TaN n-channel metal-oxide-semiconductor-field-effect transistors (NMOSFETs) is presented. In the process, a HfSiON gate dielectric with an equivalent oxide thickness of 10 Å was prepared by a simple physical vapor deposition method. Poly-Si was deposited on the HfSiON gate dielectric as a dummy gate. After the source/drain formation, the poly-Si dummy gate was removed by tetramethylammonium hydroxide (TMAH) wet-etching and replaced by a TaN metal gate. Because the metal gate was formed after the ion-implant doping activation process, the effects of the high temperature process on the metal gate were avoided. The fabricated device exhibits good electrical characteristics, including good driving ability and excellent sub-threshold characteristics. The device's gate length is 73 nm, the driving current is 117 μA/μm under power supply voltages of VGS = VDS = 1.5 V and the off-state current is only 4.4 nA/μm. The lower effective work function of TaN on HfSiON gives the device a suitable threshold voltage (∼ 0.24 V) for high performance NMOSFETs. The device's excellent performance indicates that this novel gate-last process is practical for fabricating high performance MOSFETs. [ABSTRACT FROM AUTHOR]

We fabricate p-channel metal-oxide-semiconductor-field-effect-transistors (PMOSFETs) with a HfSiAlON/MoAlN gate stack using a novel and practical gate-last process. In the process, SiO2/poly-Si is adopted as the dummy gate stack and replaced by an HfSiAlON/MoAlN gate stack after source/drain formation. Because of the high-k/metal-gate stack formation after the 1000°C source/drain ion-implant doping activation, the fabricated PMOSFET has good electrical characteristics. The device's saturation driving current is 2.71 × 10−4 A/μm (VGS = VDS = −1.5 V) and the off-state current is 2.78 × 10−9 A/μm. The subthreshold slope of 105 mV/dec (VDS = −1.5 V), drain induced barrier lowering of 80 mV/V and Vth of −0.3 V are obtained. The research indicates that the present PMOSFET could be a solution for high performance PMOSFET applications. [ABSTRACT FROM AUTHOR]

We experimentally investigate interfacial defects in a GeOx/Al2O3 gate stack based on ozone oxidation using x-ray photoelectron spectroscopy, and study their electrical characteristics using capacitance−voltage measurement. For a GeOx interlayer prepared by ozone oxidation, oxygen vacancies exist and show positive charges at the Ge/GeOx interface. Oxygen annealing helps to reduce oxygen vacancy defects. For the GeOx/Al2O3 interface, oxygen dangling bonds exist, and show negative charges. This work can be effectively applied to engineer interface improvements and enhance the performance of Ge-based devices. [ABSTRACT FROM AUTHOR]

The growth process of GeOx films formed by plasma post-oxidation (PPO) at room temperature (RT) is investigated using angle-resolved x-ray photoelectron spectroscopy (AR-XPS). The experimental results show that the distributions of the Ge4+ states, a mixture of the Ge2+ and Ge3+ states, and the Ge+1 states are localized from the GeOx surface to the GeOx/Ge interface. Moreover, the Ge+1 states are predominant when the two outermost layers of Ge atoms are oxidized. These findings are helpful for establishing in-depth knowledge of the growth mechanism of the GeOx layer and valuable for the optimization of Ge-based gate stacks for future complementary metal–oxide–semiconductor (MOS) field-effect transistor (CMOSFET) devices. [ABSTRACT FROM AUTHOR]

Strained-Si0.73Ge0.27 channels are successfully integrated with high-κ/metal gates in p-type metal-oxide- semiconductor field effect transistors (pMOSFETs) using the replacement post-gate process. A silicon cap and oxide inter layers are inserted between Si0.73Ge0.27 and high-κ dielectric to improve the interface. The fabricated Si0.73Ge0.27 pMOSFETs with gate length of 30 nm exhibit good performance with high drive current (∼428 μA/μm at VDD = 1 V) and suppressed short-channel effects (DIBL∼77 mV/V and SS∼90 mV/decade). It is found that the enhancement of effective hole mobility is up to 200% in long-gate-length Si0.73Ge0.27-channel pMOSFETs compared with the corresponding silicon transistors. The improvement of device performance is reduced due to strain relaxation as the gate length decreases, while 26% increase of the drive current is still obtained for 30-nm-gate-length Si0.73Ge0.27 devices. [ABSTRACT FROM AUTHOR]

The thickness effect of the TiN capping layer on the time dependent dielectric breakdown (TDDB) characteristic of ultra-thin EOT high-k metal gate NMOSFET is investigated in this paper. Based on experimental results, it is found that the device with a thicker TiN layer has a more promising reliability characteristic than that with a thinner TiN layer. From the charge pumping measurement and secondary ion mass spectroscopy (SIMS) analysis, it is indicated that the sample with the thicker TiN layer introduces more Cl passivation at the IL/Si interface and exhibits a lower interface trap density. In addition, the influences of interface and bulk trap density ratio Nit/Not are studied by TDDB simulations through combining percolation theory and the kinetic Monte Carlo (kMC) method. The lifetime reduction and Weibull slope lowering are explained by interface trap effects for TiN capping layers with different thicknesses. [ABSTRACT FROM AUTHOR]