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The optimization of drift region specific ON-resistance (${R} _{on,sp}$) for superjunction (SJ) MOSFETs with three-dimensional (3-D) and insulator-pillar (${i}$ -pillar) concepts is proposed and compared with the two-dimensional conventional SJ (2-D C-SJ) MOSFETs. With the constraints of avalanche breakdown and critical depletion, the optimized ${R} _{on,sp}$ and the corresponding design parameters are numerically determined. For the 3-D concept, a superior ${R} _{on,sp}$ can be obtained only for a high breakdown voltage (BV) or a low pillar aspect-ratio (AR) due to the better charge compensation. The junction field-effect transistor (JFET) effect induced by the lateral pillars depletion exceeds the charge compensation due to the stronger electric field crowding effect. For the ${i}$ -pillar concept, parasite depletion is alleviated due to an additional voltage sustained across the insulator pillar, especially for a narrow SJ pillar. The optimization design for the 650-V class SJ MOSFETs with 3-D and ${i}$ -pillar concepts demonstrates an optimized ${R} _{on,sp}$ with 3.99 $\text{m}\Omega \cdot $ cm2 at AR = 10 and 1.40 $\text{m}\Omega \cdot $ cm2 at AR = 70 can be obtained in 3-D ${i}$ -pillar SJ (3-D I-SJ) and 2-D ${i}$ -pillar SJ (2-D I-SJ), respectively. For the 650-V class SJ MOSFETs, 3-D and 2-D I-SJ structures have a lowest ${R} _{on,sp}$ than the other structures for AR less and greater than 57, respectively. The charge imbalance effects of BV for these structures are also discussed. [ABSTRACT FROM AUTHOR]

A single-channel SiC trench MOSFET (SC-TMOS) with integrated trench MOS barrier Schottky diode (TMBS) is proposed and investigated in this paper. The electric field at the Schottky interface is reduced to 0.37 MV cm−1 by the trench MOS and P+ shield under the gate, which completely suppresses the leakage current through the TMBS. The on-state voltage drop (VR_ON) of the SC-TMOS in reverse conduction state is reduced to 1.59 V (@JSD = 400 A cm−2) compared to 2.93 V of the PN body diode of a conventional trench MOSFET (C-TMOS) and 1.61 V of a three-level protection trench MOSFET (TP-TMOS). Meanwhile, higher BFOM (Baliga's figure of merit: BV2/Ron,sp) is obtained, which is 11.8% and 40% improved compared with those of the C-TMOS and TP-TMOS, respectively. Besides, the reverse recovery charge of the SC-TMOS is reduced by 41.7% and 66.4% compared with those of the C-TMOS with or without external junction barrier Schottky diode (JBS), and is comparable with that of the TP-TMOS. Moreover, with optimized design, CGS and CGD decrease dramatically. As a result, the total inductive switching loss of the proposed SC-TMOS is reduced by 19.5%, 43.2% and 28.8% compared with those of the C-TMOS with or without external JBS and TP-TMOS, respectively. [ABSTRACT FROM AUTHOR]

An improved lateral power p-channel trench metal–oxide–semiconductor field-effect transistor (MOSFET) is proposed. By using a technique of variation vertical doping (VVD), the threat of charge imbalance posted by the parasitic trench capacitance is eliminated. Moreover, a p-type VVD increases the number of carriers, and an n-type VVD intensifies the charge compensation effect. Hence, compared to the conventional device without VVD, the proposed device gets a significantly improved tradeoff relationship between the breakdown voltage (BV) and the specific ON-resistance (RON,SP). According to the simulation results, the proposed device using the triple piecewise VVD obtains a RON,SP of 10.6 mΩ ⋅ cm2 at a BV of 440 V, reaching a figure of merit (FOM = BV2/RON,SP) being 2.4 times larger than that of the prior art. [ABSTRACT FROM AUTHOR]

This article proposes a MATLAB-based optimization methodology of the drift region specific ON-resistance (${R}_{on,sp}$) both for the high-permittivity (Hk) MOSFETs and superjunction (SJ) MOSFETs with design parameters expressed by breakdown voltage (BV) and aspect ratio (AR). The optimized method has three distinctive features. First, based on the built-in functions in MATLAB, the proposed method is very efficient to accurately obtain the optimized Ron,sp (Ron,sp(opt)) and the design parameters for both MOSFETs. Second, as the reflection of the process difficulty in the Hk or SJ structure, AR is used as one of the design variables. Third, the cubic polynomial functions are used to obtain a more accurate fitting for the optimization. The optimized results demonstrate that for a given BV, the Ron,sp(opt) for the SJ MOSFET decreases as AR increases, whereas an optimum AR exists for a minimal Ron,sp(opt) for the Hk MOSFET. Extensive comparisons demonstrate that when AR is small and BV is large, the Ron,sp(opt) for the Hk MOSFET could be lower than that for the SJ MOSFET. Parameter designs are performed for the 900-V Hk MOSFET and SJ MOSFET. The impacts of important parameter variations on BV and Ron,sp are also discussed. The validity of the proposed optimization method is demonstrated by the TCAD simulations. [ABSTRACT FROM AUTHOR]

A new lateral power metal-oxide-semiconductor field-effect transistor (MOSFET) with dual conduction paths and high- ${k}$ passivation is proposed. The high- ${k}$ passivation enables the dual conduction paths to realize the double reduced surface field (RESURF) action and facilitates the formation of an accumulation layer during forward conduction. The proposed device offers a 42% reduction in specific on-resistance (${R}_{{ON},{SP}}{)}$ when compared to a similar size baseline device with the same breakdown voltage (BV). The technology computer-aided design (TCAD) simulation results, based on a $0.5~\mu \text{m}$ bipolar-CMOS-DMOS (BCD) compatible process, show that the proposed device is able to provide a ${R}_{{ON},{SP}}$ as low as 0.28 $\text{m}\Omega \cdot $ cm2 with a BV of 92 V. [ABSTRACT FROM AUTHOR]

In this paper, a super-junction p-type lateral diffused metal–oxide–semiconductor transistor (SJ-pLDMOS) utilizing electron to enhance the current capability is proposed. The proposed SJ-pLDMOS has an n-channel in the drain region and is controlled by an auto-generated voltage signal (${V}_{\mathrm {\textsf {Gn}}}$). The voltage signal ${V}_{\mathrm {\textsf {Gn}}}$ is generated during the ON- and OFF-state of the hole current which flows across an integrated resistor (${R}\text{p}$) implemented in the p-base region. Thus, the proposed SJ-pLDMOS utilizes both hole and electron currents to significantly enhance the current capability. Simulation results show that the current capability of the proposed SJ-pLDMOS without any conductivity modulation effect is comparable with that of a super-junction nLDMOS (SJ-nLDMOS). The total power loss of the proposed super-junction pLDMOS (SJ-pLDMOS) is reduced by about 26.7% and 18% compared with that of the SJ-nLDMOS and Triple Resurf nLDMOS (TR nLDMOS) at a rated load current density of $25~\mu \text{A}/\mu \text{m}$ , respectively. [ABSTRACT FROM AUTHOR]

A novel trench insulated bipolar transistor (TIGBT) is proposed, where a p-layer beneath the trench gate is introduced to form a self-biased pMOS and provide an additional path for the hole current. In the on-state, the drain-to-source voltage of the trench nMOS is clamped, which helps to decrease the saturation current. In the blocking state, the reverse voltage is sustained by the junction of p-layer/n-drift, so that the n-layer sandwiched by the p-base region and the n-drift region can be as heavily doped as possible to reduce the on-state voltage without affecting the breakdown capability. The simulation results show that, in comparison with the conventional one, under the same breakdown voltage, the saturation current and the on-state voltage of the proposed TIGBT are decreased by 47% and 35%, respectively. [ABSTRACT FROM PUBLISHER]