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Self-heating in fully depleted silicon-on-insulator (FDSOI) metal–oxide–semiconductor field-effect transistors (MOSFETs) is experimentally studied using the gate resistance thermometry technique, in a wide temperature range from 300 down to 4.2 K. We demonstrate that below 160 K, the channel temperature increase ($\Delta {T}$) due to self-heating starts to deviate significantly from the linear variation with the dissipated power, leading to an apparent power dependent thermal resistance. This power dependence is interpreted in terms of temperature dependent thermal conductivity. The thermal resistance dependence on the active device temperature (${T}_{\text {Device}}$) indicates that the former one is mainly driven by the thermal conductivity of the oxide layer. Moreover, based on this dependence we reconstructed the channel temperature increase for each dissipated power and ambient temperature, and we found that the calculated values were in a good agreement with the experimental ones. Results indicate that even at low temperatures, thermal resistance does not depend significantly on the silicon channel thickness (ranging from 7 up to 24 nm), whereas the buried-oxide thinning (145 and 25 nm) strongly reduces the magnitude of the thermal resistance. Finally, this paper intends to fill the gap of experimental data concerning self-heating in advanced FDSOI transistors at low temperatures, revealing limitations and perspectives that should be taken into account for future work. [ABSTRACT FROM AUTHOR]

Low-frequency noise (LFN) of high-k/metal stack nMOS and pMOS transistors is experimentally studied. Results obtained on 32-nm complementary metal–oxide–semiconductor (CMOS) technologies, including LFN spectra and normalized power spectral density data analysis, are presented. These results indicate that the carrier number fluctuation is the main noise source for both nMOS and pMOS devices. As noise performance may strongly vary between different devices on one chip, the variability of the LFN when scaling down devices was also evaluated. A model known in the literature was used and enhanced in order to understand the noise level variability. A statistical analysis of the noise variability is also presented showing the dependence of the standard deviation with the device area. The comparison with former results from 45-nm poly/SiON technology demonstrates a better control of noise variability in the 32-nm CMOS technology. [ABSTRACT FROM PUBLISHER]

The impact of the front oxide quality on the performance of SOI devices is investigated. In this respect, a Fowler–Nordheim stress is performed for both partially (PD) and fully (FD) depleted N-MOSFETs. Various special SOI mechanisms are analyzed, as floating body effects for PD devices and coupling effects, between front and back interfaces, for FD ones. In the first part, the influence of the front oxide quality in PD transistors on transient effects and low-frequency noise (LFN), which both are influenced by the floating body, is analyzed. In the second part, the impact of the front oxide and coupling effects on the LFN in FD MOSFETs is investigated. [Copyright &y& Elsevier]

In this letter, we demonstrate the existence of the source–drain series resistance mismatch and its impact on drain current variability with regard to the other mismatch parameters. To this end, we propose a new methodology for the drain current mismatch study based on $Y$ -function, enabling a precise determination of the various variability sources in advanced fully depleted silicon on insulator (SOI) MOS devices. [ABSTRACT FROM AUTHOR]

In this paper, a parametric statistical analysis of the low-frequency noise (LFN) in very small area ( W · L ≈ 10 −3 μm 2 ) 14 nm fully depleted silicon-on-insulator (FD-SOI) n-MOS devices is presented. It has been demonstrated that the LFN origin is due to carrier trapping/detrapping into gate dielectric traps near the interface and the mean noise level in such small area MOSFETs is well approached by the carrier number fluctuations model in all measurement conditions. The impact of gate voltage bias and temperature on the LFN variability, as well as the standard deviation dependence on frequency have been studied for the first time, focusing on their relation to the Random Telegraph Noise (RTN) effect and its characteristics. [ABSTRACT FROM AUTHOR]

Abstract: Extensive investigation of the low-frequency noise in n-channel and p-channel MOSFETs, with high-k gate stack and channel length varying from 1.8μm down to 26.4nm, has been carried out. The results demonstrate that the carrier number fluctuation with correlated mobility fluctuations describes accurately and continuously the 1/f noise for all operation regions, i.e. from weak to strong inversion and from linear to saturation. It has been found that the product of the Coulomb scattering coefficient and the effective carrier mobility is constant over a wide range of the drain current due to the interplay of the Coulomb scattering coefficient αsc and the effective carrier mobility μeff variations. In addition, a non-linear increase in the square root of the input gate voltage noise with the gate voltage overdrive was observed explained by the surface roughness scattering. The overall results lead to an analytical expression for the 1/f noise model, enabling to predict the noise level of a transistor with any channel dimensions using its transfer characteristic. This finding makes the noise model suitable for circuit simulation tools. [Copyright &y& Elsevier]

In this work, we investigate the impact of the source - drain series resistance mismatch on the drain current variability in 28 nm bulk MOSFETs. For the first time, a mismatch model including the local fluctuations of the threshold voltage ( V t ), the drain current gain factor ( β ) and the source – drain series resistance ( R SD ) in both linear and saturation regions is presented. Furthermore, it is demonstrated that the influence of the source – drain series resistance mismatch is attenuated in the saturation region, due to the weaker sensitivity of the drain current variability on the series resistance variation. The experimental results were further verified by numerical simulations of the drain current characteristics with sensitivity analysis of the MOSFET parameters V t , β and R SD . [ABSTRACT FROM AUTHOR]

A new full gate voltage range methodology using a Lambert W function based inversion charge model, for extracting the electrical parameters in FDSOI nano-MOSFET devices, has been developed. Split capacitance–voltage measurements carried out on 14 nm technology FDSOI devices show that the inversion charge variation with gate voltage can be well described by a Lambert W function. Based on the drain current equation in the linear region including the inversion charge described by the Lambert function of gate voltage and the standard mobility equation enables five electrical MOSFET parameters to be extracted from experimental I d – V g measurements (ideality factor, threshold voltage, low field mobility, first and second order mobility attenuation factors). The extracted parameters were compared with those extracted by the well-known Y-function in strong inversion region. The present methodology for extracting the electrical MOSFET parameters was verified over a wide range of channel lengths on nano-scale FDSOI devices, demonstrating its simplicity, accuracy and robustness. [ABSTRACT FROM AUTHOR]