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The oxidation rate of SiC can be greatly enhanced by pre-amorphization ion-implantation (PAI), and the PAI process has been employed to form the LOCal Oxidation of SiC (LOCOSiC) structure for device isolation in SiC integrated circuits (ICs). This work presents the study on the defect layer below the thermally grown SiO2 and the impact of the defect layer on devices. The deep-level transient spectroscopy (DLTS) analysis reveals that the defect layer consists lots of C vacancies and Si vacancies. The leakage current of the edge-intensive N+/P-junction exhibits stronger temperature dependence than that of the P+/N-junction. This result confirms that C vacancy is an effective lifetime killer in n-type SiC, but not in p-type SiC. Although these defects increase the leakage current of the edge-intensive SiC N+/P-junction by 42 times at 150 °C compared with the junction with conventional chemical vapor deposited (CVD) field oxide (FOX), the leakage current is still much lower than the required OFF-state current of ICs. The defect layer has high resistance, and it is hard to let the SiC surface into inversion state so that the threshold voltage of the field MOSFET is higher than ±24 V. [ABSTRACT FROM AUTHOR]

This work demonstrates a trench isolated lateral double-implanted MOSFET (LDMOS) on Si-face in 4H-silicon carbide (SiC). A device $\vphantom {_{\int _{}}}$ where ${L}_{\textit {ch}} = 0.8\,\,\mu \text{m}$ and ${L}_{d} = 12\,\,\mu \text{m}$ shows an ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ of 22.9 $\text{m}\Omega $ cm2 at a ${V}_{\text {GS}}$ of 20 V and a breakdown voltage (BV) of 1100 V, corresponding to a high BV2/ ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ of 55.5 MW/cm2. Devices that have different ${L}_{\text {ch}}$ , ${L}_{\text {JFET}}$ , ${L}_{d}$ , and P-top dose values are measured in order to investigate the effects of geometry on the static performance. Operations at 150 °C are measured to evaluate the temperature performance. Gate charge waveforms are also measured in order to include the switching performance in the evaluation. The ${R}_{ \mathrm{\scriptscriptstyle ON}} \times {Q}_{G}$ and ${R}_{ \mathrm{\scriptscriptstyle ON}} \times {Q}_{\text {GD}}$ values are calculated as 17.7 and $9.0~\Omega $ nC, respectively, which are promising for power-integrated circuit applications. [ABSTRACT FROM AUTHOR]

The effects of Ar inductively coupled plasma (ICP) treatment followed by a 600 °C–1000 °C rapid thermal annealing (RTA) on the n-type 4H-silicon carbide (SiC) Schottky-barrier diodes and n+-implanted ohmic contacts were investigated. The ICP treatment created a 3-nm-thick, sp2–C-rich, and amorphous layer at the SiC surface. The RTA repaired the bombardment-induced damages before metal deposition to avoid current degradation. This ICP + RTA-treated surface strongly pinned the Schottky-barrier height (SBH) at a minimum of 0.88 eV. In theory, the low SBH is beneficial to decrease the specific contact resistance ($\rho _{C}$). $\rho _{C}$ of the ICP + RTA-treated Ti ohmic contacts decreased to lower than $10^{-{5}} \,\,\Omega \cdot \text {cm}^{{2}}$ after 400 °C postmetal deposition annealing (PMDA). However, the additional O atoms, fixed in the amorphous layer by RTA, affected the $\rho _{C}$ reduction. Fortunately, due to the chemical affinity for O of Ti, the in-diffused Ti could contend for the O atoms against the Si–O bonds during the PMDA. Therefore, the oxidized barricade was decomposed gradually, leading to the lowest $\rho _{C}$ , $1.3\times 10^{-{6}} \,\,\Omega \cdot \text {cm}^{{2}}$ , after 600 °C PMDA. The lowest $\rho _{C}$ is $25\times $ and $8\times $ lower than that of the Ni silicide and the nontreated Ti contacts, respectively, at the same doping concentration. [ABSTRACT FROM AUTHOR]

Abstract: Effect of surface preparation on the radiation hardness of MOS devices with high dielectric constant gate dielectric of HfO2 and metal gate of TiN is studied using extreme ultra-violet (EUV) light as the radiation source. Three kinds of surface treatment including HF-last, chemical-oxidation, and rapid-thermal-oxidation were evaluated. Among them, chemical-oxidation exhibits the best radiation hardiness in terms of interface traps and border traps. The state-of-the-art MOSFET with a thin high-k dielectric and a high quality chemical oxide interfacial layer shows that the degradation of subthreshold swing is more severe than degradation of threshold voltage. However, the overall degradation is less than 6% even after EUV irradiation to a total dose of 580mJ/cm2. Off-state current degradation is observed due to the generation of oxide traps and interface traps at the isolation region. This phenomenon does not occur in the conventional optical lithography process but should be considered if EUV lithography is used. [Copyright &y& Elsevier]

In this letter, we present a high performance Ge n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) with a NiGe Schottky junction source/drain fabricated using phosphorus dopant segregation. Phosphorus atoms were implanted into NiGe and then driven toward the NiGe/p-Ge interface to depin the Fermi level and form a Schottky junction. A high effective barrier height (\PhiBp) of 0.57 eV, resulting in a high junction current ratio of >10^4 at the applied voltage \vertVa\vert=\pm1~V. The nMOSFET exhibited a high ION/IOFF ratio of \sim8\times 10^3~(ID), \sim10^5~(IS), and a subthreshold swing of 138 mV/decade. The nMOSFET developed in this letter exhibited greater transconductance and a drain leakage current that is more than two orders of magnitude lower compared with nMOSFETs with the conventional n^+/p junction. [ABSTRACT FROM AUTHOR]

Fringing-induced barrier lowering (FLBL) effect on nanoscale MOSFET is comprehensively examined. It is observed that by combining stack gate dielectric, conductive spacer, shod sidewall spacer, and minimum gate/drain (G/D) overlap, the Ioff with a dielectric constant of (k) 100 is only 1.6 times higher than that with k = 3.9 when the gate length is 25 nm. The fully depleted silicon-on-insulator device shows even better FLBL immunity. It is concluded that although the FIBL effect can not be eliminated, it would not an issue beyond the 45-nm technology node. [ABSTRACT FROM AUTHOR]