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Herein, cryogenic field‐effect transistors (FETs) are discussed. In particular, the saturation of the subthreshold swing due to band tailing is studied. It is shown with simulations and experiments that engineering of the oxide‐channel interfaces and a strong increase of the gate oxide capacitance are effective in improving the switching behavior of the device. The implication of scaling the oxide capacitance on the power consumption of cryogenic devices is investigated, too. Furthermore, an alternative for conventional doping in cryogenic transistors is discussed. Based on synchrotron X‐Ray absorption spectroscopy at total fluorescence (XAS‐TFY) and ultraviolet photoemission spectroscopy (UPS) measurements, it is shown experimentally that in true nanoscale devices, a simple SiO2$\left(\text{SiO}\right)_{2}$ coating yields a shift of the conduction band that is equivalent to a very high dopant concentration. As a result, nanoscale cryogenic steep slope FETs with strongly improved electrical characteristics become feasible. [ABSTRACT FROM AUTHOR]

The subthreshold behavior of floating-gate MOSFETs connected with ferroelectric capacitors (FeCs) was investigated experimentally and theoretically. We found that the subthreshold swing (SS) decreases with decreasing ferroelectric capacitance (i.e., with the decreasing FeC area), in contrast to the voltage dividing effect of regular dielectric capacitors. The ferroelectric polarization switching counteracts the effect of voltage dividing by introducing an additional charge onto the floating gate, which improves the SS and leads to the observed SS dependence. The SS improvement caused by the polarization switching is different from the negative capacitance effect, which is helpful to further understand the ferroelectric transistor. [ABSTRACT FROM AUTHOR]

This letter reports for the first time a full experimental study of performance boosting of tunnel FETs (TFETs) and MOSFETs by negative capacitance (NC) effect. We discuss the importance of capacitance matching between a ferroelectric NC and a device capacitance to achieve hysteretic and non-hysteretic characteristics. PZT ferroelectric capacitors are connected to the gate of three terminals TFETs and MOSFETs and partial or full matching NC conditions for amplification and stability are obtained. First, we demonstrate the characteristics of hysteretic and non-hysteretic NC-TFETs. The main performance boosting is obtained for the non-hysteretic NC-TFET, where the ON-current is increased by a factor of 500 times, transconductance is enhanced by three orders of magnitude, and the low slope region is extended. The boosting of performance is moderate in the hysteretic NC-TFET. Second, we investigate the impact of the same NC booster on MOSFETs. Subthreshold swing as steep as 4 mV/decade with a 1.5-V hysteresis is obtained on a commercial device fabricated in 28-nm CMOS technology. Moreover, we demonstrate a non-hysteretic NC-MOSFET with a full matching of capacitances and a reduced subthreshold swing down to 20 mV/decade. [ABSTRACT FROM AUTHOR]

This letter presents an experimental capacitance–voltage C – V analysis for Si p-tunnel FETs (TFETs) fabricated on ultrathin body at various frequencies and temperatures. The capacitance distribution in TFETs is quite different compared with MOSFETs, due to different inversion charges partitioning between source and drain. Contrary to predictions from simulations, we provide experimental evidence for the first time that the contribution of the gate-to-source capacitance C\textsf {gs} to the total gate capacitance is much larger than expected, and even comparable to the gate-to-drain capacitance C\textsf {gd} at higher V\textsf {ds} and Vg . Comparable values of C\textsf {gs} and C\textsf {gd} would imply that the Miller capacitance effect in TFETs-based circuits is less pronounced as predicted in simulations. [ABSTRACT FROM PUBLISHER]

We present a method to form ultrathin highly uniform Ni(Al) germanosilicide layers on compressively strained Si1-xGex substrates and their structural characteristics. The uniform Ni(Al) germanosilicide film is formed with Ni/Al alloy at an optimized temperature of 400 °C with an optimized Al atomic content of 20 at. %. We find only two kinds of grains in the layer. Both grains show orthogonal relationship with modified B8 type phase. The growth plane is identified to be {10-10}-type plane. After germanosilicidation the strain in the rest Si1-xGex layer is conserved, which provides a great advantage for device application. [ABSTRACT FROM AUTHOR]

Abstract: Strained SiGe heterostructure-on-insulator (001) and (110) PMOSFETs are investigated including important aspects like C–V characteristics, mobility, and ON current. The simulations are based on the self-consistent solution of 6×6 k · p Schrödinger Equation, multi subband Boltzmann Transport Equation and Poisson Equation, and capture size quantization, strain, crystallographic orientation, and SiGe alloy effects on a solid physical basis. The simulation results are validated by comparison with different experimental data sources. The simulation results show that the strained SiGe HOI PMOSFET with (110) surface orientation has a higher gate capacitance and a much higher mobility and ON current compared to a similar device with the traditional (001) surface orientation. [Copyright &y& Elsevier]

Terbium scandate (TbScO3) and lanthanum scandate (\LaScO3) have been investigated as gate dielectrics for metal–oxide–semiconductor field-effect transistors on both silicon-on-insulator (SOI) and strained SOI (sSOI) substrates. X-ray photoelectron spectroscopy analysis revealed the presence of a silicate at the interface for \TbScO3 on Si, whereas a silicate/\SiO2-like interface was found for the \LaScO3 on Si. A full replacement gate process was developed to fabricate high-\kappa/metal gate fully depleted transistors on SOI and sSOI. \LaScO3 transistors with a gate length of 2 \mu \m show excellent characteristics with steep subthreshold slopes of 72 mV/dec, high Ion/Ioff ratios, and electron mobility of 180 \cm^2/\V \cdot \s for SOI and 375 \cm^2/\V \cdot \s for sSOI at low field, which is superior to corresponding \TbScO3 devices. All sSOI transistors showed 2 times higher electron mobility than SOI reference devices. [ABSTRACT FROM PUBLISHER]

A new self-assembly patterning method for generation of epitaxial CoSi2 nanostructures was used to fabricate 70 nm gate-length Schottky barrier MOSFETs on SOI substrates. This technique involves only conventional optical lithography and standard silicon processing steps. It is based on anisotropic diffusion of Co/Si atoms in a strain field during rapid thermal processing. The strain field is generated along the edges of a mask consisting of 20 nm SiO2 and 300 nm Si3N4. During rapid thermal oxinitridation (RTON) of the masked silicide structure, a well-defined separation of the silicide layer forms along the edge of the mask. These highly uniform gaps define the channel region of the fabricated device. The separated silicide layers act as metal source and drain. During the RTON-step a 6 nm thin SiO2 is formed on top of the gap which is used as a gate oxide. The Schottky barrier MOSFETs can be driven as both p-channel and n-channel devices without complementary substrate doping and show good I–V characteristics. [Copyright &y& Elsevier]

The gate-induced-drain-leakage of MOSFETs is analyzed to better understand the sub-threshold swing degradation of SiGe tunnel field-effect transistors and their band-to-band tunneling mechanism. The numerical model of the analysis is elaborated. Equivalent trap energy levels are extracted for Si and strained SiGe. It is found that the equivalent trap energy level in SiGe is shallower than that in Si. [ABSTRACT FROM AUTHOR]

Abstract: Nanowire-array metal-oxide-semiconductor field effect transistors (MOSFETs) were fabricated along <110> and <100> crystal directions on (001) un-/strained silicon-on-insulator substrates. Lateral strain relaxation through patterning was employed to transform biaxial tensile strain into uniaxial tensile strain along the nanowire. Devices feature ideal subthreshold swings and maximum on-current/off-current ratios of 1011 for n and p-type transistors on both substrates. Electron and hole mobilities were extracted by split C–V method. For p-MOSFETs an increased mobility is observed for <110> channel direction devices compared to <100> devices. The <100>n-MOSFETs showed a 45% increased electron mobility compared to <110> devices. The comparison of strained and unstrained n-MOSFETs along <110> and <100> clearly demonstrates improved electron mobilities for strained channels of both channel orientations. [Copyright &y& Elsevier]

• The impact of various ion implantation schemes on the subthreshold behavior of cryogenic FD SOI MOSFETs is investigated. • The density of localized states was decreased by the optimized ion implantation into silicide process. • The effects of ion implantation angle and activation temperature were systematically studied. Band tailing is a critical issue for cryogenic CMOS, which significantly degrades the performance of conventional MOSFETs at cryogenic temperature. The band tail arises primarily due to Gaussian-distributed localized states, which can be induced by ion implantation during source/drain formation. In this study, we investigate the impact of various ion implantation schemes on the subthreshold behavior of cryogenic fully depleted (FD) SOI MOSFETs. By optimizing the ion implantation into silicide (IIS) process, we were able to reduce the density of localized states and achieve a steep switching performance at 5 K. We systematically examine the effects of ion implantation angle and activation temperature of IIS on the device performance at cryogenic temperatures. [ABSTRACT FROM AUTHOR]

Steep slope negative capacitance MOSFETs with HfYO x ferroelectric on FDSOI were experimentally demonstrated. An average SS of 30 mV/dec was achieved over 3 decades of drain current. The negative capacitance is believed to be a transient phenomenon because a strong polarization switching is needed for the steep slope. We found that the sub-thermal SS degrades with the cycling measurements, which is assumed to be caused by the trap charging in the ferroelectric oxide layer. The tradeoff between polarization and charge trapping is responsible for the subthreshold behavior of the device. [ABSTRACT FROM AUTHOR]

• UTBB SOI Schottky-Barrier MOSFETs are operated at cryogenic temperature. • The impact of the back-gate on the device performance is systematically studied. • The resonant tunneling and hot-carrier effects are observed at cryogenic temperature. Schottky-Barrier (SB) MOSFETs are fabricated and characterized at room temperature (RT) and 5.4 K. The substrate bias impacts on SB MOSFETs are systematically investigated by measuring the threshold voltage V th , subthreshold swing SS and transconductance G m , showing the back gate has almost no effects on these parameters at 5.4 K, in contrast to the results measured at RT. Some oscillations are created in G m curves by the quantization effect and resonant tunneling at 5.4 K. A large hysteresis is found by enhanced dynamic threshold operation at 72 K due to hot carriers and the presence of a Schottky barrier at the drain. [ABSTRACT FROM AUTHOR]

A high-κ/metal-gate (HKMG) last process for fabricating strained Si 0.5 Ge 0.5 quantum-well (QW) p-channel metal oxide semiconductor field effect transistors (p-MOSFETs) is presented. Because the HKMG was formed after the ion-implant doping activation process, the thermal budget issue could be mitigated. The transistor features good transfer and output characteristics with I on / I off ratio up to 10 6 and threshold voltage ( V T ) down to 0.1 V. The effective hole mobility of the SiGe QW transistor reaches 215 cm 2 /V s for strong inversion conditions, which is 2.74 times the SOI device’s hole mobility. [ABSTRACT FROM AUTHOR]

• SOI UTBB nMOSFETs are operated at cryogenic temperature with different gate lengths. • The impact of the back-gate on the device performance is systematically studied. • A good performance of devices is obtained at cryogenic temperature by back-gate. • Short channel effects are investigated at cryogenic temperature. In this paper we present an experimental study of SOI UTBB n-MOSFETs at cryogenic temperatures. The device employs fully silicided source/drain with dopant segregation formed by "Implantation Into Silicide" (IIS) process. The impact of the back-gate (V back) on the device performance is systematically investigated. The results demonstrate that V back is essential to tune the threshold voltage V th. And optimization of V back values can improve the subthreshold swing (SS), Drain-Induced Barrier Lowering (DIBL), transconductance G m and mobility at cryogenic temperatures, providing a potential to fulfill the ultra-low power requirement for quantum computing application. [ABSTRACT FROM AUTHOR]

• Junctionless Nanowire Transistors (JNTs) with NSDE and GSD layouts are compared. • GSD JNTs show higher on-currents, smaller variations of SS, DIBL and V T. • GSD device shows larger Cgg, but much higher cut-off frequency. • A "dumbbell" nanowire JNT is proposed and simulated. We present experimental results for junctionless nanowire transistors (JNTs) with different gate alignments to the nanowire. Devices with nanowire source/drain extensions (NSDE) show high series source/drain resistance due to the low doped nanowire extensions, which causes lower drive current and larger device performance variations comparing with devices in which the gate electrode overlaps with the source/drain contact pads (GSD). Due to the improved on-current GSD devices exhibit much higher cutoff frequency. The high fringing field in the NSDE JNT results in degradation of SS. An optimized "dumbbell" shape JNT structure is proposed to further improve the device performance. Our preliminary simulations demonstrate higher on-currents but also larger parasitic capacitances for the dumbbell JNT. However, the RF performance of the dumbbell JNT is still improved with a factor similar to our experiments. Much smaller fringing field for the dumbbell JNT is expected from the simulation, which can cause less device variations. [ABSTRACT FROM AUTHOR]