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We developed an analytical model that is able to predict the evolution of the subthreshold slope variability associated with hot carrier (HC) stress. The model assumes that HC stress generates interface states with a Poisson distribution and that the number of HC-induced interface states increases linearly with the HC-induced subthreshold slope variation. We validate the model by means of extensive variability data sets collected on n-channel MOSFETs in 45- and 65-nm CMOS technologies. Furthermore, we investigate the correlation between the threshold voltage and the subthreshold slope fluctuations in order to fully characterize their impact on the subthreshold current variability. [ABSTRACT FROM AUTHOR]

This paper examines the impact of hot carriers (HCs) on n-channel metal–oxide–semiconductor (MOS) field-effect transistor mismatch across the 45- and 65-nm complementary MOS technology generations. The reported statistical analysis is based on a large overall sample population of about 1000 transistors. HC stress introduces a source of variability in device electrical parameters due to the randomly generated charge traps in the gate dielectric or at the substrate/dielectric interface. The evolution of the threshold-voltage mismatch during an HC stress is well modeled by assuming a Poisson distribution of the induced charge traps with a nonuniform generation along the channel. Once the evolution of the HC-induced VT shift is known, a single parameter is able to accurately describe the evolution of the HC-induced VT variability. This parameter is independent of the stress time and stress bias voltage. The HC stress causes a significantly larger degradation in the subthreshold slope variability, compared to threshold voltage variability for both investigated technology nodes. [ABSTRACT FROM AUTHOR]

Systematic and random parametric mismatches are major performance limiters as well as notorious causes for redesigns of high precision mixed-signal circuits and systems. Therefore, it is extremely important to measure, analyze, interpret, model and document parametric mismatch mechanisms meticulously for mixed-signal technologies. This paper gives an overview of the main requirements and techniques for mismatch characterization of active and passive devices in deep submicron mixed-signal IC technologies. [ABSTRACT FROM AUTHOR]