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This article presents an active neutral point clamped (ANPC)-based parallel dual-active bridge (DAB) architecture which combines dv/dt cancellation and power sharing in order to reduce electromagnetic interference (EMI) caused by common-mode (CM) current. High dv/dt associated with wide bandgap devices causes high CM current mainly due to parasitic capacitances. The corresponding conducted EMI can remarkably reduce the reliability of power converters and other onboard systems. This issue becomes worse due to higher dc bus voltage trend in electric vehicles (EV) and other dc systems. Conventional techniques struggle to provide attenuation in a wide frequency range. The problem can also be severe in soft-switched DAB converters as they operate at relatively higher frequencies. In this article, initially, an in-depth theoretical analysis is provided to understand the complimentary dv/dt events. Various factors causing nonideal dv/dt cancellation are discussed in detail together with possible solutions. Detailed experimental results are obtained from a 1100 V–150 V parallel DAB system including both the high and low voltage sides at different dv/dt rates. dv/dt cancellation at lowered dv/dt rates facilitated by power sharing and small snubbers provide up to 25 dBuA reduction in CM conducted EMI. A comparison with CM chokes is also presented to validate improved attenuation in a wide frequency range. [ABSTRACT FROM AUTHOR]

This article evaluates silicon carbide (SiC) mosfet’s reliability and ruggedness comprehensively between two widely employed device package types: common source and Kelvin source. Multiple accelerated lifetime tests are conducted to comprehensively investigate SiC mosfet’s reliability at both package and die levels. Specifically, a conventional high electric field test is applied to induce gate oxide degradation, whereas package degradation is investigated by the widely adopted power cycling test. To mimic gate oxide degradation patterns closer to realistic cases, an active channel gate bias test is proposed in this study, and a fair comparison is made regarding the device's degradation pattern in the conventional high electric field test. Throughout accelerated lifetime tests, devices’ electrical parameters, consumable lifetime, and end-of-life failure modes are comprehensively evaluated. For ruggedness comparison, a single-shot short-circuit test is conducted on both common-source and Kelvin-source packaged devices with the same die technique and configuration. Other than analytical discussions with experimental waveforms, failure analysis is also conducted to investigate the device's failure mode and root cause. In respect of experimental results in accelerated lifetime tests and short-circuit tests, the existence of the common-source inductance and resistance may mitigate the electrothermal stress applied on the chip with lower gate–source voltage under load current and results in mitigated device instability and longer consumable lifetime. [ABSTRACT FROM AUTHOR]

This article evaluates the electromagnetic interference (EMI) caused by active neutral point clamped (ANPC) phase leg undergoing zero voltage switching (ZVS). ZVS, together with a high fundamental frequency operation is encountered in dual active bridge (DAB) converters. This allows ANPC phase leg to be operated in a different manner than its inverter counterpart. A comprehensive evaluation of four switching schemes for NPC/ANPC-DAB with regard to their EMI performance, voltage overshoot, and losses have been done. Switching state redundancies have been used to reduce the EMI of the ANPC phase leg. To further help in reduction of high frequency EMI and voltage overshoot, a low inductance busbar design has been presented for through-hole discrete devices. Finite element simulation and measurement results show a busbar inductance of 7.7 nH for long commutation loops. Finally, EMI performance (conducted and radiated) together with the busbar design has been experimentally validated for two of the most useful switching schemes. The switching schemes and the busbar design can boost adoption of NPC/ANPC-DAB by ensuring EMI compliance and improved efficiency without affecting the normal DAB operation or using additional hardware. [ABSTRACT FROM AUTHOR]

Gate-oxide degradation has been one of the major reliability challenges of SiC MOSFETs and should be monitored carefully to avoid unexpected power converter failures. Various precursors have been introduced in the literature for gate-oxide degradation monitoring. However, those proposed precursors are temperature dependent and it is highly challenging to eliminate temperature effects. In this article, two new temperature-independent precursors (Miller capacitance and gate–source capacitance changes) are proposed for gate-oxide degradation monitoring of SiC MOSFETs. During the accelerated aging tests under high electric field and high temperature, a consistent change in Miller capacitance and gate–source capacitance is reported for both common source and Kelvin source SiC MOSFETs. Also, the temperature sensitivity of each precursor is investigated. The proposed precursors enable the monitoring of gate-oxide degradation without decoupling the impact of package degradation. Based on the findings, a simple early warning in situ circuit is proposed to monitor gate-oxide aging. A comprehensive precursor comparison is provided to show the merits of the proposed precursors. Finally, the experimental results are presented to validate the efficacy of the in situ monitoring circuit. [ABSTRACT FROM AUTHOR]

Online junction temperature (Tj) measurement enables robust power converter operations by providing overtemperature protection and condition monitoring of the power devices. For SiC MOSFETs, the real-time (Tj) information is especially critical as limited field data are available regarding the reliability. In this article, utilizing the turn-on delay time as temperature sensitive electrical parameter, an online (Tj) measurement is realized through an intelligent gate drive. Specifically, the turn-on delay time is translated into the pulsewidth of a digital signal through the conditioning/logic circuits. During (Tj) measurements, the adjustable gate resistance circuit is activated to improve the measurement sensitivity beyond 600 ps/°C. Using the high-resolution capture module (300-ps resolution) in the system microcontroller, this pulsewidth is measured and then converted to junction temperature with a resolution of <0.5 °C. A prototype is built to validate the online (Tj) measurement method. The switching test results show that the circuit is able to precisely measure Td,on and offers a good linearity/sensitivity for (Tj) estimation. In the continuous operation, the junction temperature of a decapsulated device using an infrared camera and (Tj) obtained from the circuit match well with <1 °C difference under various operating conditions. In addition, the gate-oxide degradation's impact on Td,on is considered for SiC MOSFETs, and an aging compensation scheme is discussed to maintain the measurement accuracy throughout the device's lifetime. It is shown that the proposed circuit provides an accurate real-time (Tj) measurement for SiC MOSFETs, which can be deployed to improve the power converters’ reliability. [ABSTRACT FROM AUTHOR]

This article proposes a new complete condition monitoring method which can independently monitor both the threshold voltage drift and the packaging degradation accurately by monitoring only the reverse body diode voltage drop at different gate bias levels. The SiC MOSFETs are aged through an accelerated aging method and the corresponding changes in electrical parameters are periodically measured to assess their correlation with the state of the device's health. It has been revealed that the on-state resistance reveals the combination of gate oxide and package-related degradation while the threshold voltage mainly depicts gate oxide-related issues. Unlike these two parameters, the body diode voltage drop is found to independently indicate the state of device health both for package and gate oxide. This is caused by a unique secondary conduction mode of SiC MOSFETs in third-quadrant operation which is clearly disclosed with transition boundaries by a proposed body diode transfer characterization curve. In order to have a detailed condition information of the device with a simple circuit, monitoring the reverse body diode voltage drop at 0 and $-$ 5 V gate bias is proposed. The proposed condition monitoring method is implemented on a gate drive circuit and experimental results are given for two artificially degraded devices. The experimental results confirm that the proposed method can independently monitor both the gate oxide and packaging degradations accurately by monitoring a single precursor parameter. The proposed method can be integrated into the gate driver or converter itself to monitor SiC devices. [ABSTRACT FROM AUTHOR]

The temperature-sensitive electrical parameters (TSEPs) have been used in silicon carbide (SiC) mosfets junction temperature measurement for over-temperature protection and condition monitoring. However, the device aging can affect the TSEPs and thus leads to false ${\boldsymbol{T}}_{\boldsymbol{j}}$ measurement. In this article, the aging's impacts on various TSEPs are comprehensively investigated. Specifically, utilizing the dc power cycling test, both the gate oxide instability and package degradation are considered. Then the commercial devices with different structures are aged, and their temperature-dependent static and switching characteristics are evaluated at different aging cycles. Both the positive gate bias-induced threshold voltage shift and package degradation are observed, and their impacts on each TSEP are evaluated independently. Based on the evaluation results at various operating conditions, the temperature measurement errors due to different aging mechanisms are well summarized for each TSEP. From the dc power cycling test result, the package degradation's impact on TSEPs is found to be more significant than the gate oxide instability. It is pointed out that the aging's effect on TSEPs is an important factor that needs to be considered for accurate ${\boldsymbol{T}}_{\boldsymbol{j}}$ measurement in SiC mosfets. [ABSTRACT FROM AUTHOR]

In this article, an in situ SiC mosfet degradation monitoring method using readily available converter sensors is presented. Device's drain-source resistance in saturation and ohmic regions are employed as aging precursors to, respectively, indicate die and package-related degradations. The presented findings in this article are essential for low-cost and practical early warning systems in power electronics applications. To verify the effectiveness of the proposed method, a number of power-cycling tests are conducted to analyze aging process and fatigue mechanism. Device static parameters are measured throughout accelerated aging tests and the physical causes behind them are discussed in detail. It is shown that the drain-source resistance within saturation region at low gate bias can be used to indicate die-related degradation. Similarly, at full positive gate bias, device on-state drain-source resistance can be used to detect package-related degradation. In order to find out optimal variables such as applied gate bias, pulse duration, etc., a comprehensive single pulse test is conducted and the results are reported. Finally, the proposed degradation monitoring method is experimentally validated in the context of a three-phase inverter considering different sensor configurations and load types. [ABSTRACT FROM AUTHOR]

Silicon carbide (SiC) power mosfets are promising alternatives to Si devices in high-voltage, high-frequency, and high-temperature applications. The rapid and widespread deployment of SiC devices raises long-term reliability concerns, particularly for mission and safety critical systems due to limited field data and potential uncertainties. Therefore, it is essential to investigate progressive degradations and parameter shifts in SiC devices to develop system integrated degradation monitoring tools for self-monitoring converters, which can recognize failure precursors at the earliest stage and prevent catastrophic failures. This paper presents a comprehensive long-term reliability analysis of commercially available SiC mosfets under high temperature operation and high temperature swing, degradation related key precursors, and possible causes behind them. For this purpose, discrete SiC devices are power cycled and all datasheet parameters are recorded at certain intervals with the aid of the curve tracer. Variation of electrical parameters throughout the tests is presented in order to assess their correlation with the aging/degradation state of the switch. Among them, gate oxide charge trapping related threshold voltage drift and corresponding on state resistance variation has been observed for all samples. For some samples, bond wire heel cracking is found to be the root cause of sudden on state resistance and body diode voltage increases. The discussions regarding aging precursors are supported by failure analysis obtained through the decapsulation of failed devices. Finally, the findings are evaluated in order to define the suitability of electrical parameters as an aging precursor parameter under the light of practical implementation related issues. [ABSTRACT FROM AUTHOR]

This paper presents a comprehensive study on degradation monitoring of silicon carbide mosfets and proposes an early warning method to detect aging. The proposed plug-in tool can be integrated to smart gate drivers or directly to power converters. During the accelerated aging tests (power cycling within safe operating area), several electrical parameters are monitored to find out critical signatures and precursors of failure. Among those, gate leakage current is identified as the most practical precursor, which exhibits consistent changes in all aged devices and is relatively easy to monitor. Due to its simple scheme and low cost, it can potentially be embedded into commercial gate drivers featuring improved reliability options. [ABSTRACT FROM AUTHOR]

Thermal/power cycles are widely acknowledged methods to accelerate the package related failures. Many studies have focused on one particular aging precursor at a time and continuously monitored it using custom-built circuits. Due to the difficulties in taking sensitive measurements, the reported findings are more on the quantities requiring less sensitive measurements. In this paper, two custom-designed testbeds are used to age a number of power MOSFETs and insulated gate bipolar transistors. An automated curve tracer is utilized to capture parametric variations in I–V curves, parasitic capacitances, and gate charges at certain time intervals. The results suggest that the only viable aging precursors are the on-state voltage drop/on-state resistance, body diode voltage drop, parasitic capacitances, and gate threshold voltage for die attach solder and gate-oxide degradation mechanisms. Based on the experimental results, gate threshold voltage variation is empirically modeled to estimate the remaining useful lifetime of the switches experiencing gate oxide degradation. The model parameters are found by the least squares method applied to inliers determined by the random sample and consensus outlier removal algorithm. [ABSTRACT FROM AUTHOR]

The efforts for more reliable power conversion systems have been gaining momentum in recent years. The majority of the studies concerning reliability of power switches focus on the package-related failures, mainly caused by the cyclic thermal stress. The basic failure precursor for this type of stress has been identified as increased on-state resistance for power MOSFETs in the recent literature. On-state resistance monitoring during converter operation is a challenging and costly task as it requires current and voltage sensing circuits, which can block the high voltage across the switch during off-state to protect the measurement or control unit. This paper proposes a software frequency response analysis method to determine the health status of high-voltage power MOSFETs with high on-state resistance. This is achieved by analyzing and evaluating the variation in the plant model at double pole frequency using the same DSP that is used for control purposes. The proposed concept is analyzed for boost converter; however, it can be used to detect the on-state resistance variation in other types of converters operating in continuous condition mode (CCM). The proposed algorithm is embedded in a low cost DSP and experimentally verified on a dc/dc boost converter. [ABSTRACT FROM AUTHOR]

The research on noninvasive incipient fault diagnosis of power converters is very critical to avoid strenuous periodic checkups and costly interruptions. In many of the research studies, on-state resistance of power MOSFETs is identified as the fault precursor, and suggested to be monitored online for prognosis. In this paper, a condition monitoring algorithm is proposed for power MOSFETs of interleaved converters and integrated with the conventional current loops. The proposed technique utilizes on-state resistance information of the switches to adjust the current reference of each interleaving leg. In addition, a pulse-width adjustment method is proposed to avoid one current sensor and current-control loop. With the proposed scheme, the thermal stress on the aged device can be reduced, and the overall lifetime of the converter can be extended. The proposed approach is verified on two-leg interleaved converters both in simulation and experimentally. [ABSTRACT FROM AUTHOR]

The research on noninvasive incipient fault diagnosis of power converters is very critical to avoid strenuous periodic check-ups and costly interruptions. Thermal cycling is one of the main techniques to accelerate the package-related failure progress. In this paper, first, a custom designed accelerated aging platform that can expose multiple discrete power MOSFETs to thermal stress simultaneously is introduced. Based on the collected experimental data, the variation of the on-state resistance is identified as the failure precursor, and an exponential degradation model that fits successfully with the experimental data are developed. The remaining useful lifetime (RUL) of degraded power MOSFETs is estimated through classical least-squares algorithm run on experimental data filtered by Kalman Filter which deals with the measurement noise and model uncertainties. The essential advantage of the proposed method is that it does not require junction temperature information. The RUL estimation with limited field data is demonstrated on a number of experimental results. [ABSTRACT FROM PUBLISHER]