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This article reports on logic and memory functionality of vertically stacked bidirectional junctionless (BiJL) transistor, which can be operated as nMOS or pMOS depending on the biases applied. An inverter can be realized with a single BiJL transistor. If a complement of inputs is available, then NAND, NOR, and XOR logic can also be realized through a single BiJL transistor. The thickness of separation oxide between n-type and p-type films can be utilized to either achieve hysteresis or the absence of the same. Results provide insights into device physics, operation, and showcase new viewpoints for designing logic and memory devices with vertically stacked JL architecture, thus achieving the desired functionality with a lesser number of transistors. [ABSTRACT FROM AUTHOR]

This paper reports on the detection of hydrogen (H2) gas by utilizing a gate-all-around nanowire (NW) junctionless (JL) transistor as a sensor. The effects of temperature and pressure are considered in the transduction process through a change in gate workfunction of palladium (Pd) gate after exposure to $H_{2}$ gas. The analysis is performed through TCAD simulations, and an analytical model is developed in the subthreshold regime of device operation at a relatively low drain bias of 0.5 V. The performance of the NW JL transistor gas sensor is evaluated through the OFF-current-based sensitivity ($S_{I}$) and sensitivity based on threshold voltage shift ($S_{V}$). The analytical model developed for $S_{I}$ and $S_{V}$ shows a very good consistency with simulation data. The anomalous behavior of threshold voltage with temperature in the NW JL transistor under the influence of $H_{2}$ gas is analyzed in detail. This paper predominantly focuses on utilizing the NW JL transistor for low-power gas sensing, specifically at low pressures (10−15–10−10 torr), for temperatures ranging from 250 to 450 K. Insights into physical mechanisms within the device due to the transduction process are highlighted for optimum sensing. [ABSTRACT FROM AUTHOR]

In this paper, we propose a model for estimating short-channel effects (SCEs) in the shell-doped double-gate junctionless (JL) MOSFET. The main emphasis of this paper is to estimate SCEs by effectively capturing source/drain (S/D) extensions beyond the gate edges for different values of undoped core thickness (${T}_{\textsf {core}}$), shell doping (${N}_{\textsf {d}}$), gate length (${L}_{\textsf {g}}$), and gate (${V}_{\textsf {gs}}$) and drain (${V}_{\textsf {ds}}$) biases in subthreshold regime. The threshold voltage (${V}_{\textsf {th}}$), drain-induced barrier lowering and subthreshold swing (${S}$), extracted from transfer characteristics, are in good agreement with the simulation results. Results highlight the utility of shell doping and core thickness to provide an additional degree of freedom to control SCEs. The proposed model can be useful in estimating SCEs and optimizing core–shell JL architecture for low-power applications. [ABSTRACT FROM AUTHOR]

This paper reports on the usefulness of shell-doped (SD) junctionless (JL) transistor architecture for operation as capacitorless dynamic random-access memory (1T-DRAM). SD topology overcomes the problem associated with shallower potential depth in heavily doped devices, thereby enhancing the retention time (RT) along with improved scalability. The use of a thinner shell for achieving high RT is beneficial as it reduces generation and recombination of holes. The results show that an undoped core region with shell thickness (${T}_{\textsf {Shell}}$) of 2 nm yields maximum retention. An SD (${N}_{\mathrm {d}}$) of $10^{18}$ cm $^{-\textsf {3}}$ attains RT of ~5.5 s and ~630 ms at 27 °C and 85 °C, respectively, whereas higher ${N}_{\textsf {d}}$ ($10^{19}$ cm $^{-\textsf {3}}$ shows RT of ~13ms at 85 °C for ${L}_{\textsf {g}} = \textsf {200}$ nm. SD JL transistor shows less degradation in RT with temperature. A 10 nm SD JL device with RT of ~11 ms at 85 °C demonstrates applicability as 1T-DRAM at shorter gate lengths. [ABSTRACT FROM AUTHOR]

This paper proposes a semianalytical model to estimate short-channel effects for independent gate operation in double-gate (DG) junctionless (JL) MOSFET incorporating gate-to-source/drain underlap, through the solution of Poisson’s equations in the subthreshold regime. The model also accounts for the asymmetry in device operation through variation in gate oxide thicknesses, gate work functions, and underlap lengths. Subthreshold drain current, threshold voltage, and subthreshold swing, evaluated from the channel potential, show reasonable agreement with simulation data. Results suggest the use of negative back gate bias and longer underlap length to reduce off-current. This paper highlights the role of doping, underlap length, and back gate bias in tuning the threshold voltage. This model serves as a generic formulation (within limits) with different asymmetries to estimate, design, and optimize self-aligned DG JL transistors for subthreshold logic applications. [ABSTRACT FROM AUTHOR]

This paper reports on the suppression of single-transistor latch, an extreme condition of impact ionization (I.I.), in n-type double-gate germanium (Ge) junctionless (JL) transistors. It is shown that JL transistors can be latched to the on-state due to an increase in the I.I. generated power per unit volume with an increase in drain bias, film thickness, oxide thickness, and doping. Latch, being detrimental to switching, can be effectively suppressed by applying an appropriate negative (positive) back-gate bias for n-type (p-type) JL MOSFET. The independent gate operation with appropriate back bias allows the device to overcome latching and regain switching action with a subthreshold swing (${S}$ -swing) <10 mV/decade at room temperature. The work showcases the limit imposed on back bias due to an increase in off-state current due to band-to-band tunneling along with the utility of sidewall spacer to effectively suppress the same. We also show the tunability of hysteresis using back-gate bias. The work highlights a systematic methodology to eliminate single-transistor latch while preserving sub-60 mV/decade switching in Ge JL MOSFETs. [ABSTRACT FROM AUTHOR]

This paper reports the significance of device architecture to enhance impact ionization (I.I.) resulting in steep increase in the current from OFF- to ON-state. Recognizing that the area over which I.I. occurs is a key factor governing impact generated power per unit volume in the semiconductor film, we use raised source/drain (RSD) architecture to achieve sub-60-mV/decade subthreshold swing (S-swing) in germanium (Ge) junctionless (JL) devices at drain bias ( ${V}_{\text {ds}}$ ) of 0.9 V. The performance of RSD Ge JL device is compared with double-gate Ge JL transistor to highlight the occurrence of subthermal S-swing <5 mV/decade in RSD topology. The impact of band-to-band tunneling (BTBT) on the switching characteristics shows that RSD JL device with relatively thicker side oxide can effectively suppress BTBT while enhancing I.I. The influence of parasitic capacitance due to RSD regions and vertical doping gradient is also analyzed. Results highlight new viewpoints for the design of RSD Ge JL MOSFETs with channel doping $({N}_{\text {ch}}) \ge {5}\times {10}^{18}$ cm−3 to facilitate sharp current transition. [ABSTRACT FROM AUTHOR]

In this paper, we report on the reduction of the off-state band-to-band tunneling (BTBT) while maintaining sub-60 mV/decade switching in Germanium (Ge) Junctionless (JL) transistor through well-calibrated simulations. Recognizing the product of current density ( J ) and electric field ( E ) to be the key generic parameter governing device optimization, it is shown that a device with thicker film operated at lower drain bias ( V\text {ds} ) can sustain impact ionization and limit BTBT, thereby balancing the conflicting requirements of J\cdot E for tunneling and impact ionization. An optimal workfunction and gate-to-drain underlap of 5 nm in Ge JL MOSFET can further suppress BTBT while achieving a subthreshold swing of ~5 mV/decade with nearly four decades of steep current transition at the threshold voltage along with a low off-current ( \text 10^\text -10$}}\text{A}$ ) at {V}_{\text {ds}} = \text {0.9} V. Results highlight new viewpoints for the design optimization of steep-switching Ge JL MOSFETs. [ABSTRACT FROM PUBLISHER]

In this paper, we report on the anomalous behavior of threshold voltage ( V \sf th) with temperature in junctionless (JL) transistors. It is shown that both positive and negative values of temperature coefficient of threshold voltage (dV \sf th /dT) in nMOS Si and Ge JL devices can occur at higher drain biases. At lower temperatures, V \sf th reduces with a decrease in temperature due to the dominance of bipolar effects over thermal generation of carriers, whereas at higher temperatures, thermal generation results in essentially unipolar characteristics, and V \sf th reduces with increase in temperature. It is also shown that zero temperature coefficient condition shall be nonexistent under dominant bipolar conduction over unipolar operation. Results show new viewpoints to understand the two contrasting physical mechanisms leading to positive and negative dV \sf th /dT values in JL devices. [ABSTRACT FROM AUTHOR]

• 2 Transistor negative capacitance inverter requires less transistor count to exhibit hysteresis. • Hybrid Schmitt trigger configurations suffer from difference in NDR and strengths of n- and p-sub-circuits. • Accurate approach to model hysteresis window and minimum supply voltage has been developed. • MFMIS NCFETs can lower the V dd requirement for sustaining hysteresis in Schmitt trigger. • Negative capacitance FET based Schmitt trigger outperforms other topologies because of enhanced feedback made possible through a higher on-to-off current ratio. Through an analytical framework, the work showcases the potential benefits of Metal-Ferroelectric-Metal-Insulator-Semiconductor (MFMIS) negative capacitance (NC) transistor (T) to enhance the hysteresis width (Δ V H) and reduce the minimum supply voltage (V dd,min) of ultra low power (ULP) subthreshold Schmitt trigger (ST) at shorter gate lengths. Analyzing different ST configurations i.e. 2T (both NCFET), 4T-hybrid (realized through combination of NCFETs and MOSFETs), and 6T (all NCFETs or MOSFETs), leads to the inferences that (i) an inherent negative differential resistance of NCFET can be utilized for hysteresis in 2T-ST circuit, (ii) 4T-hybrid ST is not beneficial for enhancing Δ V H due to a current mismatch between MOSFET and NCFET, and (iii) an optimized 2T-ST and 6T-ST designed with high-permittivity (κ) sidewall spacer (Si 3 N 4) and ferroelectric layer (6 nm) can function at V dd,min of ∼ 55 mV, and ∼ 39 mV, respectively. Results indicate towards potential benefits of realizing ULP subthreshold ST through MFMIS NCFETs without any circuit overhead. [ABSTRACT FROM AUTHOR]